CN221007789U - FPGA core board IO port detection circuit and detection tooling - Google Patents

Abstract

The utility model relates to an FPGA core board IO port detection circuit, comprising: a data selection subcircuit (1), connected to the IO port of the FPGA core board (2) under test; an indication subcircuit (3), connected to the data selection subcircuit (1), used to indicate the high/low level state of the IO port; a counting subcircuit (4), respectively connected to a signal source and the indication subcircuit (3). Compared with the prior art, the timing subcircuit of the utility model is connected to the data selection subcircuit, and can select the FPGA core board IO port under test, and finally display the high and low level states of the current IO port through the indication subcircuit, and the tester can judge whether there is a fault by observing the high and low level states of the current IO port.

Description

FPGA core board IO port detection circuit and detection tooling

Technical Field

The utility model relates to the technical field of detection circuits, in particular to an FPGA core board IO port detection circuit and a detection tool.

Background technique

With the development of integrated circuit technology, the integration of chips is getting higher and higher, and the workload of chip testing is also increasing accordingly. FPGA (Field-Programmable Gate Array) is increasingly used in complex circuits due to its reprogrammability and high flexibility. Its stability is an important factor in ensuring the operation of the circuit. FPGA IO (Input/Output) port fault detection is one of the important steps to ensure the normal operation of FPGA. Previous tests relied on testers to use instruments such as signal generators, multimeters and oscilloscopes to perform tests. The following are several common background technologies:

Port scanning: This technique scans each IO port one by one and reads its status to detect possible faults. For example, the JTAG interface can be used to scan the IO port and the scan result can be compared with the expected value to determine whether there is a fault. This method requires additional equipment with a control chip, which is costly.

Voltage and current testing: By measuring the voltage and current of each port on the chip, it is possible to determine whether there is a short circuit, open circuit or other electrical fault. This can be achieved by using a multimeter or oscilloscope, but it is inefficient to test one port at a time.

Visual inspection: By visually inspecting the physical state of components such as pads, pins, and connectors on the chip, it can be determined whether there is looseness, damage, or other mechanical failures. These techniques usually need to be used in combination to ensure that FPGA IO port failures are reliably detected. This test method has low test efficiency and slow speed and cannot achieve large-scale and large-volume testing.

Some existing FPGA core board IO port detection can only perform single IO port detection, and the circuit connection needs to be changed after each detection, which is very inconvenient.

Therefore, there is currently a lack of an FPGA core board IO port detection circuit so that operators can easily and quickly check the FPGA chip IO port, thereby avoiding obstruction of board-level verification or interference problem location due to FPGA chip failure.

Utility Model Content

The purpose of the utility model is to provide an FPGA core board IO port detection circuit and detection tooling in order to overcome the defects of the above-mentioned prior art.

The purpose of the utility model can be achieved through the following technical solutions:

One aspect of the utility model provides an FPGA core board IO port detection circuit, comprising:

The data selection subcircuit is connected to the IO port of the FPGA core board under test;

An indication subcircuit, connected to the data selection subcircuit, for indicating a high/low level state of the IO port;

The counting subcircuit is connected to the signal source and the indicating subcircuit respectively.

As a preferred technical solution, it also includes:

A strobe switch, a common end of which is connected to the counting subcircuit, and two strobe ends of which are respectively connected to the waveform generator and the manual trigger subcircuit, and the waveform generator and/or the manual trigger subcircuit serve as the signal source.

As a preferred technical solution, the counting subcircuit includes:

A counter chip, wherein a counting output terminal is connected to the data selection subcircuit, and a trigger terminal is connected to the common terminal of the gating switch;

The NAND gate has an input end that is the counting output end of the counter chip and an output end that is connected to the reset end of the counter chip.

As a preferred technical solution, the manual trigger subcircuit includes:

A button is connected to a selection end of the selection switch.

As a preferred technical solution, the button is an Omron touch button.

As a preferred technical solution, the data selection subcircuit includes multiple data selector chips, the data input end of the data selector chip is connected to the IO port of the FPGA core board under test, the data output end is connected to the indication subcircuit, and the counting input end is connected to the counting subcircuit.

As a preferred technical solution, the multiple data selector chips are arranged in parallel, and the data selector chip is an 8-way data selector chip.

As a preferred technical solution, the indication subcircuit includes:

LED light, one end is connected to the power supply;

The transistor has a collector connected to the other end of the LED lamp, a base connected to the data selection subcircuit, and an emitter connected to the ground.

As a preferred technical solution, it also includes:

The power supply sub-circuit is connected to the FPGA core board under test and the counting sub-circuit respectively.

Another aspect of the utility model provides a detection tool, including a mounting seat matching the FPGA core board to be tested and the above-mentioned FPGA core board IO port detection circuit.

Compared with the prior art, the utility model has the following advantages:

Realize flexible detection of multiple IO ports: The timing subcircuit of the present application is connected with the data selection subcircuit, which can select the FPGA core board IO port currently being tested, and finally display the high and low level status of the current IO port through the indication subcircuit. The tester can judge whether there is a fault by observing the high and low level status of the current IO port.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of an FPGA core board IO port detection circuit in an embodiment;

FIG2 is a schematic diagram of a gate switch and a manual trigger subcircuit in an embodiment;

FIG3 is a schematic diagram of a counting subcircuit in an embodiment;

FIG4 is a schematic diagram of a data selection subcircuit in an embodiment;

FIG5 is a schematic diagram of an indication subcircuit in an embodiment,

Among them, 1. data selection subcircuit, 101. data selector chip, 2. FPGA core board, 3. indication subcircuit, 301. LED light, 302. transistor, 4. counting subcircuit, 401. counter chip, 402. NAND gate, 5. selection switch, 6. waveform generator, 7. manual trigger subcircuit, 701. button, 8. power supply subcircuit.

Detailed ways

The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, not all of them. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the utility model.

Example 1

Referring to FIG. 1 , this embodiment provides an FPGA core board IO port detection circuit, including

The data selection subcircuit 1 is connected to the IO port of the FPGA core board 2 under test;

The indication sub-circuit 3 is connected to the data selection sub-circuit 1 and is used to indicate the high/low level state of the current corresponding IO port;

The counting subcircuit 4 is connected to the signal source and the indicating subcircuit 3 respectively, and changes the built-in counting value by changing the signal source level, thereby selecting different IO port levels to output to the indicating subcircuit 3.

3 is a schematic diagram of a counting subcircuit 4, comprising:

The counter chip 401 has a counting output terminal connected to the data selection sub-circuit 1 and a trigger terminal connected to the signal source;

The NAND gate 402 has an input terminal that is the counting output terminal of the counter chip 401 , and an output terminal that is connected to the reset terminal of the counter chip 401 .

The data selection subcircuit 1 includes a plurality of data selector chips 101 (8 in the present embodiment) arranged in parallel, and referring to FIG4 for a schematic diagram of one of the data selector chips 101, the data input end of the data selector chip 101 is connected to the IO port of the FPGA core board 2 under test, the data output end is connected to the indication subcircuit 3, and the counting input end is connected to the counting subcircuit 4. In the present embodiment, the data selector chip 101 adopts an 8-way data selector chip. The remaining 7 data selector chips 101 are similar in connection mode except that the IO ports of the connected FPGA core boards are different.

5 is a schematic diagram of the indication subcircuit, the indication subcircuit 3 includes: an LED lamp 301, one end of which is connected to the power supply, and the other end is connected to the collector of a transistor 302, the base of the transistor 302 is connected to the data selection subcircuit 1, and the emitter is grounded.

The power supply sub-circuit 8 is connected to the FPGA core board 2 under test and the counting sub-circuit 4 respectively. In this embodiment, the input voltage is DC12V, and a 12V to 5V power supply chip and peripheral circuits are used to realize power supply.

Example 2

Referring to FIG. 1 , based on Example 1, the FPGA core board IO port detection circuit of this embodiment further includes:

The connection relationship of the selection switch 5 is shown in Figure 2. The common end is connected to the counting sub-circuit 4, and the two selection ends are respectively connected to the waveform generator 6 and the manual trigger sub-circuit 7. The waveform generator 6 and/or the manual trigger sub-circuit 7 serve as signal sources. At this time, the trigger end of the counter chip 401 is connected to the common end of the selection switch 5.

Referring to FIG. 2 , the manual trigger subcircuit 7 includes:

The button 701 is connected to an enabling terminal of the enabling switch 5 .

In this embodiment, the button 701 is an Omron touch button. Preferably, the periphery of the button 701 uses a debouncing and anti-static circuit.

The working principle of the FPGA core board IO port detection circuit is:

The operator first connects the IO port to be tested on the FPGA core board 2 to the data selection subcircuit 1. In this embodiment, the 88 IO ports of the FPGA core board are tested, and the 88 IO ports are connected to 8 data selector chips 101 respectively. Then, the signal source is set through the selection switch 5. The signal source can be a waveform generator 6 or a manual trigger subcircuit 7. The level change generated by the signal source will cause the count value in the counter chip 401 in the counting subcircuit 4 to change, thereby changing the IO port selected by the data selection subcircuit 1. The selected IO port indicates the on and off of the IO port by turning on and off the LED light 301 in the indication subcircuit 3. The setting of the NAND gate 402 can form a counter with the counter chip 401 to ensure that the counting subcircuit 4 can count cyclically.

By setting a selection switch, the present application allows testers to flexibly select automatic triggering and manual triggering according to actual test needs. Under automatic triggering, the waveform generator generates a trigger signal, and under manual triggering, the trigger signal is manually generated. The trigger signal enters the counting subcircuit to realize counting and connect the next IO port.

Example 3

The present embodiment provides a detection tool, including a mounting seat matching the FPGA core board 2 to be tested and the FPGA core board IO port detection circuit as described in the above embodiment 1 or embodiment 2. The detection tool provided in the present embodiment can save the connection process between the IO port of the FPGA core board 2 and the data selection subcircuit 1, and the connection can be completed by directly fixing the FPGA core board 2 on the mounting seat. The FPGA core board 1 is inserted into the mounting seat, and the level of the core board IO port can be intuitively judged according to the display of the LED light 301.

The above is only a specific implementation of the utility model, but the protection scope of the utility model is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the utility model, and these modifications or replacements should be included in the protection scope of the utility model. Therefore, the protection scope of the utility model should be based on the protection scope of the claims.

Claims (10)

1. An FPGA core board IO port detection circuit, which is characterized by comprising:

The data selection subcircuit (1) is connected with an IO port of the FPGA core board (2) to be tested;

An indication sub-circuit (3) connected with the data selection sub-circuit (1) and used for indicating the high/low level state of the IO port;

and the counting sub-circuit (4) is respectively connected with the signal source and the indicating sub-circuit (3).

2. The FPGA core board IO port detection circuit of claim 1, further comprising:

The public end of the gating switch (5) is connected with the counting sub-circuit (4), the two gating ends are respectively connected with the waveform generator (6) and the manual triggering sub-circuit (7), and the waveform generator (6) and/or the manual triggering sub-circuit (7) are/is used as the signal source.

3. An FPGA core board IO port detection circuit according to claim 2, wherein said counting sub-circuit (4) comprises:

A counter chip (401), wherein a counting output end is connected with the data selection subcircuit (1), and a trigger end is connected with a common end of the gating switch (5);

And the input end of the NAND gate (402) is a counting output end of the counter chip (401), and the output end is connected with a zero clearing end of the counter chip (401).

4. An FPGA core board IO port detection circuit according to claim 2, wherein said manual triggering sub-circuit (7) comprises:

And the key (701) is connected with one gating end of the gating switch (5).

5. The FPGA core panel IO port detection circuit of claim 4, wherein said key (701) is an Omron touch key.

6. The circuit for detecting the IO port of the FPGA core board according to claim 1, wherein the data selection sub-circuit (1) comprises a plurality of data selector chips (101), a data input end of each data selector chip (101) is connected with the IO port of the FPGA core board (2) to be detected, a data output end is connected with the indicating sub-circuit (3), and a counting input end is connected with the counting sub-circuit (4).

7. The FPGA core panel IO port detection circuit of claim 6, wherein the plurality of data selector chips (101) are arranged in parallel, and the data selector chips (101) are 8-way data selector chips.

8. The FPGA core board IO port detection circuit according to claim 1, wherein said indicator sub-circuit (3) comprises:

an LED lamp (301), one end of which is connected with a power supply;

And the collector electrode of the triode (302) is connected with the other end of the LED lamp (301), the base electrode of the triode is connected with the data selection subcircuit (1), and the emitter electrode of the triode is grounded.

9. The FPGA core board IO port detection circuit of claim 1, further comprising:

And the power supply sub-circuit (8) is respectively connected with the tested FPGA core board (2) and the counting sub-circuit (4).

10. A detection tool, which is characterized by comprising a mounting seat matched with a tested FPGA core board and the FPGA core board IO port detection circuit according to any one of claims 1-9.