CN221239610U

CN221239610U - Width compact semiconductor packaging structure

Info

Publication number: CN221239610U
Application number: CN202323074599.7U
Authority: CN
Inventors: 陈君飞; 李圣均
Original assignee: Giantec Semiconductor Corp
Current assignee: Giantec Semiconductor Corp
Priority date: 2023-11-14
Filing date: 2023-11-14
Publication date: 2024-06-28
Anticipated expiration: 2033-11-14

Abstract

The present utility model provides a variety of width compact semiconductor package structures, comprising: a package substrate in the shape of a rectangle including long sides and narrow sides; a plurality of bonding pads which are arranged in a staggered manner and/or symmetrically along a narrow-side symmetrical axis of the packaging substrate; each bonding pad is in a cutting circular shape; the cutting circle at least comprises a longitudinal section, and the longitudinal section is adjacent and parallel to the long side of the packaging substrate. The utility model has the advantages of small width of the packaging structure, good stability and large accommodating space.

Description

Width compact semiconductor packaging structure

Technical Field

The utility model relates to the field of semiconductor packaging, in particular to a width compact type semiconductor packaging structure.

Background

Because the camera on the mobile phone adopts a cmos (complementary metal oxide semiconductor) image sensor with larger size, the size of the camera module of the mobile phone still needs to keep the original size or be as small and light as possible. Therefore, on the premise of not increasing the volume of the whole mobile phone camera module, the occupied space of other components in the mobile phone camera module is provided with higher compression requirements. Based on the restriction in narrow space, the shape of the anti-shake driver chip with the position sensor arranged inside the mobile phone camera module is narrow and long, so that the occupied volume of the anti-shake driver chip is smaller, and more vacancies are formed in the chip, so that more sensors or other components can be loaded, and on the premise of ensuring reliability, a novel semiconductor packaging structure is needed to meet the application of the chip in special occasions in the narrow space.

Disclosure of utility model

The utility model aims to provide a semiconductor packaging structure with compact width, which has the advantages of small packaging structure width, good stability and large accommodating space.

To achieve the above object, the present utility model provides a width-compact semiconductor package structure, comprising: a package substrate in the shape of a rectangle including long sides and narrow sides; the bonding pads are sequentially arranged on two sides of the narrow-side symmetry axis of the packaging substrate in a crossing mode, and two adjacent bonding pads are arranged in a staggered mode along the narrow-side symmetry axis of the packaging substrate; each bonding pad is in a cutting circular shape; the cutting circle at least comprises a longitudinal section, and the longitudinal section is adjacent and parallel to the long side of the packaging substrate.

Preferably, the projection distance of the center distances of two adjacent bonding pads on the narrow side of the packaging substrate is greater than or equal to the minimum packaging distance d _min.

Preferably, the included angle of the two adjacent bonding pads is theta, and theta epsilon (0,90 degrees); or projections of the adjacent two bonding pads on the long side of the packaging substrate are not overlapped with each other.

Preferably, the distance d _v＝n₁×r_u from the center of the pad to the longitudinal section of the pad is n ₁, r _u is the radius of the pad, and n ₁ epsilon (0, 1).

Preferably, the bonding pad adjacent to the narrow side of the package substrate is a fan-shaped bonding pad, and the fan-shaped bonding pad further comprises a transverse section, and the transverse section is parallel to the narrow side of the package substrate.

Preferably, the distance d _v＝n₁×r_su from the center of the fan-shaped bonding pad to the longitudinal section of the fan-shaped bonding pad is equal to n ₁, r _su is equal to the radius of the fan-shaped bonding pad, and n ₁ epsilon (0, 1); the distance d _h＝n₂×r_su from the center of the fan-shaped bonding pad to the transverse section of the fan-shaped bonding pad is equal to n ₂, r _su is equal to the radius of the fan-shaped bonding pad, and n ₂ epsilon (0, 1).

Preferably, the semiconductor package structure further comprises at least one sensor; the sensor is arranged at the vacancy of the other side of the narrow-side symmetry axis corresponding to any bonding pad.

The present utility model provides yet another width-compact semiconductor package structure, comprising: a package substrate in the shape of a rectangle including long sides and narrow sides; a plurality of pad groups arranged on the surface of the package substrate along the long-side array of the package substrate; each bonding pad group comprises two bonding pads, and the two bonding pads are symmetrically arranged along the symmetry axis of the narrow side of the packaging substrate; and each bonding pad is in a cutting round shape; the cutting circle at least comprises a longitudinal section, and the longitudinal section is adjacent and parallel to the long side of the packaging substrate.

Preferably, the center-to-center distance of two pads symmetrically arranged in the pad group is greater than or equal to the minimum packaging distance d _min.

Preferably, the semiconductor package structure further comprises at least one sensor; the sensor is arranged at the middle position of any two adjacent bonding pad groups.

The present utility model provides a semiconductor package structure having a compact width, comprising: a package substrate in the shape of a rectangle including long sides and narrow sides; at least two first bonding pad groups, wherein each first bonding pad group comprises two first bonding pads symmetrically arranged along the symmetry axis of the narrow side of the packaging substrate; the second bonding pad group comprises at least two second bonding pads which are arranged in a staggered manner along the symmetry axis of the narrow side of the packaging substrate; each first bonding pad group is arranged on the surface of the packaging substrate along the long-side array of the packaging substrate; each second bonding pad group is correspondingly arranged between every two adjacent first bonding pad groups; each bonding pad is in a cutting circular shape; the cutting circle at least comprises a longitudinal section, and the longitudinal section is adjacent and parallel to the long side of the packaging substrate.

Preferably, the center distance between two first pads symmetrically arranged in the first pad group is greater than or equal to the minimum packaging distance d _min.

Preferably, the included angle of two adjacent second bonding pads arranged in a staggered manner in the second bonding pad group is θ, θ∈ (0,90 °); or projections of two adjacent second bonding pads arranged in a staggered manner in the second bonding pad group on the long edge are not overlapped with each other.

Preferably, a distance d _v＝n₁×r_u from the center of each pad to its longitudinal section, where n ₁ is a packaging coefficient, r _u is the pad radius, n ₁ e (0, 1).

Preferably, adjacent to the narrow side of the package substrate is a first pad, which is a fan-shaped pad, and the fan-shaped pad further includes a transverse section, and the transverse section is parallel to the narrow side of the package substrate.

Preferably, the semiconductor package structure further comprises at least one sensor; the sensor is arranged at a vacancy of the second bonding pad group where the second bonding pad is not arranged.

In summary, compared with the prior art, the width compact semiconductor packaging structure provided by the utility model has the following beneficial effects: (1) The shape of the bonding pad is set to be a cutting circle, so that the width of the bonding pad is reduced, the width of the packaging substrate is further reduced, and the narrow-side design of the semiconductor packaging structure is realized; (2) The bonding pads symmetrically arranged along the narrow-side symmetry axis of the packaging substrate are arranged, so that the welding stress borne by the packaging substrate is balanced, the influence of the welding stress on the packaging substrate is reduced, and the stability of the packaging structure is improved; (3) Through setting up the pad of following the narrow limit symmetry axis dislocation set of encapsulation base plate, increased the vacancy on the encapsulation base plate, make sensor or other parts can nimble install in corresponding vacancy, and can not increase the narrow limit width and the long limit length of encapsulation base plate, realized semiconductor packaging structure's miniaturization.

Drawings

FIG. 1 is a schematic diagram of a compact-width semiconductor package 100 according to one embodiment of the present utility model disposed within a camera module;

FIG. 2 is a schematic diagram of a conventional wafer level package structure;

fig. 3 is a schematic view of a width-compact semiconductor package according to a first embodiment of the present utility model;

FIG. 4 is a schematic view of another width-compact semiconductor package according to the first embodiment of the present utility model;

fig. 5 is a schematic diagram of a width-compact semiconductor package according to a second embodiment of the present utility model;

fig. 6 is a schematic diagram of another width-compact semiconductor package according to the second embodiment of the present utility model;

fig. 7 is a schematic view of a width-compact semiconductor package according to a third embodiment of the present utility model;

Fig. 8 is a schematic diagram of another width-compact semiconductor package according to the third embodiment of the present utility model.

Detailed Description

The technical scheme, constructional features, achieved objects and effects of the embodiments of the present utility model will be described in detail below with reference to fig. 1 to 8 in the embodiments of the present utility model.

It should be noted that, the drawings are in very simplified form and all use non-precise proportions, which are only used for the purpose of conveniently and clearly assisting in describing the embodiments of the present utility model, and are not intended to limit the implementation conditions of the present utility model, so that the present utility model has no technical significance, and any modification of structure, change of proportion or adjustment of size, without affecting the efficacy and achievement of the present utility model, should still fall within the scope covered by the technical content disclosed by the present utility model.

It is noted that in the present utility model, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

The compact-width semiconductor package structure 100 according to the present utility model is applied to the camera module 2 mounted on the portable terminal 1 such as the smart phone and the mobile phone shown in fig. 1. It should be understood that the width-compact semiconductor package structure 100 provided by the present utility model is not limited to application to the portable terminal 1, and furthermore, the width-compact semiconductor package structure 100 provided by the present utility model is not limited to application to the camera module 2 in the portable terminal 1.

Conventional wafer level package structure as shown in fig. 2, the conventional package structure 200 includes a conventional package substrate 201 and a plurality of circular pads 202 disposed on a surface array thereof, and the circular pads 202 are used for carrying solder balls. The width wt of the conventional package substrate 201 is limited by the diameter d1 of the circular pads 202 and the distance d2 between the centers of the adjacent two circular pads 202. Specifically, as shown in fig. 2, the minimum width of the package substrate 201 in the conventional package structure 200 is limited to wt > d 1/2+d2+d1/2=d1+d2. On the premise of the minimum width limitation, the width wt of the conventional packaging structure 200 cannot meet the trend that the mounting space reserved by the camera module 2 is narrower and narrower, so the utility model provides three kinds of width compact semiconductor packaging structures.

Example 1

Fig. 3 is a schematic diagram of a width-compact semiconductor package 100 according to a first embodiment of the present utility model, where the width-compact semiconductor package 100 includes: a package substrate 101 having a rectangular shape including long sides and narrow sides, so that the package substrate 101 can be accommodated in a narrow and long space at the edge of the camera module 2; the bonding pads 121 are sequentially and crosswise arranged at two sides of a narrow-side symmetry axis A-A of the package substrate 101, and two adjacent bonding pads 121 are arranged in a staggered manner along the narrow-side symmetry axis A-A of the package substrate 101, namely, the bonding pads 121 are distributed in a fold line in the long-side direction of the package substrate 101, and each bonding pad 121 is used for bearing a solder ball; and each of the pads 121 has a shape of a cut circle; the dicing circle includes at least one longitudinal section 1211, and the longitudinal section 1211 is disposed adjacent to and parallel to the long side of the package substrate 101.

The projection distance of the center distance of two adjacent bonding pads 121 on the narrow side of the package substrate 101 is greater than or equal to the minimum package distance d _min. The minimum package spacing d _min is the minimum distance that ensures that after solder balls are soldered to two pads 121 that are adjacently disposed in the longitudinal direction of the package substrate 101, signal hops can be avoided. The value of the minimum package pitch d _min is related to the width of the package substrate 101 and the layout of the circuit layout under the package substrate 101, which is set according to the actual situation.

Further, as shown in fig. 3, in the present embodiment, 6 pads 121 are provided on the package substrate 101, and are labeled pl1, pl2, pl3, pr1, pr2, pr3, respectively. The shape of each of the circular cutting pads 121 is the same, and here, the pad pl3 is taken as an example, the dotted line portion thereof is the first cutting portion 1212 to be cut, and the solid line portion is the remaining circular cutting pad pl3. Wherein, the radius of the pad pl3 is r _u, and the packaging coefficient is n ₁, and the distance d _v＝n₁×r_u,n₁ epsilon (0, 1) from the center of the pad pl3 to the longitudinal section 1211 thereof. By cutting the pads from a complete circle to an incomplete circle (i.e., cutting a circle), the width of the pads 121 in the direction of the narrow side of the package substrate 101 is reduced, and thus the narrow side of the package substrate 101 can be further reduced, so that miniaturization of the package structure is achieved. At this time, the width wt of the package substrate 101 only needs to satisfy wt > 2×d _v+d_min, where d _v is the distance from the center of the pad 121 to the longitudinal section 1211, and d _min is the minimum package pitch. Of course, the number of pads 121 is not limited to 6, and a wafer level package structure of two columns is applicable.

Further, as shown in fig. 2 and 3, the direction of the center distance d2 of the circular pads 202 adjacently disposed on the conventional package substrate 201 is a vertical or horizontal direction. In the first embodiment, the two adjacent pads 121 are arranged in a staggered manner along the narrow-side symmetry axis A-A of the package substrate 101, and the included angle between the centers of the circles of the two adjacent pads 121 is θ (i.e., the included angle between the connecting line of the centers of circles and the horizontal line is θ), at this time, the spacing d3=d _min/cos θ between the centers of circles of the two adjacent pads 121 is θ e (0,90 °). Since d _min is the minimum packaging space and 0 < cos θ < 1, the space d3 between the centers of circles of two bonding pads 121 arranged in a staggered manner is larger than the minimum packaging space d _min, that is to say, the space d3 between the centers of circles of two bonding pads 121 arranged in an adjacent staggered manner must meet the requirement of the minimum packaging space.

Preferably, the projections of the two adjacent bonding pads 121 disposed in a staggered manner on the long side of the package substrate 101 are not overlapped with each other, so that a vacancy is formed on the other side of the narrow-side symmetry axis A-A corresponding to each bonding pad 121, so that a larger number of sensors or other electronic components can be mounted, and a more abundant wiring space is provided. When the included angle between the centers of the adjacent two pads 121 is 90 °, two rows of pads equivalent to two rows of pads disposed on both sides of the symmetry axis A-A of the narrow side of the package substrate 101 become one row of pads, and the width of the package structure 100 of the chip is the smallest at this time, but the package structure 100 disposed in one row is limited by the limitation of the integrated circuit layout, the package substrate 101 cannot be made very thin and narrow, and at the same time, the corresponding length of the package substrate 101 in the same area is longer, so that the stress of the package structure 100 becomes larger, and the package substrate 101 is likely to be broken, so that the application range of the included angle θ between the centers of the adjacent two pads 121 is 0-90 °.

In another width-compact semiconductor package structure provided in the first embodiment, as shown in fig. 4, the bonding pad adjacent to the narrow side of the package substrate 101 is a fan-shaped bonding pad 122, the fan-shaped bonding pad 122 further includes a transverse tangential plane 1222, the transverse tangential plane 1222 is parallel to the narrow side of the package substrate 101, and the longitudinal tangential plane 1221 of the fan-shaped bonding pad 122 is also parallel to the long side of the package substrate 101. Specifically, as shown in fig. 4, in the first embodiment, 2 fan-shaped pads 122 are included, and two fan-shaped pads 122 are respectively disposed on opposite corners of the package substrate 101, and are respectively denoted by ps1 and ps2. Each fan-shaped pad 122 has the same shape, and here, the fan-shaped pad ps2 is taken as an example, the broken line portion is the second cut portion 1223 that is cut, and the solid line portion is the remaining fan-shaped pad ps2. Specifically, a distance d _v＝n₁×r_su from the center of the fan-shaped pad ps2 to the longitudinal section 1221 thereof, where n ₁ is a packaging coefficient, r _su is a radius of the fan-shaped pad ps2, and n ₁ e (0, 1). Further, the distance d _h＝n₂×r_su from the center of the fan-shaped pad ps2 to the transverse section 1222 thereof, where n ₂ is a cutting coefficient, r _su is the radius of the fan-shaped pad ps2, and n ₂ e (0, 1). It should be noted that, in practical application, the packaging coefficient n ₁ and the cutting coefficient n ₂ may be equal or unequal, and they are set according to the actual reserved space of the product, so that the packaging structure formed by the packaging substrate with the fan-shaped bonding pad can be installed in the reserved space of the product. By setting the pads adjacent to the narrow sides of the package substrate 101 as the fan-shaped pads 122, not only the width of the package substrate 101 in the narrow side direction is reduced, but also the length of the package substrate 101 in the long side direction is shortened, so that the size of the package structure provided in the first embodiment can be further reduced, and the application scene of the package structure is enlarged on the premise of ensuring the balance of welding stress.

Further, the semiconductor package 100 further includes at least one sensor 103, as shown in fig. 4, two sensors 103 (including a first sensor H1 and a second sensor H2) are disposed in this embodiment, where the first sensor H1 and the second sensor H2 are respectively disposed at a vacancy on the other side of the narrow-side symmetry axis A-A corresponding to the pad pr2 and the pad pl 2. In the case where the sensor 103 is disposed on the package substrate 101, a distance from the sensor 103 to the pad 121 needs to be considered, especially, a distance between the sensor 103 and the pad 121 closest thereto needs to be considered, when the solder ball is disposed on the pad 121, a signal jump is caused by data transmission on the solder ball, and the sensor 103 is a source generating a weak signal, so that in order to reduce interference of the solder ball on the pad 121 on the sensor 103, the sensor 103 needs to be kept at a certain distance from the pad 121. In this embodiment, the first sensor H1 and the second sensor H2 are disposed at the gaps in the horizontal direction corresponding to the pads pr2 and pl2, so that the distances between the sensors 103 and the pads pr2 and pl2, respectively, can be satisfied without increasing the length of the package substrate 101 in the longitudinal direction. At this time, the package structure 100 after the sensor 103 is mounted can still ensure that the width wt of the package substrate 101 meets the minimum width limit specified by wt > 2×d _v+d_min, and the narrow-side design of the package structure 100 is realized.

In summary, in the compact semiconductor package structure with a width provided in the first embodiment, the plurality of pads 121 are sequentially arranged on the package substrate 101 in a crossing manner, so that the stress of the package substrate 101 is balanced, and the phenomenon of unbalanced stress distribution of the package substrate 101 is reduced; further, by setting the shape of the pad 121 to be a cut circle, the width of the pad 121 is reduced, and thus the width of the package substrate 101 is reduced, realizing the narrow-side design of the semiconductor package structure; meanwhile, two adjacent bonding pads 121 are arranged in a staggered manner along the narrow-side symmetry axis A-A of the package substrate 101, so that the gaps on the package substrate 101 are increased, the sensor 103 or other components can be flexibly mounted in the corresponding gaps, the narrow-side width and the long-side length of the package substrate 101 are not increased, and the miniaturization of the semiconductor package structure is realized.

Example two

Fig. 5 is a schematic diagram of a width-compact semiconductor package 100 according to a second embodiment of the present utility model, where the width-compact semiconductor package 100 includes: a package substrate 101 having a rectangular shape including long sides and narrow sides, so that the package substrate 101 can be accommodated in a narrow and long space at the edge of the camera module 2; a plurality of pad groups 102 arranged on the surface of the package substrate 101 along the long side array of the package substrate 101; each bonding pad group 102 comprises two bonding pads 121, the two bonding pads 121 are symmetrically arranged along a narrow-side symmetry axis A-A of the package substrate 101, and each bonding pad 121 is used for bearing a solder ball; and each of the pads 121 has a shape of a cut circle; the dicing circle includes at least one longitudinal section 1211, and the longitudinal section 1211 is disposed adjacent to and parallel to the long side of the package substrate 101. Preferably, the number of the bonding pad groups 102 is 3 groups or 4 groups.

The center-to-center distance between the two pads 121 symmetrically arranged in each pad group 102 is equal to or greater than the minimum package distance d _min. The minimum package spacing d _min is the minimum distance that can prevent signal jump after the solder balls are soldered to the two pads 121 symmetrically arranged. The minimum package pitch d _min is related to the width of the package substrate 101 and the layout of the circuit layout under the package substrate 101, and needs to be set according to the actual situation.

Further, as shown in fig. 5, in the present embodiment, 4 pad groups 102, that is, 8 pads 121 in total, are provided on the package substrate 101, and are denoted by pl1, pl2, pl3, pl4, pr1, pr2, pr3, pr4, respectively. Taking the pad pl4 as an example, the dotted line portion is a first cut portion 1212 to be cut, and the solid line portion is a remaining cut circular pad pl4. Wherein, the radius of the pad pl4 is r _u, and the packaging coefficient is n ₁, and the distance d _v＝n₁×r_u,n₁ epsilon (0, 1) from the center of the pad pl4 to the longitudinal section 1211 thereof. By cutting the pads from a complete circle to an incomplete circle (i.e., cutting a circle), the width of the pads 121 in the direction of the narrow side of the package substrate 101 is reduced, and thus the narrow side of the package substrate 101 can be further reduced, so that miniaturization of the package structure is achieved. At this time, the width wt of the package substrate 101 only needs to satisfy wt > 2×d _v+d_min, where d _v is the distance from the center of the pad 121 to the longitudinal section 1211, and d _min is the minimum package pitch.

In another compact semiconductor package structure provided in the second embodiment, as shown in fig. 6, the bonding pad adjacent to the narrow side of the package substrate 101 is a fan-shaped bonding pad 122, the fan-shaped bonding pad 122 further includes a transverse tangential plane 1222, the transverse tangential plane 1222 is parallel to the narrow side of the package substrate 101, and the longitudinal tangential plane 1221 of the fan-shaped bonding pad 122 is also parallel to the long side of the package substrate 101. Specifically, as shown in fig. 6, in the second embodiment, 4 fan-shaped pads 122 are included, and ps1, ps2, ps3, and ps4 are respectively labeled. Taking the fan-shaped pad ps1 as an example, the broken line portion is the second dicing portion 1223 that is diced, and the solid line portion is the remaining fan-shaped pad ps1. Specifically, a distance d _v＝n₁×r_su from the center of the fan-shaped pad ps1 to the longitudinal section 1221 thereof, where n ₁ is a packaging coefficient, r _su is a radius of the fan-shaped pad ps1, and n ₁ e (0, 1). Further, the distance d _h＝n₂×r_su from the center of the fan-shaped pad ps1 to the transverse section 1222 thereof, where n ₂ is a cutting coefficient, r _su is the radius of the fan-shaped pad ps1, and n ₂ e (0, 1). It should be noted that, in practical application, the packaging coefficient n ₁ and the cutting coefficient n ₂ may be equal or unequal, and they are set according to the actual reserved space of the product, so that the packaging structure formed by the packaging substrate with the fan-shaped bonding pad can be installed in the reserved space of the product. By setting the pads adjacent to the narrow sides of the package substrate 101 as the fan-shaped pads 122, not only the width of the package substrate 101 in the narrow side direction is reduced, but also the length of the package substrate 101 in the long side direction is shortened, so that the size of the package structure provided in the second embodiment can be further reduced, and the application scene of the package structure is enlarged on the premise of ensuring the balance of welding stress.

Further, as shown in fig. 5, the semiconductor package 100 further includes at least one sensor 103. When the sensor 103 is disposed on the package substrate 101, a distance from the sensor 103 to the pad 121 needs to be considered, especially a distance between the sensor 103 and the pad 121 closest to the sensor 103 needs to be considered, after the solder balls are disposed on the pad 121, data transmission on the solder balls causes signal jump, and the sensor 103 is a source generating weak signals, so in order to reduce interference of the solder balls on the pad 121 on the sensor 103, the sensor 103 needs to be kept at a certain distance from the pad 121. For the above reasons, the present utility model disposes the sensor 103 at the middle position of any two adjacent pad groups 102, i.e., along the vertical arrangement of the pads 121, without being disposed between two pads 121 disposed horizontally symmetrically; the arrangement is that the vertical distance between the sensor 103 and the bonding pad group 102 can be increased due to less size limitation in the long side direction of the package substrate 101, so that the influence of the solder balls on the bonding pads 121 on the sensor 103 in data transmission is avoided, and meanwhile, the increase of the narrow side width of the package substrate 101 is avoided, so that the width of the package substrate 100 is not limited by the distance between the solder balls and the sensor 103, the width wt of the package substrate 101 can still be ensured to meet the minimum width limitation specified by wt & gt2×d _v+d_min, and the narrow side design of the package structure 100 is realized. In the second embodiment, 4 bonding pad groups 102 are disposed on the package substrate 101, and the sensor 103 is used for position detection and is disposed in the center of the package substrate 101, that is, in the middle position of two bonding pad groups 102 disposed on two adjacent sides of the long-side symmetry axis of the package substrate 101, so as to ensure stress balance of the package structure. Of course, the sensor 103 may also be an array of several sensors.

In summary, in the compact semiconductor package structure with a width provided in the second embodiment, the pads 121 on the package substrate 101 are symmetrically arranged along the symmetry axis of the narrow side, so that the welding stress on the package substrate 101 is balanced, the influence of the welding stress on the package substrate 101 is reduced, and the stability of the package structure 100 is improved.

Further, by setting the shape of the pad 121 to a cut circular shape, the width of the pad 121 and thus the width of the package substrate 101 is reduced, and miniaturization of the semiconductor package structure 100 is achieved.

Further, by disposing the sensor 103 in the middle of two adjacent pad groups 102, signal interference of solder balls on the pads 121 to the sensor 103 is avoided, and the narrow side width of the package substrate 101 is not increased, so that the narrow side design of the package structure 100 is realized.

Example III

Fig. 7 is a schematic diagram of a width-compact semiconductor package 100 according to a third embodiment of the present utility model, where the width-compact semiconductor package 100 includes: the shape of the packaging substrate 101 is a rectangle comprising long sides and narrow sides, so that the shape of the packaging substrate 101 is matched with a narrow and long space reserved at the edge of the camera module 2; at least two first pad groups 104, each of the first pad groups 104 including two first pads 141 symmetrically disposed along a narrow-side symmetry axis A-A of the package substrate 101; at least one second bonding pad group 105, wherein the second bonding pad group 105 comprises at least two second bonding pads 151 arranged in a staggered manner along a narrow-side symmetry axis A-A of the package substrate 101; each first pad group 104 is arranged on the surface of the package substrate 101 along the long-side array of the package substrate 101; each of the second pad groups 105 is correspondingly disposed between every two adjacent first pad groups 104; each of the pads (including the first pad 141 and the second pad 151) is for carrying solder balls, and each of the pads is in a shape of a cut circle; the dicing circle at least includes a longitudinal section (including a first longitudinal section 1411 corresponding to the first bonding pad 141 and a second longitudinal section 1511 corresponding to the second bonding pad 151), and each longitudinal section is disposed adjacent to and parallel to the long side of the package substrate 101.

The center distance between the two first pads 141 symmetrically arranged in each of the first pad groups 104 is greater than or equal to the minimum package distance d _min. The minimum package spacing d _min is the minimum distance that can prevent signal jump after the solder balls are soldered to the two symmetrically arranged first pads 141. The minimum package pitch d _min is related to the width of the package substrate 101 and the layout of the circuit layout under the package substrate 101, and needs to be set according to the actual situation.

Further, as shown in fig. 2 and 7, the direction of the center-to-center distance d2 of the circular pads 202 adjacently disposed on the conventional package substrate 201 is a vertical or horizontal direction. In the third embodiment, two adjacent second pads 151 in the second pad group 105 are arranged in a staggered manner along the narrow-side symmetry axis A-A, and the included angle between the centers of circles of the two adjacent second pads 151 is θ (i.e., the included angle between the connecting line of the two centers of circles and the horizontal line is θ), at this time, the spacing d4=d _min/cos θ between the centers of circles of the two adjacent second pads 151 is θ e (0,90 °). Since d _min is the minimum packaging interval and 0 < cos θ < 1, the interval d4 between the circle centers of the two second bonding pads 151 arranged in a staggered manner is larger than the minimum packaging interval d _min, that is to say, the interval d4 between the circle centers of the two second bonding pads 151 arranged in a staggered manner must meet the requirement of the minimum packaging interval. Preferably, the projections of the two adjacent second bonding pads 151 of the second bonding pad group 105, which are arranged in a staggered manner, on the long side of the package substrate 101 do not overlap with each other, so that a space is formed vertically above or vertically below the two second bonding pads 151 of the second bonding pad group 105, so that a larger number of sensors or other electronic components can be mounted, and a more abundant wiring space is provided.

In the third embodiment, as shown in fig. 7, two first bonding pad groups 104 are disposed on the package substrate 101 and are respectively located at two narrow-side edges, and each first bonding pad group 104 includes two first bonding pads 141 symmetrically disposed along a narrow-side symmetry axis A-A of the package substrate 101; the second bonding pad group 105 is disposed between the two first bonding pad groups 104, and the second bonding pad group 105 includes two second bonding pads 151 disposed offset along the narrow-side symmetry axis A-A of the package substrate 101. In other embodiments, the number of the first bonding pad groups 104 disposed on the package substrate 101 is greater than 2, at this time, the second bonding pad groups 105 are disposed between every two adjacent first bonding pad groups at intervals, so as to form a layout in which the first bonding pad groups 104 and the second bonding pad groups 105 are sequentially disposed at intervals along the long side of the package substrate 101, and the layout provides more gaps between bonding pads, so that more number of sensors or other components can be mounted without increasing the length of the package substrate 101, and the space utilization of the package substrate 101 is greatly improved.

Further, as shown in fig. 7, in the third embodiment, the first bonding pad 141 and the second bonding pad 151 have the same cutting shape, and the first bonding pad pl7 is taken as an example, the dotted line portion thereof is a first cutting portion 1412 to be cut, and the solid line portion is a remaining circular cutting first bonding pad pl7. The radius of the first pad pl7 is r _u, and the packaging coefficient is n ₁, so that the distance d _v＝n₁×r_u,n₁ e (0, 1) from the center of the first pad pl7 to the longitudinal section 1411 thereof. By cutting the bonding pad from a complete circle to an incomplete circle (i.e., cutting a circle), the width of the bonding pad in the direction of the narrow side of the package substrate 101 is reduced, and thus the narrow side of the package substrate 101 can be further reduced, so that miniaturization of the package structure is achieved. At this time, the width wt of the package substrate 101 only needs to satisfy wt > 2×d _v+d_min, where d _v is the distance from the center of the pad 121 to the longitudinal section 1411, and d _min is the minimum package pitch.

In another compact semiconductor package structure provided in the third embodiment, as shown in fig. 8, the pads adjacent to the narrow side of the package substrate 101 are two fan-shaped pads 122 symmetrically disposed along the symmetry axis A-A of the narrow side of the package substrate 101, the fan-shaped pads 122 further include a transverse tangential plane 1222, the transverse tangential plane 1222 is parallel to the narrow side of the package substrate 101, and the longitudinal tangential plane 1221 of the fan-shaped pads 122 is also parallel to the long side of the package substrate 101. Specifically, as shown in fig. 8, the present embodiment includes 4 fan-shaped pads 122, which are respectively denoted by ps1, ps2, ps3, and ps4. Taking the fan-shaped pad ps3 as an example, the broken line portion is the second dicing portion 1223 that is diced, and the solid line portion is the remaining fan-shaped pad ps3. Specifically, a distance d _v＝n₁×r_su from the center of the fan-shaped pad ps3 to the longitudinal section 1221 thereof, where n ₁ is a packaging coefficient, r _su is a radius of the fan-shaped pad ps3, and n ₁ e (0, 1). Further, the distance d _h＝n₂×r_su from the center of the fan-shaped pad ps3 to the transverse section 1222 thereof, where n ₂ is a cutting coefficient, r _su is the radius of the fan-shaped pad ps3, and n ₂ e (0, 1). It should be noted that, in practical application, the packaging coefficient n ₁ and the cutting coefficient n ₂ may be equal or unequal, and they are set according to the actual reserved space of the product, so that the packaging structure formed by the packaging substrate with the fan-shaped bonding pad can be installed in the reserved space of the product. By setting the first bonding pad adjacent to the narrow side of the package substrate 101 as the fan-shaped bonding pad 122, not only the width in the narrow side direction of the package substrate 101 is reduced, but also the length in the long side direction of the package substrate 101 is shortened, so that the size of the package structure provided in the third embodiment can be further reduced, and the application scene of the package structure is enlarged on the premise of ensuring the balance of welding stress.

Further, the semiconductor package 100 further includes at least one sensor 103, as shown in fig. 7, two sensors 103 (including a first sensor H1 and a second sensor H2) are disposed in this embodiment, where the first sensor H1 and the second sensor H2 are disposed at the empty positions of the second bonding pad group 103 where the second bonding pads 151 are not disposed, respectively. In the case where the sensor 103 is disposed on the package substrate 101, a distance between the sensor 103 and the second pad 151, particularly, a distance between the sensor 103 and the second pad 151 closest thereto needs to be considered, and when the solder balls are disposed on the second pad 151, data transmission on the solder balls causes signal hopping, and the sensor 103 is a source generating weak signals, so that in order to reduce interference of the solder balls on the second pad 151 on the sensor 103, the sensor 103 needs to be kept at a certain distance from the second pad 151. In this embodiment, the first sensor H1 and the second sensor H2 are disposed at the gaps in the longitudinal direction corresponding to the two second pads 151, so that the distances between the sensors 103 and the second pads 151 can be satisfied without increasing the length of the package substrate 101 in the longitudinal direction. At this time, the package structure 100 after the sensor 103 is mounted can still ensure that the width wt of the package substrate 101 meets the minimum width limit specified by wt > 2×d _v+d_min, and the narrow-side design of the package structure 100 is realized. The offset arrangement of the second pads 151 allows the package substrate 101 to have a large space in the longitudinal direction, so that the mounting positions of the first sensor H1 and the second sensor H2 can be moved within the space in the longitudinal direction, and is not limited to that shown in fig. 7. Of course, the sensor 104 may also be an array of several sensors.

In summary, in the compact semiconductor package structure with a width provided in the third embodiment, the first pads 141 symmetrically arranged along the symmetry axis of the narrow side of the package substrate 101 are provided, so that the welding stress on the package substrate 101 is balanced, the influence of the welding stress on the package substrate 101 is reduced, and the stability of the package structure 100 is improved.

Further, by setting the shapes of the first land 141 and the second land 151 to be the same cut circle, the widths of the first land 141 and the second land 151 are reduced, and thus the width of the package substrate 101 is reduced, realizing the narrow-side design of the semiconductor package structure.

Further, by providing the second bonding pads 151 disposed in a staggered manner along the narrow-side symmetry axis of the package substrate 101, a space on the package substrate 101 is increased, so that the sensor 103 or other components can be flexibly mounted in the corresponding space, and the narrow-side width and the long-side length of the package substrate 101 are not increased, thereby realizing miniaturization of the semiconductor package structure.

While the present utility model has been described in detail through the foregoing description of the preferred embodiment, it should be understood that the foregoing description is not to be considered as limiting the utility model. Many modifications and substitutions of the present utility model will become apparent to those of ordinary skill in the art upon reading the foregoing. Accordingly, the scope of the utility model should be limited only by the attached claims.

Claims

1. A width-compact semiconductor package, comprising:

a package substrate in the shape of a rectangle including long sides and narrow sides;

the bonding pads are sequentially arranged on two sides of the narrow-side symmetry axis of the packaging substrate in a crossing mode, and two adjacent bonding pads are arranged in a staggered mode along the narrow-side symmetry axis of the packaging substrate;

Each bonding pad is in a cutting circular shape;

The cutting circle at least comprises a longitudinal section, and the longitudinal section is adjacent and parallel to the long side of the packaging substrate.

2. The semiconductor package according to claim 1, wherein a projected distance of a center-to-center distance between two adjacent pads on a narrow side of the package substrate is equal to or greater than a minimum package distance d _min.

3. The compact-width semiconductor package according to claim 1, wherein the angle between the adjacent two bonding pads is θ, θ∈ (0,90 °); or projections of the adjacent two bonding pads on the long side of the packaging substrate are not overlapped with each other.

4. The compact-width semiconductor package according to claim 1, wherein a distance d _v＝n₁×r_u from a center of the pad to a longitudinal section thereof, where n ₁ is a package coefficient, r _u is a radius of the pad, and n ₁ e (0, 1).

5. The compact-width semiconductor package according to claim 1, wherein the pads adjacent to the narrow side of the package substrate are fan-shaped pads, the fan-shaped pads further comprising a transverse cut parallel to the narrow side of the package substrate.

6. The compact-width semiconductor package according to claim 5, wherein a distance d _v＝n₁×r_su from a center of the fan-shaped pad to a longitudinal section thereof, where n ₁ is a package coefficient, r _su is a radius of the fan-shaped pad, n ₁ e (0, 1); the distance d _h＝n₂×r_su from the center of the fan-shaped bonding pad to the transverse section of the fan-shaped bonding pad is equal to n ₂, r _su is equal to the radius of the fan-shaped bonding pad, and n ₂ epsilon (0, 1).

7. The width-compact semiconductor package of claim 1, further comprising at least one sensor; the sensor is arranged at the vacancy of the other side of the narrow-side symmetry axis corresponding to any bonding pad.

8. A width-compact semiconductor package, comprising:

A plurality of pad groups arranged on the surface of the package substrate along the long-side array of the package substrate;

Each bonding pad group comprises two bonding pads, and the two bonding pads are symmetrically arranged along the symmetry axis of the narrow side of the packaging substrate; and each bonding pad is in a cutting round shape;

9. The semiconductor package according to claim 8, wherein a center-to-center distance of two of the pads symmetrically arranged in the pad group is equal to or larger than a minimum package distance d _min.

10. The compact-width semiconductor package according to claim 8, wherein a distance d _v＝n₁×r_u from a center of the pad to a longitudinal section thereof, where n ₁ is a package coefficient, r _u is a radius of the pad, and n ₁ e (0, 1).

11. The compact-width semiconductor package according to claim 8, wherein the pads adjacent to the narrow side of the package substrate are fan-shaped pads, the fan-shaped pads further comprising a transverse cut parallel to the narrow side of the package substrate.

12. The compact-width semiconductor package according to claim 11, wherein a distance d _v＝n₁×r_su from a center of the fan-shaped pad to a longitudinal section thereof, where n ₁ is a package coefficient, r _su is a radius of the fan-shaped pad, n ₁ e (0, 1); the distance d _h＝n₂×r_su from the center of the fan-shaped bonding pad to the transverse section of the fan-shaped bonding pad is equal to n ₂, r _su is equal to the radius of the fan-shaped bonding pad, and n ₂ epsilon (0, 1).

13. The width-compact semiconductor package of claim 8, further comprising at least one sensor; the sensor is arranged at the middle position of any two adjacent bonding pad groups.

14. A width-compact semiconductor package, comprising:

At least two first bonding pad groups, wherein each first bonding pad group comprises two first bonding pads symmetrically arranged along the symmetry axis of the narrow side of the packaging substrate;

the second bonding pad group comprises at least two second bonding pads which are arranged in a staggered manner along the symmetry axis of the narrow side of the packaging substrate;

Each first bonding pad group is arranged on the surface of the packaging substrate along the long-side array of the packaging substrate; each second bonding pad group is correspondingly arranged between every two adjacent first bonding pad groups;

Each bonding pad is in a cutting circular shape; the cutting circle at least comprises a longitudinal section, and the longitudinal section is adjacent and parallel to the long side of the packaging substrate.

15. The semiconductor package according to claim 14, wherein a center-to-center distance of two first pads of the first pad group, which are symmetrically disposed, is equal to or greater than a minimum package distance d _min.

16. The compact-width semiconductor package according to claim 14, wherein an included angle between two adjacent second pads arranged in a staggered manner in the second pad group is θ, θ∈ (0,90 °); or projections of two adjacent second bonding pads arranged in a staggered manner in the second bonding pad group on the long edge are not overlapped with each other.

17. The compact-width semiconductor package according to claim 14, wherein a distance d _v＝n₁×r_u from a center of each of the pads to a longitudinal section thereof, where n ₁ is a package coefficient, r _u is a radius of the pad, and n ₁ e (0, 1).

18. The compact-width semiconductor package according to claim 14, wherein adjacent to the narrow side of the package substrate is a first pad, the first pad being a fan-shaped pad, the fan-shaped pad further comprising a transverse cut parallel to the narrow side of the package substrate.

19. The compact-width semiconductor package according to claim 18, wherein a distance d _v＝n₁×r_su from a center of the fan-shaped pad to a longitudinal section thereof, where n ₁ is a package coefficient, r _su is a radius of the fan-shaped pad, n ₁ e (0, 1); the distance d _h＝n₂×r_su from the center of the fan-shaped bonding pad to the transverse section of the fan-shaped bonding pad is equal to n ₂, r _su is equal to the radius of the fan-shaped bonding pad, and n ₂ epsilon (0, 1).

20. The width-compact semiconductor package of claim 14, further comprising at least one sensor; the sensor is arranged at a vacancy of the second bonding pad group where the second bonding pad is not arranged.