CN221281524U - FPGA (field programmable Gate array) calculation co-processing module based on VITA74 standard - Google Patents

Abstract

An FPGA computation co-processing module based on the VITA74 standard, comprising: the system comprises an FPGA chip, and a memory module, GPHY modules, a power module, a clock module, a health management module and a VNX connector which are arranged on the FPGA chip; all the devices are domestic devices. The calculation co-processing module meets the miniaturization product of the VITA74 standard, can be used as a general standard shelf product, and can greatly reduce the research and development process; meanwhile, compared with VITA46 or ASAAC architecture products, the module size is reduced in length, width and height, the form of 'carrier plate + daughter card' is supported, smaller-sized modules meeting the standard can be provided for customers, the competitiveness of similar products is improved, and the product diversity under different size requirements is promoted.

Description

FPGA (field programmable Gate array) calculation co-processing module based on VITA74 standard

Technical Field

The utility model relates to the field of FPGA (field programmable gate array) calculation co-processing, in particular to an FPGA calculation co-processing module based on VITA74 standards.

Background

In the development of an embedded system, most of traditional signal processing systems serving as FPGA co-processing functional units are integrated in other modules, so that the size of the modules is larger, the size of a case is increased, and in the requirements of the current miniaturized equipment, the requirements on the size, the power consumption and the like are severe; under the domestic trend, the research and development production time is greatly increased from the principle design, PCB wiring, plate making and subsequent production processes, and the efficiency is lower.

Therefore, it is necessary to design an FPGA computation co-processing module based on the VITA74 standard to overcome the above-mentioned problems.

Disclosure of utility model

In order to avoid the problems, an FPGA calculation co-processing module based on the VITA74 standard is provided, and a miniaturized product meeting the VITA74 standard can be used as a general standard shelf product, so that the research and development process can be greatly reduced; meanwhile, compared with VITA46 or ASAAC architecture products, the module size is reduced in length, width and height, the form of 'carrier plate + daughter card' is supported, smaller-sized modules meeting the standard can be provided for customers, the competitiveness of similar products is improved, and the product diversity under different size requirements is promoted.

The utility model provides an FPGA (field programmable gate array) calculation co-processing module based on VITA74 standard, which comprises the following components: the system comprises an FPGA chip, and a memory module, GPHY modules, a power module, a clock module, a health management module and a VNX connector which are arranged on the FPGA chip; all the devices are domestic devices.

Further, the FPGA chip is K7 series JFM K325T and comprises a high-speed interface, a general IO and the like.

Further, the memory module comprises a plurality of DDR3 memory chips SCB13H4G160AF-11MI and 32MB SPI FLASH chips SM25QH256MX, the plurality of DDR3 memory chips SCB13H4G160AF-11MI are combined to form a 64-bit wide program storage, and the 32MB SPI FLASH chips SM25QH256MX are used for program storage of the FPGA under the MIG controller of the FPGA chip. The DDR3 memory chip SCB13H4G160AF-11MI is 4 pieces, and can form a 2GB 64bit memory, and each chip is 16 bits; the 32MB SPI FLASH chip SM25QH256MX is 1 piece.

Furthermore, GPHY modules are JEM88E1111 kilomega PHY chips, and the FPGA chips are interconnected with the chips through RGMII interfaces to lead out kilomega electric ports.

Further, the power supply module includes an AST4630 power supply chip, an AST4644I power supply chip, and an LDO XYP7172 chip. The AST4630 power supply chip outputs 1.0V power supply to provide power for the FPGA kernel, and outputs 3.3V power supply to provide power for the FPGA IO BANK and peripheral chips such as a level conversion chip 4T245, an SM25QH256MX SPI FLASH chip and the like; the AST 4634I power chip outputs 1.5V power for supplying power to the FPGA HP BANK and the SCB13H4G160AF-11MI memory chip, outputs 1.8V power for supplying power to the FPGA HR BANK, outputs MGT1.0V for supplying power to the FPGA high-speed GTX interface MGTAVCC, and outputs MGT1.2V for supplying power to the FPGA high-speed GTX interface MGTAVTT; LDO XYP7172 chip output MGT1.8V provides power for the FPGA high-speed GTX interface MGTAVAUX power supply.

Further, the clock module comprises a clock BUFFER chip INS6110 to form a clock supply circuit, and multiple paths of 25MHz single-ended clocks are respectively supplied to different FPGA BANK and used as FPGA reference clocks.

Further, the health management module (BMC) comprises a Cortex-M4 BMC GD32F303VGT6 chip and is used for acquiring health information of the board card, including temperature, voltage and current, and supporting reporting of the health information.

Further, VNX connectors include 400pin connector GVNX-TW-MMMMM-1ASF, and VNX connector includes X4 PCIe interface, gigabit electrical interface, UART interface, GPIO interface, BMC reporting information IIC interface.

Further, the method further comprises the following steps:

SPI FALSH SM25QH256MX serial interface chip, which is interconnected with the FPGA through SPI x4 mode and is used as an FPGA starting program memory chip;

The temperature sensor GX18B20U chip is used for reading the ambient temperature of the FPGA chip;

The amplifier LT199G1XC6 chip is used for collecting power supply current in the board.

Further, the FPGA chip is used as an EP end to extend X4 PCIe to communicate with an RC end of a main control chip in the system, or to extend a 10GBase-R interface to be used for high-speed data communication.

The FPGA calculation co-processing module based on the VITA74 standard integrates domestic FPGA, DDR3, FLASH, network PHY, serial port, power supply, clock and VNX connectors on a printed board, and is carried out according to the thickness of 19mm of the VITA74 standard specification, and the connector signal definition is carried out according to the standard. The calculation co-processing module provides 12V and 3.3V Standby power to the inside, provides 1 path of X4 PCIe communication to the outside as an EP end to communicate with a main node RC on the system, and simultaneously externally leads out 1 path of network, 1 path of serial port and multiple paths of GPIOs to carry out auxiliary communication interaction. The calculation co-processing module can be used as a standard goods shelf product, and is convenient for adapting to a client system.

Compared with the prior art, the utility model has the following beneficial effects: the FPGA computing unit comprises DDR, FLASH, network, serial port and the like, so that an FPGA minimum system is built, the used device is a domestic device, the size and the signal definition of the FPGA minimum system accord with the VITA74 standard, the FPGA minimum system can be used as a general standard goods shelf product, and the goods shelf product accord with the standard architecture and can be general, so that the research and development process can be greatly reduced; meanwhile, compared with a miniaturized product meeting the VITA74 standard, the module size of the VITA46 or ASAAC architecture product is reduced in length, width and height, a carrier plate and daughter card form is supported, a module with smaller size and meeting the standard can be provided for customers, the competitiveness of similar products is improved, and the product diversity under different size requirements is promoted.

Drawings

Fig. 1 is a schematic structural diagram of an FPGA computation co-processing module based on the VITA74 standard according to a preferred embodiment of the present utility model.

Detailed Description

The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings. In the description of the present utility model, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present utility model and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present utility model. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present utility model, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present utility model will be understood in specific cases by those of ordinary skill in the art.

As shown in fig. 1, the FPGA computation co-processing module based on the VITA74 standard provided in this embodiment includes the following:

1 400pin connector conforming to the VITA74 standard;

4 DDR3 memory chips SCB13H4G160AF-11MI form 2GB capacity storage;

1 piece of 32MB SPI FLASH chip SM25QH256MX is used as a program storage of the FPGA;

1 chip GPHY chip JEM88E1111 and transformer are used for expanding 1 kilomega electric port as auxiliary data interaction channel;

3 pieces of RS4T245, wherein 1 piece is used for leading out 1 path of LVTTL level UART signal as a low-speed data interface, and the other 2 pieces are used for leading out FPGA JTAG signal, so that JTAG signal damage caused by hot plug is prevented;

1 Cortex-M4 BMC GD32F303VGT6 is used for monitoring the health information of the whole board, and simultaneously, 1 IIC is led out outwards to support a system main control node to acquire the health information of the whole board for real-time monitoring;

The 2-chip power supply chips AST4630 and AST4644 are used for outputting power sources of 1.0V, 1.5V, 1.8V, 3.3V and the like to supply power to the main chip and other auxiliary circuits;

the 1-chip clock BUFFER IN6110 is used for leading out clocks required by the FPGA;

the 1-chip LDO XYP7172 is used for leading out an FPGA high-speed interface auxiliary power supply;

The 1-piece temperature sensor GX18B20U is used for acquiring the environmental temperature of the FPGA chip;

The 3-chip amplifier LT199G1XC6 is connected to the BMC for current collection;

The FPGA chip can be used as an EP end to communicate with a system main control node through PCIe, and 1 path of supporting 10GBase-R interfaces are led out to the outside at the same time to support high-speed data communication.

The VNX connector conforming to the VITA74 standard comprises 12V, 3.3V Standby power input, 1X 4 PCIe interface, 110 GBase-R interface, 1 gigabit network electric interface, 1 FPGA leading-out serial port, 6 3.3V GPIO interface, 1 SWD debugging port led out by BMC, 1 UART and BOOT control signal.

The calculation co-processing module accords with the standard VITA74 standard, the size of 19mm is regulated in the standard, and the signal definition is executed according to standard recommendation. It includes JFM K325T chip, JEM88E1111GPHY chip, SCB13H4G160AF-11MIDDR3 memory chip, INS6110 clock BUFFER chip, GD32F303VGT6 BMC chip, AST4630 and AST4644 power chips, and GVNX-TW-MMM-1 ASF VNX connector. The FPGA externally leads out 1 path PCIe x4 interface, and 1 path network and serial port to VNX connectors. The utility model integrates domestic FPGA chips and peripheral DDR3, networks, serial ports and the like into a 19mm thickness module conforming to the VITA74 standard, the signal definition conforms to the standard recommendation, the external communication can be carried out through the PCIe interface, an FPGA calculation co-processing module conforming to the VITA74 standard and supporting PCIe communication is constructed, and the FPGA calculation co-processing module can be matched with a CPU and the like to carry out co-processing and support dynamic loading and the like.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present utility model, and not for limiting the same; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the utility model.

Claims (10)

1. An FPGA computation co-processing module based on VITA74 standard, comprising: the system comprises an FPGA chip, and a memory module, GPHY modules, a power module, a clock module, a health management module and a VNX connector which are arranged on the FPGA chip; all the devices are domestic devices.

2. The FPGA computing co-processing module based on the VITA74 standard as set forth in claim 1, wherein: the FPGA chip is K7 series JFM K325T and comprises a high-speed interface and a general IO.

3. The FPGA computing co-processing module based on the VITA74 standard as set forth in claim 1, wherein: the memory module comprises a plurality of DDR3 memory chips SCB13H4G160AF-11MI and 32MB SPI FLASH chips SM25QH256MX, the DDR3 memory chips SCB13H4G160AF-11MI are combined to form a 64-bit wide program storage which is mounted under an MIG controller of the FPGA chip, and the 32MB SPI FLASH chips SM25QH256MX are used for the program storage of the FPGA.

4. The FPGA computing co-processing module based on the VITA74 standard as set forth in claim 1, wherein: the GPHY module is a JEM88E1111 kilomega PHY chip, and the FPGA chip is interconnected with the chip through an RGMII interface to lead out kilomega electric port.

5. The FPGA computing co-processing module based on the VITA74 standard as set forth in claim 1, wherein: the power supply module comprises an AST4630 power supply chip, an AST4644I power supply chip and an LDO XYP7172 chip.

6. The FPGA computing co-processing module based on the VITA74 standard as set forth in claim 1, wherein: the clock module comprises a clock BUFFER chip INS6110 to form a clock supply circuit, and the clock supply circuit is used for respectively supplying multiple paths of 25MHz single-ended clocks to different FPGA BANK to be used as FPGA reference clocks.

7. The FPGA computing co-processing module based on the VITA74 standard as set forth in claim 1, wherein: the health management module comprises a Cortex-M4 BMC GD32F303VGT6 chip and is used for acquiring health information of the board card, including temperature, voltage and current, and supporting reporting of the health information.

8. The FPGA computing co-processing module based on the VITA74 standard as set forth in claim 1, wherein: the VNX connector comprises a 400pin connector GVNX-TW-MMM-1 ASF, and the VNX connector comprises an X4 PCIe interface, a gigabit electric interface, a UART interface, a GPIO interface and a BMC reporting information IIC interface.

9. The FPGA computing co-processing module based on the VITA74 standard as set forth in claim 1, wherein: further comprises:

SPI FALSH SM25QH256MX serial interface chip, which is interconnected with the FPGA through SPI x4 mode and is used as an FPGA starting program memory chip;

The temperature sensor GX18B20U chip is used for reading the ambient temperature of the FPGA chip;

The amplifier LT199G1XC6 chip is used for collecting power supply current in the board.

10. The FPGA computing co-processing module based on the VITA74 standard as set forth in claim 1, wherein: the FPGA chip is used as an EP end to extend X4 PCIe to communicate with an RC end of a main control chip in the system, or to extend a 10GBase-R interface to be used for high-speed data communication.