CN222014743U - Hot plug control circuit of on-board network card - Google Patents

Abstract

The utility model provides an onboard network card hot-swap control circuit, including an onboard network card, a network card power switch, a network card power supply, a reset control module, a clock generator, a main control module and a switch circuit, wherein the onboard network card is connected to a PCIE interface of the main control module via a PCIE bus, the power interface of the onboard network card is connected to the network card power supply via the network card power switch, the clock interface is connected to the clock generator, and the reset interface is connected to the reset control module. The switch circuit controls the main control module to close or open the physical interface function of the PCIE interface via a first output interface, controls the clock generator to output or close the output clock signal to the clock interface, and controls the reset control module to output a reset signal to the reset interface; and controls the network card power switch to connect or disconnect the connection between the network card power supply and the power interface via a second output interface. The utility model can completely shield or isolate the onboard network card in hardware and can freely and flexibly switch back to the onboard network card.

Description

Hot plug control circuit of on-board network card

Technical Field

The utility model relates to the technical field of computers, in particular to a hot plug control circuit of an on-board network card.

Background

The on-board network card is a network card chip integrated with a main board integrating network functions, and along with popularization of network communication technology, the network card gradually becomes one of basic accessories of computer equipment, and more main boards are provided with the on-board network card.

Hot plug (Hot Swap), i.e., hot plug, refers to inserting or extracting a module and a board card into or from a system without affecting the normal operation of the system under the condition of not shutting down the power supply of the system, so as to improve the expansibility and flexibility of the whole system and the timely recovery capability when coping with faults.

At present, a network card on a main board of a computer device such as a home computer or a server cannot realize real hot plug, generally only can be used for unloading on software and can not thoroughly unload on hardware, however, in some professional application fields or scenes, for example, in order to ensure application safety, it is hoped to at least thoroughly shield or isolate the network card on hardware and switch back the network card freely and flexibly, namely, realize hot plug management of an on-board network card on hardware.

Therefore, how to realize the hot plug management of the on-board network card on the hardware, so as to thoroughly shield or isolate the on-board network card on the hardware and switch back to the on-board network card freely and flexibly is a problem to be solved.

Disclosure of utility model

The utility model aims to provide an on-board network card hot plug control circuit which can thoroughly shield or isolate the on-board network card on hardware and can freely and flexibly switch back to the on-board network card, thereby realizing hot plug management of the on-board network card on the hardware.

The utility model provides an on-board network card hot plug control circuit which is arranged on a computer main board and comprises an on-board network card, a network card power switch, a network card power supply, a reset control module, a clock generator, a main control module and a switch circuit, wherein the on-board network card is connected to a PCIE interface of the main control module through a PCIE bus, the on-board network card comprises a power interface, a clock interface and a reset interface, the power interface is connected to the network card power supply through the network card power switch, the clock interface is connected to the clock generator, and the reset interface is connected to the reset control module; the switching circuit comprises a first output interface and a second output interface, wherein the first output interface is respectively connected to the main control module, the clock generator and the reset control module, the second output interface is connected to the network card power switch, the switching circuit controls the main control module to close or open the physical interface function of the PCIE interface through the first output interface, controls the clock generator to output or close an output clock signal to the clock interface, controls the reset control module to output a reset signal to the reset interface, and controls the network card power switch to be communicated with the power interface or disconnect the connection of the network card power with the power interface through the second output interface.

Preferably, the switch circuit further includes a status switch, where when the status switch is in a first state, the first output interface outputs a first status signal to the master control module, the clock generator, and the reset control module, the master control module starts a physical interface function of the PCIE interface, the clock generator outputs a clock signal to the clock interface, the second output interface outputs a first switch signal to the network card power switch, the network card power switch is connected to the network card power supply and the power interface, and the network card power supply supplies power to the on-board network card; when the state switch is in a second state, the first output interface outputs a second state signal to the main control module, the clock generator and the reset control module, the main control module closes the physical interface function of the PCIE interface, the clock generator closes the output clock signal to the clock interface, the second output interface outputs a second switch signal to the network card power switch, and the network card power switch disconnects the network card power supply from the power interface; the first output interface outputs the second state signal to the reset control module, and when the first state signal is converted into the first state signal, the reset control module outputs the reset signal to the reset interface.

Preferably, the switch circuit further comprises a switch unit, wherein a control end of the switch unit is connected to an output end of the status switch, and an output end of the switch unit is the first output interface; the output end of the status switch extends out of the second output interface.

Preferably, the switch unit is an NMOS field-effect transistor, the gate of the NMOS field-effect transistor is the control end of the switch unit, the drain of the NMOS field-effect transistor is the output end of the switch unit, the drain is further connected to a P3V3SB motherboard power supply via a first resistor, and the source of the NMOS field-effect transistor is grounded; the output end of the state switch outputs a low-level signal when the state switch is in the first state, and the output end of the state switch outputs a high-level signal when the state switch is in the second state.

Preferably, the network card power switch comprises a PMOS field effect transistor, wherein a gate of the PMOS field effect transistor is connected to the second output interface through a third resistor, a source of the PMOS field effect transistor is connected to the network card power supply, a drain of the PMOS field effect transistor is connected to the power interface, and a first capacitor is connected between the gate and the drain of the PMOS field effect transistor; the output end of the state switch outputs a low-level signal when the state switch is in the first state, and the output end of the state switch outputs a high-level signal when the state switch is in the second state.

Preferably, the output end of the status switch is grounded through a transient voltage suppression diode.

Preferably, the state switch is a single pole double throw switch, and the output end of the state switch is grounded when the state switch is in the first state, and the output end of the state switch is connected to the P3V3SB motherboard power supply through a second resistor when the state switch is in the second state.

Preferably, the reset control module includes a controller and an and gate, wherein a network card disable input end of the controller is connected to the first output interface, a network card disable output end of the controller is connected to a second input end of the and gate, a first input end of the and gate introduces a sys_ PCIERST # signal of the motherboard, and an output end of the and gate is connected to the reset interface of the on-board network card and is grounded through a fourth resistor and a second capacitor, respectively; the first output interface outputs the second state signal to the reset control module, and when the first state signal is converted into the first state signal, the reset control module delays for a preset time and then outputs the reset signal to the reset interface.

Preferably, the controller is an embedded controller or a complex programmable logic device.

Preferably, the main control module is a central processing unit or a platform controller hub.

The utility model has the beneficial effects that: the on-board network card hot plug control circuit controls the main control module, the clock generator to close the connection with the on-board network card, the network card power supply to supply power to the on-board network card and the reset control module to provide reset signals for the on-board network card through the switch circuit, can thoroughly shield or isolate the on-board network card on hardware, and can freely and flexibly switch back to the on-board network card, thereby realizing hot plug management of the on-board network card on hardware, meeting the hot plug requirements of the on-board network card in some professional application fields and facilitating seamless switching of the on-board network card in each application scene.

Drawings

For a further understanding of the nature and technical aspects of the present utility model, reference should be made to the following detailed description of the utility model and to the accompanying drawings, which are provided for purposes of reference only and are not intended to limit the utility model.

In the drawings of which there are shown,

Fig. 1 is a circuit block diagram of a hot plug control circuit of an on-board network card according to the present utility model.

Fig. 2 is a circuit diagram of an on-board network card hot plug control circuit according to an embodiment of the utility model.

Detailed Description

In order to further explain the technical means adopted by the present utility model and the effects thereof, the following detailed description is given with reference to the preferred embodiments of the present utility model and the accompanying drawings.

As shown in fig. 1, the on-board network card hot plug control circuit of the present utility model is configured on a computer motherboard, and includes an on-board network card 10, a network card power switch 20, a network card power supply 30, a reset control module 40, a clock generator 50, a main control module 60, and a switch circuit 70.

The on-board network card 10 is connected to a PCIE interface of the main control module 60 through a PCIE bus, so as to implement a network communication function under control of the main control module 60. The on-board network card 10 comprises a power interface, a clock interface and a reset interface, wherein the power interface is connected to the network card power supply 30 through the network card power switch 20, and the network card power supply 30 is used for supplying power to the on-board network card 10; the clock interface is connected to the clock generator 50, and the clock generator 50 is configured to provide a clock signal for the on-board network card 10; the reset interface is connected to the reset control module 40, and the reset control module 40 is configured to provide a reset signal for the on-board network card 10.

The switch circuit 70 includes a first output interface 71 and a second output interface 72, the first output interface 71 is connected to the main control module 60, the clock generator 50, and the reset control module 40, respectively; the second output interface 72 is connected to the network card power switch 20. The switch circuit 70 controls the main control module 60 to close or open the physical interface function of the PCIE interface through the first output interface 71, so as to disconnect the signal connection between the main control module 60 and the on-board network card 10 or establish the signal connection between the main control module 60 and the on-board network card 10; the first output interface 71 controls the clock generator 50 to output or close the clock interface outputting the clock signal to the on-board network card 10, and controls the reset control module 40 to output the reset signal to the reset interface of the on-board network card 10. The switch circuit 70 controls the network card power switch 20 to communicate the network card power supply 30 with the power interface of the on-board network card 10 through the second output interface 72, so that the network card power supply 30 can supply power to the on-board network card 10 through the network card power switch 20, or disconnect the connection between the network card power supply 30 and the power interface of the on-board network card 10, and at this time, the network card power supply 30 stops supplying power to the on-board network card 10.

Thus, when the on-board network card 10 works normally, the switch circuit 70 controls the network card power switch 20 to communicate the network card power supply 30 with the power interface of the on-board network card 10 via the second output interface 72, and the network card power supply 30 supplies power to the on-board network card 10; the switch circuit 70 controls the main control module 60 to start the physical interface function of the PCIE interface through the first output interface 71, the main control module 60 is in signal connection with the on-board network card 10, and controls the clock generator 50 to output a clock signal to the clock interface of the on-board network card 10 through the first output interface 71.

If the on-board network card 10 needs to be shielded or isolated, the switch circuit 70 controls the network card power switch 20 to disconnect the network card power supply 30 from the power interface of the on-board network card 10 through the second output interface 72; the switch circuit 70 controls the main control module 60 to close the physical interface function of the PCIE interface through the first output interface 71, so as to disconnect the signal connection between the main control module 60 and the on-board network card 10, and controls the clock generator 50 to close the clock interface outputting the clock signal to the on-board network card 10 through the first output interface 71, thereby realizing shielding or isolation of the on-board network card 10 from hardware.

If the network card 10 needs to be switched back, the switch circuit 70 controls the network card power switch 20 to communicate the network card power supply 30 with the power interface of the network card 10 via the second output interface 72, and the network card power supply 30 supplies power to the network card 10; the switch circuit 70 controls the main control module 60 to start the physical interface function of the PCIE interface through the first output interface 71, the main control module 60 is in signal connection with the on-board network card 10, controls the clock generator 50 to output a clock signal to the clock interface of the on-board network card 10 through the first output interface 71, and controls the reset control module 40 to output a reset signal to the reset interface of the on-board network card 10 through the first output interface 71, so that the on-board network card 10 can be switched and connected back to the motherboard system.

Therefore, the hot plug control circuit of the on-board network card can thoroughly shield or isolate the on-board network card on hardware, and can switch back to the on-board network card freely and flexibly, that is, the hot plug management of the on-board network card on hardware can be realized.

Specifically, the switch circuit 70 further includes a status switch 73, when the status switch 73 is in a first state, the first output interface 71 of the switch circuit 70 outputs a first status signal to the main control module 60, the clock generator 50 and the reset control module 40, and at this time, the main control module 60 opens the physical interface function of the PCIE interface thereof, establishes a signal connection between the main control module 60 and the on-board network card 10, and the clock generator 50 outputs a clock signal to the clock interface of the on-board network card 10; the second output interface 72 outputs a first switching signal to the network card power switch 20, the network card power switch 20 communicates the network card power supply 30 with the power interface of the on-board network card 10, and the network card power supply 30 supplies power to the on-board network card 10.

When the status switch 73 is in the second state, the first output interface 71 of the switch circuit 70 outputs a second status signal to the main control module 60, the clock generator 50 and the reset control module 40, at this time, the main control module 60 turns off the physical interface function of the PCIE interface, disconnects the signal connection between the main control module 60 and the on-board network card 10, and the clock generator 50 turns off the clock interface outputting a clock signal to the on-board network card 10; the second output interface 70 outputs a second switching signal to the network card power switch 20, and the network card power switch 20 disconnects the network card power supply 30 from the power interface of the on-board network card 10.

When the first output interface 71 is converted from outputting the second status signal to the reset control module 40 to outputting the first status signal to the reset control module 40, the reset control module 40 outputs the reset signal to the reset interface of the on-board network card 10.

Further, the switch circuit 70 may further include a switch unit 74, a control end of the switch unit 74 is connected to an output end of the status switch 73, and an output end of the switch unit 74 is the first output interface 71; the output of the status switch 73 extends out of the second output interface 72. That is, the state switch 73 of the switch circuit 70 outputs the first state signal or the second state signal to the main control module 60, the clock generator 50 and the reset control module 40 via the switch unit 74; and the status switch 73 may directly output the first switch signal or the second switch signal to the network card power switch 20.

In a preferred embodiment, the switch unit 74 is an NMOS field-effect transistor, a gate of the NMOS field-effect transistor is a control end of the switch unit 74, a drain of the NMOS field-effect transistor is an output end of the switch unit 74, the drain is further connected to a P3V3SB motherboard power supply via a first resistor, and a source of the NMOS field-effect transistor is grounded. The output terminal of the status switch 73 outputs a low level signal when the status switch 73 is in the first state (e.g., the output terminal of the status switch 73 is grounded), and the output terminal of the status switch 73 outputs a high level signal when the status switch 73 is in the second state (e.g., the output terminal of the status switch 73 is connected to the P3V3SB motherboard power supply via a second resistor). Therefore, when the status switch 73 is in the first state, the NMOS fet is turned off, and the drain of the NMOS fet, that is, the first status signal output by the first output interface 71, is a high level signal; when the status switch 73 is in the second state, the NMOS fet is turned off, and the drain of the NMOS fet, that is, the second status signal output by the first output interface 71, is a low level signal.

In a preferred embodiment, the network card power switch 20 includes a PMOS field effect transistor, where a gate of the PMOS field effect transistor is connected to the second output interface 72 via a third resistor, that is, to the output end of the status switch 73, a source of the PMOS field effect transistor is connected to the network card power supply 30, a drain of the PMOS field effect transistor is connected to the power interface of the on-board network card 10, and a first capacitor is connected between the gate and the drain of the PMOS field effect transistor. The output terminal of the status switch 73 outputs a low level signal when the status switch 73 is in the first state (e.g., the output terminal of the status switch 73 is grounded), and the output terminal of the status switch 73 outputs a high level signal when the status switch 73 is in the second state (e.g., the output terminal of the status switch 73 is connected to the P3V3SB motherboard power supply via a second resistor). Therefore, when the status switch 73 is in the first state, the second output interface 72 outputs the first switch signal, i.e. the low level signal, the PMOS fet is turned on, and the network card power supply 30 supplies power to the on-board network card 10 via the PMOS fet; when the status switch 73 is in the second state, the second output interface 72 outputs the second switch signal, i.e. the high level signal, the PMOS fet is turned off, and the network card power supply 30 does not supply power to the on-board network card 10.

Of course, the specific configurations of the switch unit 74 and the network card power switch 20 are not limited to the above, and other circuit configurations may be selected to achieve the same function.

Preferably, the output of the status switch 73 is also grounded via a tvs diode.

In a preferred embodiment, the status switch 73 is a single pole double throw switch, and the output terminal of the status switch 73 is grounded when the status switch 73 is in the first state, and the output terminal of the status switch 73 is connected to the P3V3SB motherboard power supply via a second resistor when the status switch 73 is in the second state.

Further, in a preferred embodiment, the reset control module 40 may include a controller 41 and an and gate 42, where a network card disable input of the controller 41 is connected to the first output interface 71, a network card disable output of the controller 41 is connected to a second input of the and gate 42, a first input of the and gate 42 introduces a sys_ PCIERST # signal of the motherboard (the sys_ PCIERST # signal of the motherboard remains high in a power-on state), and an output of the and gate 42 is connected to the reset interface of the on-board network card 10 and is grounded via a fourth resistor and a second capacitor, respectively. Specifically, as described above, the first status signal is a high level signal, the second status signal is a low level signal, and when the first output interface 71 is converted from outputting the second status signal to the reset control module 40, to outputting the first status signal to the reset control module 40, the reset control module 40 may delay the preset time and then output the reset signal to the reset interface of the on-board network card 10, so that the on-board network card 10 is reset, and the reset signal is a high level signal.

That is, when the status signal received by the network card disable input end of the controller 41 of the reset control module 40 from the low level to the high level, the controller 41 delays for a preset time, for example, 100ms, and then outputs the high level to the second input end of the and gate 42, and the sys_ PCIERST # signal phase from the motherboard is taken as the and gate 42 outputs the high level reset signal to the reset interface of the on-board network card 10, and the on-board network card 10 is reset on power, so that the timing requirement of the on-board network card 10 on power reset can be satisfied.

The logic device in the reset control module 40 is not limited to the and gate 42, and other structures may be used to achieve the same function.

In a preferred embodiment, the controller 41 may be an Embedded Controller (EC) or a Complex Programmable Logic Device (CPLD).

Further, the main control module 60 may be a Central Processing Unit (CPU) or a platform hub control (PCH).

Fig. 2 is a circuit diagram of an on-board network card hot plug control circuit according to an embodiment of the utility model. The on-board network card 10 of the on-board network card hot plug control circuit is a PCIE LAN network card, the main control module 60 is a central processing unit or a platform hub for controlling, and the controller 41 of the reset control module 40 is an embedded controller or a complex programmable logic device.

The switch circuit 70 comprises a state switch 73 (SWBTN 1) and a switch unit 74, wherein the state switch 73 is a single-pole double-throw switch and comprises a port 1, a port 2 and a port 3, wherein the port 2 is an output end of the state switch 73, the port 1 is grounded, the port 3 is connected with a P3V3SB main board power supply through a second resistor R2, the single-pole double-throw switch can be switched between the port 1 and the port 3, and when the port 1 is connected with the port 2, the port 2 of the state switch 73 is grounded; when the port 3 is connected to the port 2, i.e. the output end of the status switch 73 is connected to the P3V3SB motherboard power supply via the second resistor R2. Port 2 of the status switch 73 is also grounded via the tvs ESD 22.

The switch unit 74 is an NMOS field-effect transistor Q1, a gate of the NMOS field-effect transistor Q1 is a control end of the switch unit 74, and is connected to an output end of the status switch 73, that is, the port 2, a drain of the NMOS field-effect transistor Q1 is an output end of the switch unit 74, that is, a first output interface of the switch circuit 70, the drain is further connected to a P3V3SB motherboard power supply via a first resistor R1, and a source of the NMOS field-effect transistor Q1 is grounded.

The network card power switch 20 includes a PMOS field-effect transistor Q2, where a gate of the PMOS field-effect transistor Q2 is connected to a port 2 (shown by LANPWR _en signal in the figure) of the status switch 73 via a third resistor R3; the source electrode of the PMOS field-effect transistor Q2 is connected to the network card power supply 30, and in this embodiment, the network card power supply 30 is a P3V3 motherboard power supply; the drain electrode of the PMOS fet Q2 is connected to the Power interface Power (shown by p3v3_lan signal in the figure) of the on-board network card 10, and a first capacitor C1 is connected between the gate electrode and the drain electrode of the PMOS fet Q2.

The drain of the NMOS fet Q1 is connected to the reset control module 40, the clock generator 50, and the main control module 60 (shown as lan_disable# signal) as the output end of the switch unit 74, that is, the first output interface of the switch circuit 70.

Specifically, the Reset control module 40 includes a controller 41 and an and gate 42, the drain electrode of the NMOS fet Q1 is connected to a network card Disable input lan_disable_in of the controller 41, a network card Disable output lan_disable_out of the controller 41 is connected to a second input of the and gate 42, a first input of the and gate 42 introduces a sys_ PCIERST # signal of the motherboard, and an output of the and gate 42 is connected to a Reset interface Reset of the on-board network card 10 and is grounded via a fourth resistor R4 and a second capacitor C2, respectively.

The drain electrode of the NMOS field effect transistor Q1 is also connected to the Out1_Strap port of the Clock generator 50, and the Clock signal output interface clock_OUT1 of the Clock generator 50 is connected to the Clock interface Clock of the on-board network card 10.

The drain electrode of the NMOS fet Q1 is further connected to a port1_prsnt Port of the main control module 60, and the on-board network card 10 is connected to a PCIE interface pcie_port1 of the main control module 60 through a PCIE BUS.

In the hot plug control circuit of the on-board network card shown in fig. 2, when the on-board network card 10 is in a normal working state, the Port1 and the Port 2 of the status switch 73 are connected, the status switch 73 is in a first state, the NMOS field effect transistor Q1 is turned off, the PMOS field effect transistor Q2 is turned on, the drain electrode of the NMOS field effect transistor Q1 keeps outputting a high level signal (a first status signal) to the reset control module 40, the clock generator 50 and the master control module 60, the clock generator 50 keeps outputting a clock signal to the on-board network card 10, the master control module 60 keeps turning on the physical interface function of the PCIE interface pcie_port1, and the P3V3 motherboard power supply keeps supplying power to the on-board network card 10.

When the on-board network card 10 is to be turned off, the Port 3 and the Port 2 of the status switch 73 are connected, the status switch 73 is in the second state, the NMOS field-effect transistor Q1 is turned on, the PMOS field-effect transistor Q2 is turned off, the drain electrode of the NMOS field-effect transistor Q1 outputs a low-level signal (second status signal) to the reset control module 40, the clock generator 50 and the main control module 60, the clock generator 50 turns off the output clock signal to the on-board network card 10, the main control module 60 turns off the physical interface function of the PCIE interface pcie_port1, and the P3V3 main board power supply no longer supplies power to the on-board network card 10. Thus, the on-board network card 10 is completely shielded or isolated from the motherboard hardware.

When the on-board network card 10 is to be switched back, the Port1 and the Port 2 of the status switch 73 are connected again, the status switch 73 enters the first status, the NMOS fet Q1 is turned off, the PMOS fet Q2 is turned on, the P3V3 motherboard power supply supplies power to the on-board network card 10 via the PMOS fet Q2, the drain of the NMOS fet Q1 outputs a high level signal (first status signal) to the reset control module 40, the clock generator 50 and the master control module 60, the clock generator 50 outputs a clock signal to the on-board network card 10, the master control module 60 starts the physical interface function of the PCIE interface pcie_port1 thereof, the controller 41 of the reset control module 40 outputs a high level signal (ec_lan_rst# signal in the figure) to the second input end of the and gate 42 after delaying for a preset time, and the gate 42 outputs a high level reset signal (sys_ PCIERST # signal phase and a high level phase to the reset control module 40) to the on-board network card RST 10, thereby realizing the reset interface of the on-board network card 10. Therefore, the on-board network card 10 can be switched back on the main board hardware again, and the on-board network card 10 can enter the working state again.

In summary, the on-board network card hot plug control circuit of the utility model controls the main control module, the clock generator to close the connection with the on-board network card, the network card power supply to supply power to the on-board network card and the reset control module to provide the reset signal of the on-board network card through the switch circuit, can thoroughly shield or isolate the on-board network card on hardware, and can switch back to the on-board network card freely and flexibly, thereby realizing hot plug management of the on-board network card on hardware, meeting the hot plug requirement of the on-board network card in some professional application fields, and facilitating seamless switching of the on-board network card in each application scene.

Besides ensuring that the on-board network card is thoroughly shielded or isolated on hardware and flexibly switched back to the on-board network card, the hot plug control circuit of the on-board network card can also cooperate with a BIOS system and an operating system to realize the shielding or isolation of the on-board network card on hardware and the driving unloading of the on-board network card on software, and the switching back of the on-board network card on hardware and the driving of reinstalling the on-board network card on software.

When the method is implemented, the main control module can inform an operating system to unload the drive of the on-board network card through a BIOS system when the physical interface function of the PCIE interface is closed by receiving a second state signal transmitted by the switch circuit; when the physical interface function of the PCIE interface is started by receiving the first state signal transmitted by the switch circuit, the BIOS system informs the operating system of installing the drive of the on-board network card, so that the unloading of the on-board network card software is synchronously realized.

Specifically, when the main control module receives the second status signal transmitted by the switch circuit, the main control module informs the operating system to unload the PCIE related driver through the BIOS system, and closes a physical interface function of a PCIE interface correspondingly connected to the on-board network card; and then the operating system re-enumerates all PCIE peripheral devices, re-mounts corresponding peripheral device drivers, and re-allocates MEM and IO resources, thereby realizing the shielding or isolation of the on-board network card on hardware and the unloading on software.

When the main control module receives the first state signal transmitted by the switch circuit, the main control module starts the physical interface function of the PCIE interface correspondingly connected with the on-board network card, informs the operating system of unloading all PCIE related drivers through the BIOS system, then the operating system enumerates all PCIE peripheral devices again, and reloads the corresponding peripheral device drivers, and reallocates MEM and IO resources, thereby simultaneously realizing switching back of the on-board network card on hardware and reinstalling the driver of the on-board network card on software.

In the above, it should be apparent to those skilled in the art that various other modifications and variations can be made in accordance with the technical solution and the technical idea of the present utility model, and all such modifications and variations are intended to fall within the scope of the claims of the present utility model.

Claims (10)

1. The on-board network card hot plug control circuit is used for being arranged on a computer main board and is characterized by comprising an on-board network card, a network card power switch, a network card power supply, a reset control module, a clock generator, a main control module and a switch circuit, wherein the on-board network card is connected to a PCIE interface of the main control module through a PCIE bus, the on-board network card comprises a power interface, a clock interface and a reset interface, the power interface is connected to the network card power supply through the network card power switch, the clock interface is connected to the clock generator, and the reset interface is connected to the reset control module; the switching circuit comprises a first output interface and a second output interface, wherein the first output interface is respectively connected to the main control module, the clock generator and the reset control module, the second output interface is connected to the network card power switch, the switching circuit controls the main control module to close or open the physical interface function of the PCIE interface through the first output interface, controls the clock generator to output or close an output clock signal to the clock interface, controls the reset control module to output a reset signal to the reset interface, and controls the network card power switch to be communicated with the power interface or disconnect the connection of the network card power with the power interface through the second output interface.

2. The on-board network card hot plug control circuit of claim 1, wherein the switch circuit further comprises a status switch, when the status switch is in a first state, the first output interface outputs a first status signal to the master control module, the clock generator and the reset control module, the master control module starts a physical interface function of the PCIE interface, the clock generator outputs a clock signal to the clock interface, the second output interface outputs a first switch signal to the network card power switch, the network card power switch communicates the network card power supply with the power interface, and the network card power supply supplies power to the on-board network card; when the state switch is in a second state, the first output interface outputs a second state signal to the main control module, the clock generator and the reset control module, the main control module closes the physical interface function of the PCIE interface, the clock generator closes the output clock signal to the clock interface, the second output interface outputs a second switch signal to the network card power switch, and the network card power switch disconnects the network card power supply from the power interface; the first output interface outputs the second state signal to the reset control module, and when the first state signal is converted into the first state signal, the reset control module outputs the reset signal to the reset interface.

3. The on-board network card hot plug control circuit according to claim 2, wherein the switch circuit further comprises a switch unit, a control end of the switch unit is connected to an output end of the status switch, and an output end of the switch unit is the first output interface; the output end of the status switch extends out of the second output interface.

4. The on-board network card hot plug control circuit according to claim 3, wherein the switch unit is an NMOS field-effect transistor, a gate of the NMOS field-effect transistor is a control end of the switch unit, a drain of the NMOS field-effect transistor is an output end of the switch unit, the drain is further connected to a P3V3SB motherboard power supply via a first resistor, and a source of the NMOS field-effect transistor is grounded; the output end of the state switch outputs a low-level signal when the state switch is in the first state, and the output end of the state switch outputs a high-level signal when the state switch is in the second state.

5. The on-board network card hot plug control circuit according to claim 3 or 4, wherein the network card power switch comprises a PMOS field effect transistor, a gate of the PMOS field effect transistor is connected to the second output interface through a third resistor, a source of the PMOS field effect transistor is connected to the network card power supply, a drain of the PMOS field effect transistor is connected to the power supply interface, and a first capacitor is connected between the gate and the drain of the PMOS field effect transistor; the output end of the state switch outputs a low-level signal when the state switch is in the first state, and the output end of the state switch outputs a high-level signal when the state switch is in the second state.

6. The on-board network card hot plug control circuit of claim 5, wherein the output of the status switch is further coupled to ground via a transient voltage suppression diode.

7. The hot plug control circuit of claim 2, 3 or 4, wherein the status switch is a single pole double throw switch, and an output terminal of the status switch is grounded when the status switch is in the first state, and an output terminal of the status switch is connected to a P3V3SB motherboard power supply via a second resistor when the status switch is in the second state.

8. The on-board network card hot plug control circuit according to claim 2, wherein the reset control module comprises a controller and an and gate, wherein a network card disable input end of the controller is connected to the first output interface, a network card disable output end of the controller is connected to a second input end of the and gate, the first input end of the and gate introduces a sys_ PCIERST # signal of the motherboard, and an output end of the and gate is connected to the reset interface of the on-board network card and is grounded via a fourth resistor and a second capacitor, respectively; the first output interface outputs the second state signal to the reset control module, and when the first state signal is converted into the first state signal, the reset control module delays for a preset time and then outputs the reset signal to the reset interface.

9. The on-board network card hot plug control circuit of claim 8, wherein the controller is an embedded controller or a complex programmable logic device.

10. The on-board network card hot plug control circuit of claim 1, wherein the main control module is a central processing unit or a platform controller hub.