CN222148126U - Semiconductor device, memory system, and electronic apparatus - Google Patents
Semiconductor device, memory system, and electronic apparatus Download PDFInfo
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- CN222148126U CN222148126U CN202420587606.9U CN202420587606U CN222148126U CN 222148126 U CN222148126 U CN 222148126U CN 202420587606 U CN202420587606 U CN 202420587606U CN 222148126 U CN222148126 U CN 222148126U
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Abstract
The utility model discloses a semiconductor device, a storage system and electronic equipment, wherein the semiconductor device comprises a first electrode, a storage layer and a second electrode, the storage layer comprises a first surface, a second surface and a first side surface, the first surface and the second surface are oppositely arranged, the first side surface is connected between the first surface and the second surface, the first electrode is positioned on one side of the first surface, the second electrode is positioned on one side of the second surface, the storage layer is a bidirectional threshold switch layer, and the semiconductor device further comprises a first protection layer covered on the first side surface.
Description
Technical Field
The present utility model relates to the field of semiconductor technologies, and in particular, to a semiconductor device, a memory system, and an electronic apparatus.
Background
The ovonic threshold switch (Ovonic Threshold Switch, OTS) is a switching device designed based on an ovonic material (e.g., a chalcogenide compound), and is currently used in various programmable resistive memories, particularly in a select-Only-Memory (SOM). In SOM, OTS gates material as a storage medium to implement read-write functions of the memory.
However, in a SOM memory using an OTS gating material as a memory layer, because the memory cell lacks effective protection at the sidewall of the memory layer, the sidewall of the memory layer is prone to undesirable phenomena such as oxidation and etching damage during the process, and electrical leakage is prone to occur during the testing and use processes, thereby causing the electrical property of the memory layer to be affected.
Disclosure of utility model
The embodiment of the utility model provides a semiconductor device, a storage system and electronic equipment, which can improve the protection effect on the first side surface of a storage layer, reduce the probability of oxidation, etching damage and electric leakage phenomena of the storage layer, improve the threshold transition voltage drift phenomenon of the semiconductor device and improve the yield of the semiconductor device.
The embodiment of the utility model provides a semiconductor device, which comprises a first electrode, a storage layer and a second electrode;
The storage layer comprises a first surface, a second surface and a first side surface, wherein the first surface and the second surface are oppositely arranged, the first side surface is connected between the first surface and the second surface, the first electrode is positioned on one side of the first surface, and the second electrode is positioned on one side of the second surface;
The storage layer is an bidirectional threshold switch layer, and the semiconductor device further comprises a first protection layer covering the first side face.
In some embodiments of the utility model, the first protective layer is disposed around the storage layer and covers the first side.
In some embodiments of the utility model, the first electrode includes a third surface facing the storage layer and a second side connected to the third surface, the second electrode includes a fourth surface facing the storage layer and a third side connected to the fourth surface, and the first protective layer further covers the second side and the third side and is disposed around the first electrode and the second electrode.
In some embodiments of the utility model, the semiconductor device further comprises a second protective layer located on a side of the first protective layer remote from the memory layer.
In some embodiments of the present utility model, the first protection layer includes a first protection sub-layer and a second protection sub-layer, two second protection sub-layers disposed opposite to each other and spaced apart from each other are disposed between two first protection sub-layers disposed opposite to each other and spaced apart from each other, the first electrode, the storage layer, and the second electrode are disposed in a cavity formed by the first protection sub-layer and the second protection sub-layer, and the first protection sub-layer and the second protection sub-layer respectively cover the first side surface;
The first protection sub-layer protrudes from the second protection sub-layer along two ends in a first direction, the first direction is an extending direction of the first protection sub-layer in a top view, and the second protection layer is located at one side, far away from the storage layer, of the first protection sub-layer and the second protection sub-layer.
In some embodiments of the present utility model, the second protection layer includes a third protection sub-layer and a fourth protection sub-layer, the third protection sub-layer is located at a side of the first protection sub-layer away from the storage layer, two ends of the third protection sub-layer in the first direction are flush with two ends of the first protection sub-layer in the first direction, and the fourth protection sub-layer is located at a side of the second protection sub-layer away from the storage layer and is connected with two ends of the first protection sub-layer protruding from the second protection sub-layer.
In some embodiments of the utility model, the first electrode is in contact with the first surface and the second electrode is in contact with the second surface;
Or the semiconductor device further comprises a barrier layer between the first electrode and the memory layer and/or between the second electrode and the memory layer.
In some embodiments of the present utility model, the semiconductor device further includes a word line and a bit line, the first electrode is connected to one of the word line and the bit line, and the second electrode is connected to the other of the word line and the bit line.
In accordance with the above object of the present utility model, there is also provided a memory system including a controller coupled with the semiconductor device to control the semiconductor device, and the semiconductor device.
According to the above object of the present utility model, an embodiment of the present utility model further provides an electronic device, which includes the storage system.
The embodiment of the utility model provides a semiconductor device, a storage system and electronic equipment, wherein a first protection layer is arranged on a first side surface of a storage layer to protect the first side surface of the storage layer, so that the probability of oxidation, etching damage and electric leakage phenomena of the storage layer is reduced, the threshold transition voltage drift phenomenon of the semiconductor device is improved, and the electrical stability and yield of the semiconductor device are improved.
Drawings
The technical solution and other advantageous effects of the present utility model will be made apparent by the following detailed description of the specific embodiments of the present utility model with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present utility model;
fig. 2 is a schematic circuit diagram of a semiconductor device according to an embodiment of the present utility model;
fig. 3 is a schematic diagram of another structure of a semiconductor device according to an embodiment of the present utility model;
fig. 4 is a schematic top view of a semiconductor device according to an embodiment of the present utility model;
FIG. 5 is a schematic diagram of a memory system according to an embodiment of the present utility model;
fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present utility model.
Detailed Description
The technical solutions in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model. It will be apparent that the described embodiments are only some, but not all, embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to fall within the scope of the utility model.
The following disclosure provides many different embodiments, or examples, for implementing different features of the utility model. In order to simplify the present disclosure, components and arrangements of specific examples are described below. They are, of course, merely examples and are not intended to limit the utility model. Furthermore, the present utility model may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present utility model provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the application of other processes and/or the use of other materials.
Referring to fig. 1, an embodiment of the present utility model provides a semiconductor device, which includes a first electrode 11, a memory layer 13, and a second electrode 12.
Wherein the storage layer 13 includes a first surface 131 and a second surface 132 disposed opposite to each other, and a first side 133 connected between the first surface 131 and the second surface 132, the first electrode 11 is located on one side of the first surface 131, and the second electrode 12 is located on one side of the second surface 132.
In some embodiments, the storage layer 13 is an ovonic threshold switch layer, and it is understood that the storage layer 13 is an ovonic threshold switch (Ovonic Threshold Switch, OTS). OTS is used in various programmable memories (e.g., SOM). In SOM, OTS gates material as a storage medium to implement read-write functions of the memory.
Wherein the semiconductor device further comprises a first protection layer 21 covering the first side 133. In the application process, the first protection layer 21 is disposed on the first side 133 of the storage layer 13 to protect the first side 133 of the storage layer 13, so that the probability of oxidation, etching damage and leakage phenomena of the storage layer 13 is reduced, and the electrical stability and yield of the semiconductor device are improved.
With continued reference to fig. 1, the semiconductor device provided in the embodiment of the utility model includes a plurality of memory cells 10, and each memory cell 10 may include the first electrode 11 and the second electrode 12 disposed opposite to each other, and the memory layer 13 disposed between the first electrode 11 and the second electrode 12.
When a voltage pulse in a preset direction is applied between the first electrode 11 and the second electrode 12, the semiconductor device is in a SET state (low-resistance state) and has a lower first threshold transition voltage, and then a voltage pulse in a direction opposite to the preset direction is applied to the semiconductor device, and the semiconductor device is RESET to a high-resistance state (RESET state) and has a higher second threshold transition voltage. Further, in the reading process of the semiconductor device, by applying a value between the first threshold transition voltage and the second threshold transition voltage between the first electrode 11 and the second electrode 12, it is possible to read whether the semiconductor device is in the SET or RESET state.
In some embodiments, the memory layer 13 contains chalcogenides, such As compounds of arsenic (As), selenium (Se), and germanium (Ge) (AsSeGe), compounds of arsenic (As), selenium (Se), germanium (Ge), and silicon (Si) (AsSeGeSi), compounds of arsenic (As), selenium (Se), germanium (Ge), silicon (Si), and indium (In) (ASSEGESIIN), compounds of arsenic (As), selenium (Se), germanium (Ge), and indium (In) (AsSeGeIn).
With continued reference to fig. 1, 2 and 3, in some embodiments, the semiconductor device further includes a bit line 31 and a word line 32, the first electrode 11 is connected to one of the bit line 31 and the word line 32, the second electrode 12 is connected to the other of the bit line 31 and the word line 32, and the first electrode 11 is connected to the bit line 31 and the second electrode 12 is connected to the word line 32 in the drawings provided by the present utility model.
Referring to fig. 1 and 2, the bit lines 31 and the word lines 32 are used for loading signals to the first electrode 11 and the second electrode 12, respectively, and in the semiconductor device, a plurality of the memory cells 10 may be arranged in an array, and a plurality of the memory cells 10 in a same row may be connected to a same word line 32 and to different bit lines 31, and a plurality of the memory cells 10 in a same column may be connected to a same bit line 31 and to different word lines 32.
In some embodiments, the first electrode 11 may be in contact with the first surface 131, the second electrode 12 may be in contact with the second surface 132, i.e. the storage layer 13 is directly disposed between the first electrode 11 and the second electrode 12, the first electrode 11 is directly connected to the storage layer 13, and the second electrode 12 is also directly connected to the storage layer 13.
In other embodiments, referring to fig. 3, the semiconductor device further includes a barrier layer 40, the barrier layer 40 is located between the first electrode 11 and the storage layer 13, and/or the barrier layer 40 is located between the second electrode 12 and the storage layer 13, i.e., the semiconductor device may include one barrier layer 40 and may be located between the first electrode 11 and the storage layer 13 or between the second electrode 12 and the storage layer 13, or the semiconductor device may include two barrier layers 40, and the two barrier layers 40 are located between the first electrode 11 and the storage layer 13 and between the second electrode 12 and the storage layer 13, respectively.
For example, the barrier layer 40 includes a first barrier layer 41 and a second barrier layer 42, and the first barrier layer 41 is located between the first electrode 11 and the storage layer 13, and the second barrier layer 42 is located between the second electrode 12 and the storage layer 13.
In some embodiments, the barrier layer 40 may be used to prevent the material in the first electrode 11 and the second electrode 12 from diffusing into the storage layer 13 to reduce the probability of the semiconductor device being shorted or not turned off. The barrier layer 40 may have a thickness of 5 to 50 nanometers, for example, the barrier layer may be a layer of conductive material having a thickness of 20 nanometers. The barrier layer 40 may comprise carbon, or a combination of silicon and carbon, or other materials. When the barrier layer 40 is made of other materials, it may be a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), titanium boron nitride (TiBN), zirconium silicon nitride (ZrSiN), tungsten silicon nitride (WSiN), tungsten boron nitride (WBN), zirconium aluminum nitride (ZrAlN), molybdenum silicon nitride (MoSiN), molybdenum aluminum nitride (WAIN), tantalum silicon nitride (TaSiN), or tantalum aluminum nitride (TaAlN). In addition to metal nitride, the barrier layer 40 may include doped polysilicon, tungsten (W), copper (Cu), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium silicide (TiSi), tantalum silicide (TaSi), titanium Tungsten (TiW), titanium oxynitride (ton), titanium aluminum oxynitride (TiAlON), tungsten oxynitride (WON), tantalum oxynitride (TaON), or the like.
In the related art, the storage unit 10 lacks effective protection at the side wall of the OTS storage layer, so that the side wall of the OTS storage layer is prone to generate electric leakage, oxidation, etching damage and other adverse phenomena in the process, so that the threshold transition voltage of the OTS storage layer is shifted, and the electrical property of the OTS storage layer is affected; therefore, the semiconductor device provided in the embodiment of the present utility model further includes the first protection layer 21, and the first protection layer 21 covers the first side 133 of the storage layer 13, so as to protect the first side 133 of the storage layer 13, reduce the probability of oxidation, etching damage and leakage phenomena of the storage layer 13, improve the threshold transition voltage drift phenomenon of the semiconductor device, and improve the electrical stability and yield of the semiconductor device.
Referring to fig. 1 and fig. 4, in some embodiments, the first protection layer 21 is disposed around the storage layer 13 and covers the first side 133, that is, the first protection layer 21 covers all of the first side 133 of the storage layer 13, so as to better protect the storage layer 13.
In some embodiments, the first electrode 11 includes a third surface 111 facing the storage layer 13 and a second side 112 connected to the third surface 111, the second electrode 12 further includes a fourth surface 121 facing the storage layer 13 and a third side 122 connected to the fourth surface 121, and the first protection layer 21 further covers the second side 112 and the third side 122 and is disposed around the first electrode 11 and the second electrode 12, that is, the first protection layer 21 surrounds the storage unit 10 and covers a side wall of the storage unit 10 to provide protection to the entire side of the storage unit 10.
In some embodiments, the first protective layer 21 contains a nitride, for example, silicon nitride, and the first protective layer 21 may be synthesized using a silicon precursor and an ammonia precursor, where the silicon precursor may include SiCl 4, silane (SiH 4), trisilylamine (TSA, N (SiH 3)3), neopentasilane (NPS), (SiH 3)4 Si), iodosilane, bromosilane, alkylaminosilane (for example ,SiH(N(CH3)2)3、(SiH2(NHtBu)2)、C9H29N3Si3、C6H17NSi、C9H25N3Si、C8H22N2Si) or a combination thereof), and the ammonia precursor may include ammonia (NH 3), hydrazine (N 2H4) or a combination thereof, and further preferably, the ammonia precursor may include ammonia, and the generated silicon nitride film is more dense due to the easier reaction of the ammonia, which may effectively improve the protective effect of the first protective layer 21, further reduce the probability of oxidation, etching damage and leakage phenomena of the storage layer 13, and improve the electrical stability and yield of the semiconductor device.
In some embodiments, after the first protective layer 21 is formed, in order to obtain a denser film layer, plasma may be formed using, for example, helium gas to treat the first protective layer 21 so as to fill defect voids in the first protective layer 21, thereby forming the first protective layer 21 having high quality and high compactness.
In some embodiments, the thickness of the first protective layer 21 may be greater than or equal to 0.5nm and less than or equal to 5nm.
The memory cell 10 may have a quadrangular shape in a plan view, and the first protective layer 21 continuously surrounds four sides of the memory cell 10.
In some embodiments, the first protection layer 21 includes a first protection sub-layer 211 and a second protection sub-layer 212, two second protection sub-layers 212 disposed opposite and at intervals are disposed between two first protection sub-layers 211 disposed opposite and at intervals, and the two first protection sub-layers 211 and the two second protection sub-layers 212 surround to form a cavity, the first electrode 11, the storage layer 13, and the second electrode 12 are disposed in the cavity formed by the first protection sub-layers 211 and the second protection sub-layers 212, and the first protection sub-layers 211 and the second protection sub-layers 212 respectively cover the first side 133.
In some embodiments, the first protection sub-layer 211 extends along a first direction X in fig. 4, the second protection sub-layer 212 extends along a second direction Y in fig. 4, and the first direction is an extending direction of the first protection sub-layer 211 in a top view, and the second direction Y is an extending direction of the second protection sub-layer 212 in a top view.
In some embodiments, the first protective sub-layer 211 is made using ammonia, or the second protective sub-layer 212 is made using ammonia, or both the first protective sub-layer 211 and the second protective sub-layer 212 are made using ammonia.
In some embodiments, referring to fig. 2 and 4, the first direction X may be the extending direction of the word line 32, and the second direction Y may be the extending direction of the bit line 31.
In some embodiments, the first protective sub-layer 211 is treated with a helium plasma after formation, or the second protective sub-layer 212 is treated with a helium plasma after formation, or both the first protective sub-layer 211 and the second protective sub-layer 212 are treated with a helium plasma after formation.
In some embodiments, the first protective layer 21 also covers the sides of the bit line 31 and the word line 32.
In some embodiments, the semiconductor device further comprises a second protection layer 22, the second protection layer 22 being located on a side of the first protection layer 21 remote from the storage layer 13.
Further, the second protection layer 22 covers a side of the first protection layer 21 away from the storage layer 13, the first electrode 11, and the second electrode 12.
Further, the second protection layer 22 also covers a side of the first protection layer 21 away from the bit line 31 and the word line 32.
In some embodiments, the second protection layer 22 is located on a side of the first protection sub-layer 211 and the second protection sub-layer 212 away from the storage layer 13, and in particular, the second protection layer 22 includes a third protection sub-layer 221 and a fourth protection sub-layer 222, the third protection sub-layer 221 is located on a side of the first protection sub-layer 211 away from the storage layer 13, and the fourth protection sub-layer 222 is located on a side of the second protection sub-layer 212 away from the storage layer 13.
In some embodiments, the second protective layer 22 may continuously cover the side of the first protective layer 21 away from the storage layer 13.
In other embodiments, referring to fig. 1 and 4, the second protection layer 22 may also be discontinuously covered on the side of the first protection layer 21 away from the storage layer 13, where two ends of the first protection sub-layer 211 along the first direction X protrude from the second protection sub-layer 212, two ends of the third protection sub-layer 221 along the first direction X are flush with two ends of the first protection sub-layer 211 along the first direction, and the fourth protection sub-layer 222 is connected with two ends of the first protection sub-layer 211 protruding from the second protection sub-layer 212. The first protective sub-layer 211 protrudes from the surface of the second protective layer 22 away from the first protective layer 21 at both ends of the second protective sub-layer 212 in the first direction X to form a flat surface on the side of the second protective layer 22 away from the first protective layer 21.
In some embodiments, the thickness of the second protective layer 22 may be greater than or equal to 0.5nm and less than or equal to 5nm.
It should be noted that, between the plurality of memory cells 10 in the semiconductor device, a heat insulating material is further provided, that is, between adjacent memory cells 10, the heat insulating material is filled between the second protective layer 22 surrounding one of the memory cells 10 and the second protective layer 22 surrounding the other memory cell 10, and the heat insulating material is a special material containing carbon (C), nitrogen (N), and O, and has good filling property and heat insulating effect, and can play a role in spacing and protecting the plurality of memory cells 10.
In some embodiments, the second protective layer 22 contains an oxide, such as silicon oxide, and the second protective layer 22 may also act as an adhesion enhancing layer, where the second protective layer 22 is dense, not only to protect the material in the memory cell 10 from oxidation, but also to increase adhesion with the thermal insulating material.
By arranging the first protection layer 21 on the first side 133 of the storage layer 13, the utility model protects the first side 133 of the storage layer 13, reduces the probability of oxidation, etching damage and leakage phenomena of the storage layer 13, and improves the electrical stability and yield of the semiconductor device.
In addition, referring to fig. 5, the memory system 50 includes the semiconductor device 51 described in the above embodiment, and the semiconductor device 51 may be a memory or a part of a memory, and in the embodiment of the present utility model, the semiconductor device 51 is taken as an example of the memory to be described.
In some embodiments, the memory system 50 further includes the controller 52, where the controller 52 is coupled to the semiconductor device 51 and is used to control the semiconductor device 51 to store data, and the semiconductor device 51 is a semiconductor device manufactured by the manufacturing method of the semiconductor device described in the above embodiments or the semiconductor device described in the above embodiments.
In some embodiments, the controller 52 may control the semiconductor device 51 through a channel CH, and the semiconductor device 51 may perform an operation based on the control of the controller 52 in response to a request from a host. The semiconductor device 51 may receive a command CMD and an address ADDR from the controller 52 through a channel CH and access an area selected from the memory array in response to the address. In other words, the semiconductor device 51 may perform an internal operation corresponding to a command on an area selected by an address.
In some embodiments, the storage system 50 may be implemented to include, but is not limited to, multimedia cards such as universal flash memory storage (UFS) devices, solid State Drives (SSDs), MMC, eMMC, RS-MMC and micro-MMC forms, secure digital cards in SD, mini SD and micro SD forms, personal Computer Memory Card International Association (PCMCIA) card type storage devices, peripheral Component Interconnect (PCI) type storage devices, PCI-express (PCI-E) type storage devices, compact Flash (CF) cards, high-speed computing interconnects (Compute Express Link, CXL), high-bandwidth memory (High Bandwidth Memory, HBM), smart media cards or memory sticks, and the like.
In some embodiments, the storage system 50 may be used on a computer, a television, a set-top box, a vehicle-mounted terminal product, etc.
Referring to fig. 6, some embodiments of the present utility model further provide an electronic device 60, where the electronic device 60 includes the storage system 50, and the storage system 50 is a storage system described in the foregoing embodiments of the present utility model, specifically, the electronic device 60 may include, but is not limited to, any device capable of storing data, such as a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a wearable device, a mobile power supply, and the like.
The electronic equipment provided by the embodiments of the utility model has the same beneficial effects as the storage system provided by the embodiments of the utility model.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
The above description of the semiconductor device, the storage system and the electronic device provided by the embodiments of the present utility model has been provided in detail, and specific examples are applied to the description of the principles and implementation manners of the present utility model, where the description of the above embodiments is only for helping to understand the technical solutions and core ideas of the present utility model, and those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some technical features therein, and these modifications or substitutions do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present utility model.
Claims (10)
1. A semiconductor device comprising a first electrode, a memory layer, and a second electrode;
The storage layer comprises a first surface, a second surface and a first side surface, wherein the first surface and the second surface are oppositely arranged, the first side surface is connected between the first surface and the second surface, the first electrode is positioned on one side of the first surface, and the second electrode is positioned on one side of the second surface;
The storage layer is an bidirectional threshold switch layer, and the semiconductor device further comprises a first protection layer covering the first side face.
2. The semiconductor device according to claim 1, wherein the first protective layer is disposed around the memory layer and covers the first side.
3. The semiconductor device according to claim 2, wherein the first electrode includes a third surface facing the memory layer and a second side surface connected to the third surface, wherein the second electrode includes a fourth surface facing the memory layer and a third side surface connected to the fourth surface, wherein the first protective layer further covers the second side surface and the third side surface and is disposed around the first electrode and the second electrode.
4. The semiconductor device of claim 1, further comprising a second protective layer located on a side of the first protective layer remote from the memory layer.
5. The semiconductor device according to claim 4, wherein the first protective layer includes a first protective sub-layer and a second protective sub-layer, the two second protective sub-layers disposed opposite and apart are disposed between the two first protective sub-layers disposed opposite and apart, the first electrode, the memory layer, and the second electrode are disposed in a cavity formed by the first protective sub-layer and the second protective sub-layer, and the first protective sub-layer and the second protective sub-layer respectively cover the first side surface;
The first protection sub-layer protrudes from the second protection sub-layer along two ends in a first direction, the first direction is an extending direction of the first protection sub-layer in a top view, and the second protection layer is located at one side, far away from the storage layer, of the first protection sub-layer and the second protection sub-layer.
6. The semiconductor device according to claim 5, wherein the second protective layer includes a third protective sub-layer and a fourth protective sub-layer, the third protective sub-layer is located on a side of the first protective sub-layer away from the memory layer, both ends of the third protective sub-layer in the first direction are flush with both ends of the first protective sub-layer in the first direction, and the fourth protective sub-layer is located on a side of the second protective sub-layer away from the memory layer and connected to both ends of the first protective sub-layer protruding from the second protective sub-layer.
7. The semiconductor device according to claim 1, wherein the first electrode is in contact with the first surface and the second electrode is in contact with the second surface;
Or the semiconductor device further comprises a barrier layer between the first electrode and the memory layer and/or between the second electrode and the memory layer.
8. The semiconductor device according to claim 1, further comprising a word line and a bit line, wherein the first electrode is connected to one of the word line and the bit line, and wherein the second electrode is connected to the other of the word line and the bit line.
9. A memory system comprising a controller and the semiconductor device of any one of claims 1 to 8, the controller being coupled to the semiconductor device to control the semiconductor device.
10. An electronic device, characterized in that, the electronic device comprising the storage system of claim 9.
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| CN202420587606.9U CN222148126U (en) | 2024-03-25 | 2024-03-25 | Semiconductor device, memory system, and electronic apparatus |
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Denomination of utility model: Semiconductor devices, storage systems, and electronic equipment Granted publication date: 20241210 Pledgee: CITIC Bank Limited by Share Ltd. Wuhan branch Pledgor: Xincun Technology (Wuhan) Co.,Ltd. Registration number: Y2025980014559 |
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