CN222321509U - A 2b/cycle Successive Approximation Analog-to-Digital Converter with Dual Comparators - Google Patents

Abstract

The utility model discloses a 2b/cycle successive approximation analog-to-digital converter with double comparators. The analog-digital conversion circuit comprises a DAC module, a comparator module, a recoding module and a successive approximation logic module, wherein the DAC module comprises a main DAC capacitor array and an auxiliary DAC capacitor array, the main DAC capacitor array comprises a main quantization capacitor and a main C0 capacitor, the auxiliary DAC capacitor array adopts a differential structure for generating reference voltage, the auxiliary DAC capacitor array comprises an auxiliary capacitor and an auxiliary C0 capacitor, the comparator module comprises a comparator CMP1, a comparator CMP2 and two NOR gates, the comparator CMP1 is connected with the main DAC capacitor array, and the comparator CMP2 is connected with the main DAC capacitor array. The analog-to-digital conversion method has the advantages that the analog-to-digital conversion method plays an important role in improving the linearity of the ADC, reduces the power consumption and the area of the SAR ADC, ensures the stability of asynchronous time sequences, has higher linearity and lower power consumption, realizes the analog-to-digital conversion of high-speed data, and improves the accuracy of conversion.

Description

2B/cycle successive approximation analog-to-digital converter with double comparators

Technical Field

The utility model relates to a high-speed data converter, in particular to a 2b/cycle successive approximation analog-to-digital converter with double comparators.

Background

In the fields of digital signal processing and electronic measurement, analog-to-digital converters (ADCs) play a vital role, and Successive Approximation Register (SAR) ADCs are favored because of their simple structure and low power consumption. However, with the continuous increase of the data processing speed requirements of modern electronic systems, the limitation of the traditional SAR ADC on the conversion speed is gradually highlighted, and becomes a key factor for restricting the expansion of the application range. In this context, a 2b/cycle ADC has been developed that can determine two digital codes simultaneously in each quantization period, thereby significantly improving the conversion rate. For an N-bit ADC, after adopting a 2b/cycle technology, the whole quantization process can be completed only by N/2 cycles, which means that the conversion speed is doubled compared with that of the traditional SAR ADC. The 2b/CYCLE SAR ADC under the technical background not only maintains the advantages of low power consumption and high precision of the SAR ADC, but also greatly improves the conversion efficiency by reducing the required quantization period, so that the SAR ADC is more suitable for high-speed signal processing occasions.

2B/CYCLE SAR ADC require two DACs, one primary DAC for sampling and quantizing the input signal and the other auxiliary DAC for generating the three reference voltages required for the quantization comparison. Furthermore, at least three comparators are required to compare the three reference voltages with the residual signal generated by the main DAC. The output of these comparators is a thermometer code, which is then converted to a binary code to accomplish the two-bit per cycle quantization. However, mismatch between different comparators will affect the linearity of the overall ADC, and three comparators will increase the power consumption of the overall circuit.

Disclosure of Invention

The utility model aims to provide a 2b/cycle successive approximation analog-to-digital converter with a double comparator, which has higher linearity and lower power consumption.

In order to solve the technical problem, the 2b/cycle successive approximation analog-to-digital converter using the dual comparator of the new model comprises a DAC module, a comparator module, a recoding module and a successive approximation logic module, wherein the DAC module comprises a main DAC capacitor array and an auxiliary DAC capacitor array, the main DAC capacitor array comprises 2N-2 main quantized capacitors and a main C0 capacitor used for matching an input signal range and a quantized range, an upper polar plate of the main quantized capacitors is connected with an input signal, a lower polar plate of the main quantized capacitors is connected with a cut-off residual DAC signal, the auxiliary DAC capacitor array adopts a differential structure for generating a reference voltage, the auxiliary DAC capacitor array comprises 2N-2 auxiliary capacitors and an auxiliary C0 capacitor used for adjusting the magnitude of the reference voltage, an upper polar plate of the auxiliary DAC capacitor array is connected to the input reference voltage, the other side array of the auxiliary DAC capacitor array generates a reference DAC voltage required to be compared next, the comparator module comprises a comparator CMP1, a comparator CMP2 and two NOR gates, the comparator CMP1 is connected with the main DAC capacitor array and is used for comparing the residual signal on the main DAC capacitor array with a low reference voltage and the DAC capacitor array with the main DAC capacitor array and comparing the residual signal with the high voltage with the main DAC capacitor array.

The comparator CMP1 and the comparator CMP2 are four-input comparators, the four-input comparators are connected with a clock CLKC, a first stage of the four-input comparator adopts a four-input dynamic pre-amplifier, a second stage is an inverter, a third stage is a latch structure and can output 1 at the output ends of the comparator CMP1 and the comparator CMP2 when the clock CLKC is at a low level, and one end of the four-input comparator outputs a high level and the other end outputs a low level when the clock CLKC is at a high level.

The outputs of the comparator CMP1 and the comparator CMP2 are connected to the 1-bit TDC, and the difference between the differential input signal and the high reference voltage and the difference between the differential input signal and the low reference voltage can be judged according to the comparison time of the comparator CMP1 and the comparator CMP2, so that the 3-bit thermometer code is finally obtained.

The clock CLKC is composed of a two-input nand gate and a three-input nor gate and is capable of generating asynchronous clocks from the outputs CMPP2 and CMPN2 of the 1-bit TDC.

The successive approximation logic module is connected with the comparison module and can directly generate control signals for switching the main CDAC and the auxiliary DAC switch array according to the 3-bit thermometer code generated by the comparison module.

The successive approximation logic module is provided with two dynamic control logic units, and can be used for controlling the bottom polar plate of the capacitor array after the dynamic control logic units Outp and Outn are effective, wherein the P and N of one dynamic control logic unit are respectively connected with the output CMPP2 and CMPN2 of the 1-bit TDC, and the P and N of the other dynamic control logic unit are respectively connected with the output CMPN and CMPP3 of the two four-input comparators.

The recoding module is connected with the comparator CMP1 and the comparator CMP2 through the successive approximation logic module and can be used for recoding the 3-bit thermometer codes generated by the comparator CMP1, the comparator CMP2 and the 1-bit TDC to obtain corresponding binary digital codes.

The utility model has the advantages that:

The converter only uses two comparators to obtain a 3-bit thermometer code, compared with the traditional 2b/CYCLE SAR ADC, the reduction of the number of the comparators plays an important role in improving the linearity of the ADC, reduces the power consumption and the area of the SAR ADC on the premise of reducing one comparator, ensures the stability of asynchronous time sequence, has higher linearity and lower power consumption, can effectively realize the analog-to-digital conversion of high-speed data through a skillfully designed circuit structure, and improves the conversion accuracy under the condition of not increasing the complexity.

Drawings

FIG. 1 is a schematic diagram of a 2b/cycle successive approximation analog-to-digital converter of a dual comparator of the present utility model;

FIG. 2 is a schematic diagram of a primary CDAC array structure in accordance with the present utility model;

FIG. 3 is a schematic diagram of an auxiliary CDAC array structure in accordance with the present utility model;

FIG. 4 is a schematic diagram of a four-input comparator structure according to the present utility model;

FIG. 5 is a schematic diagram of a 1-bit TDC in accordance with the present utility model;

FIG. 6 is a diagram of an asynchronous clock logic circuit in accordance with the present utility model;

FIG. 7 is a schematic diagram of a successive approximation logic module according to the present utility model;

Fig. 8 is a circuit diagram of a recoding module in the present utility model.

Detailed Description

The 2b/cycle successive approximation analog-to-digital converter of the dual comparator of the present utility model is described in further detail below with reference to the accompanying drawings and detailed description.

As shown in the figure, the 2b/cycle successive approximation analog-to-digital converter of the dual comparator comprises a DAC module, a comparator module, a recoding module and a successive approximation logic module, wherein the DAC module comprises a main DAC capacitor array and an auxiliary DAC capacitor array, as shown in figure 2, the main DAC capacitor array comprises 2N-2 main quantization capacitors (numbered from high to low in weight as C1p, C2p, C3p, & gt, CN-1p and C1N, C2N, C3N, & gt, CN-1N, wherein N is the bit number of the analog-to-digital converter) and main C0 capacitors used for matching an input signal range and a quantization range, the upper polar plates of the main quantization capacitors are connected with the input signal through a gate voltage bootstrap switch, the lower polar plates of the main quantization capacitors are respectively connected with cut-off DAC signals, as shown in figure 3, the auxiliary DAC capacitor array (single-side capacitor array) adopts a differential structure for generating reference voltages, and the auxiliary DAC capacitor array comprises 2N-2 auxiliary capacitors (numbered from high to low in weight as C1p c2p, C3p, CN-1p and C1n, C2n, C3n, C1n, CN-1 n) and an auxiliary C0 capacitor for adjusting the magnitude of the reference voltage, the upper plate of the auxiliary DAC capacitor array is connected to the input reference voltage (reference voltage V _FS/2 of the first quantization period) through a switch, the other side of the auxiliary DAC capacitor array switches the switch array to generate the reference DAC voltage to be compared next, the sampling stage samples the input signal to the top plate of the CDAC (main DAC capacitor array) through a gate voltage bootstrap switch S1 and a gate voltage bootstrap switch S2, the bottom plate is connected to the high reference voltage and the low reference voltage through a switch, the auxiliary DAC (auxiliary DAC capacitor array) sampling stage samples the differential reference voltage V _FS/4 identical to the common mode voltage of the input signal to the top plate through a switch, and when the sampling stage is finished, the first comparison is directly performed without switching the bottom plate switches of the main DAC array and the auxiliary DAC array, the comparator module is formed by a comparator CMP1, The comparator CMP2 is connected with the main DAC capacitor array and is used for comparing the residual signal on the main DAC capacitor array with a low reference voltage (-V _F S/2), the comparator CMP2 is connected with the main DAC capacitor array and is used for comparing the residual signal on the main DAC capacitor array with a high reference voltage (V _FS/2), the 1-bit TDC is formed by the two NOR gates, and the two comparators and the 1-bit TDC can generate a 3-bit thermometer code.

Further, the comparator CMP1 and the comparator CMP2 are four-input comparators, the four-input comparators are connected with a clock CLKC, a first stage of the four-input comparator adopts a four-input dynamic pre-amplifier, a second stage is an inverter, a third stage is a latch structure and can reset the comparator CMP1 and the comparator CMP2 when the clock CLKC is in a low level so that the output ends of the comparator CMP1 and the comparator CMP2 output 1, when the clock CLKC is in a high level, the four-input comparator compares an input signal voltage (Vip-Vin) with a reference voltage, after the clock CLKC is amplified by the first stage pre-amplifier, the latch latches according to the input of the first two stages so that one end of the four-input comparator outputs a high level, and the other end outputs a low level,

When Vip-vin=vrefn-Vrefp, the conventional 2b/CYCLE SAR ADC is to use three comparators to compare the input signal on the top plate of the main DAC with +v _FS/2,0,-V_FS/2, and the two comparators of the comparator module of the present utility model compare the input signal on the top plate of the main DAC with +v _FS/2,-V_FS/2.

As shown in FIG. 5, the outputs of the comparator CMP1 and the comparator CMP2 are connected to the 1-bit TDC, because the larger the difference value between the differential input signal and the reference voltage is, the shorter the comparison time is, the magnitude of the difference value between the differential input signal and +V _FS/2 and the magnitude of the difference value between the differential input signal and the +V _FS/2 can be judged according to the comparison time of the comparator CMP1 and the comparator CMP2, the 3-bit thermometer code can be finally obtained, one comparator can be omitted, the power consumption of the integral SAR ADC is reduced, when the integral SAR ADC is reset, the outputs of the two comparators are both high level, and the outputs at the two ends of the 1-bit TDC are both 1.

In 2b/CYCLE SAR ADC, the differential input signal only needs to be compared with a high reference voltage (V _FS/2) and a low reference voltage (-V _FS/2) each comparison period, so that only one differential reference voltage V _FS/2 needs to be generated in the auxiliary DAC before each comparison. When the difference value between Vip-Vin and Vrefn-Vrefp is larger, the equivalent transconductance of the input pair tube of the comparator is larger, the comparison time is shorter, the outputs of the two comparators are connected to a 1-bit TDC consisting of two NOR gates, and a 3-bit thermometer code can be obtained; for example, when the input signal is in the [ V _FS/2,V_FS ] section, CMPN1 outputs 0, CMPP3 outputs 1,1 bit TDC with P end output high, thermometer code 111 can be obtained, when the input signal is in the [0, V _FS/2 ] section, two comparators output CMPP3 and CMPN1 low, but because of the larger difference between the differential input signal and-V _FS/2, CMPN1 will drop faster than CMPP3, two NOR gates will positive feedback, CMPP2 output high, CMPN2 output low, generating thermometer code 011, when the input signal is in the [ V _FS/2, 0] section, two comparators output CMPP3 and CMPN1 low, but because of the larger difference between the differential input signal and V _FS/2, CMPP3 will drop faster than CMPN, two NOR gates will feedback, PP2 output low, 25 output high, generating thermometer PP2 output high, and CMPP 1 output low, generating thermometer code can be obtained when CMPP3 and CMPP 1 output high, CMPP 1 at positive feedback, 96/2 output high, and CMPP2 output positive-low, and 96000 when the input signal is in the [ V _FS/2, and CMPP 1 ] high.

Still further, fig. 6 shows an asynchronous clock logic circuit, in which the clock CLKC is composed of a two-input nand gate and a three-input nor gate and can be generated by the outputs CMPP2 and CMPN2 of the 1-bit TDC, the conventional 2b/CYCLE SAR ADC uses three comparators, the comparison time of each of the different comparators is completely inconsistent, the stability of the asynchronous clock cannot be guaranteed, and the complexity of the circuit is increased, in the above circuit structure, the clock CLKC is generated by a simple logic gate after the comparison of the comparator CMP1 and the comparator CMP2 is completed, so that the CMPP2 and CMPN ensure that the asynchronous clock can be turned over after the thermometer code is completely established, the reset phases CMPP2 and CMPN2 are both high, the nand gate output is low, the Valid signal is high, one end of one bit outputs high, the other end outputs low, and the nand gate output is high, and the Valid signal is low. The three input nor gate inputs are connected to the sampling clock CLKS and the comparison completion flag signal RDY and the output signal of the nand gate, respectively, to generate an asynchronous clock CLKC signal of the comparator.

Still further, as shown in fig. 7, the successive approximation logic module is connected to the comparing module and is capable of directly generating the control signal for switching the main CDAC and the auxiliary DAC switch array according to the 3-bit thermometer code generated by the comparing module, without performing the operation of converting the thermometer code into the binary code, so as to achieve a faster quantization speed.

Still further, the SAR ADC realizes the successive approximation process under the control of the SAR logic, the SAR logic circuit directly utilizes the 3-bit thermometer code generated by the comparison module to generate the control signal switching capacitor array, latches the control signals, latches all the control signals when all the conversion is completed, converts the thermometer code into binary code and uniformly outputs the binary code. The power consumption of digital circuits based on conventional SAR control logic is still quite significant, and, in order to reduce the power consumption of digital circuits,

As shown in fig. 7, since two binary codes need to be converted for each comparison, two dynamic control logic units are needed for each comparison, so the successive approximation logic module has two dynamic control logic units, the input D is at low level in the sampling stage, the outputs P and N of the dynamic control logic units are reset and cleared, and the node Q is discharged to ground. When input D goes from low to high, CLKi is pulled down to ground. Since the two-bit digital code is quantized in each comparison period, after the dynamic control logic units Outp and Outn are valid, the output nodes P and N are used for controlling the bottom plates of the capacitor array, the P and N of one dynamic control logic unit are respectively connected with the outputs CMPP2 and CMPN2 of the one-bit TDC, and the P and N of the other dynamic control logic unit are respectively connected with the outputs CMPN and CMPP3 of the two four-input comparators. The Valid signal is generated by the output and the NOT operation of the one-bit TDC, and meanwhile, the falling edge of the Valid signal comes, and the output Q is pulled up to VDD, so that the conversion is finished. The P and N of the dynamic logic control unit control the switch switching of the bottom polar plate of the reference voltage DAC through AND operation, and the outputs P1-Pn and N1-NN of the dynamic logic control unit generate control signals through the combinational logic circuit to control the capacitor in the capacitor driving switch DAC array so as to complete the successive approximation process.

2B/CYCLE SAR ADC, a 3-bit thermometer code can be generated by two comparators and a 1-bit TDC, an input signal is sampled to a main CDAC top pole plate through a gate voltage bootstrap switch, a bottom pole plate switch array is not required to be switched after sampling is finished, a first conversion process is directly carried out, and the generated 3-bit thermometer code is directly used for controlling the switching of the switch array to prepare for the next conversion.

The successive approximation logic unit is controlled by the outputs CMPP2 and CMPN2 of the 1-bit TDC to control the bottom plate switch array control signals P2, N2, P4, N4 of the main CDAC, and the successive approximation logic unit is controlled by the outputs CMPP1 and CMPN3 of the two comparators to control the bottom plate switch array control signals P1, N1, P3, N3. of the main CDAC. Generating switch array control signals RP1, RP2, RP3 of a reference voltage DAC by P2/N2, P4/N4, P6/N6..

Still further, as shown in fig. 8, the recoding module is connected to the comparator CMP1 and the comparator CMP2 through a logic circuit, and is configured to recode the 3-bit thermometer codes generated by the two comparators and the 1-bit TDC to obtain corresponding binary codes, where the recoding module can generate binary codes according to Pi and Ni signals output by the dynamic control logic unit and uniformly latch the binary codes to obtain final binary codes, the first set of dynamic control logic units output P1, P2, N1 and N2, the P2 can obtain the second bit D2 in the two-bit binary codes, the P1 and N1 perform nor operation, and then the output result and the P2 perform exclusive or operation to obtain the first bit D1 in the two-bit binary codes, so as to complete encoding of a set of two-bit binary codes, similarly complete conversion of other binary codes, and uniformly latch the binary codes to obtain the final binary codes.

It should be understood that the above description is not intended to limit the utility model to the particular embodiments disclosed, but to limit the utility model to the particular embodiments disclosed, and that the utility model is not limited to the particular embodiments disclosed, but is intended to cover modifications, adaptations, additions and alternatives falling within the spirit and scope of the utility model.

Claims (7)

1. The 2b/cycle successive approximation analog-to-digital converter of the double comparator comprises a DAC module, a comparator module, a recoding module and a successive approximation logic module, and is characterized in that the DAC module comprises a main DAC capacitor array and an auxiliary DAC capacitor array, the main DAC capacitor array comprises 2N-2 main quantized capacitors and main C0 capacitors used for matching an input signal range and a quantized range, an upper polar plate of the main quantized capacitors is connected with an input signal, a lower polar plate of the main quantized capacitors is connected with a cut-off DAC signal, the auxiliary DAC capacitor array adopts a differential structure and is used for generating a reference voltage, the auxiliary DAC capacitor array is composed of 2N-2 auxiliary capacitors and an auxiliary C0 capacitor used for adjusting the magnitude of the reference voltage, an upper polar plate of the auxiliary DAC capacitor array is connected to the input reference voltage, the other side array of the auxiliary DAC capacitor array generates a reference DAC voltage required to be compared next, the comparator module is composed of a comparator CMP1, a comparator 2 and two NOR gates, the comparator CMP1 is connected with the main DAC capacitor array and is used for comparing the main residual capacitor array with the main DAC capacitor array with the reference voltage and the low DAC capacitor array and the main DAC capacitor array and is used for comparing the main DAC capacitor array with the high-residual voltage with the main DAC capacitor array and the main DAC array.

2. The two-comparator 2b/cycle successive approximation analog-to-digital converter of claim 1, wherein the comparator CMP1 and the comparator CMP2 are four-input comparators, the four-input comparators are connected with a clock CLKC, a first stage of the four-input comparators adopts a four-input dynamic pre-amplifier, a second stage is an inverter, a third stage is a latch structure and can output 1 at the output ends of the comparator CMP1 and the comparator CMP2 when the clock CLKC is at a low level, and one end of the four-input comparators outputs a high level and the other end outputs a low level when the clock CLKC is turned to a high level.

3. The 2b/cycle successive approximation analog-to-digital converter of claim 2, wherein the outputs of the comparator CMP1 and the comparator CMP2 are connected to the 1-bit TDC and are capable of determining the difference between the differential input signal and the high reference voltage and the low reference voltage according to the comparison time of the comparator CMP1 and the comparator CMP2, thereby obtaining the 3-bit thermometer code.

4. The 2b/cycle successive approximation analog-to-digital converter of claim 3, wherein said clock CLKC is comprised of a two-input NAND gate and a three-input NOR gate and is capable of generating asynchronous clocks from outputs CMPP2 and CMPN2 of a 1-bit TDC.

5. The 2b/cycle successive approximation analog-to-digital converter of claim 4, wherein the successive approximation logic module is coupled to the comparison module and is capable of directly generating control signals for switching the primary CDAC and the auxiliary DAC switch array based on the 3-bit thermometer code generated by the comparison module.

6. The 2b/cycle successive approximation analog-to-digital converter of claim 5, wherein said successive approximation logic block has two dynamic control logic units, and is capable of controlling the bottom plates of the capacitor array after said dynamic control logic units Outp and Outn are enabled, wherein P and N of one dynamic control logic unit are respectively connected to the outputs CMPP2 and CMPN2 of the 1-bit TDC, and P and N of the other dynamic control logic unit are respectively connected to the outputs CMPN1 and CMPP3 of the two four-input comparators.

7. The 2b/cycle successive approximation analog-to-digital converter of claim 6, wherein the recoding module is coupled to the comparator CMP1 and the comparator CMP2 via successive approximation logic and is operable to recode the 3-bit thermometer codes generated by the comparator CMP1, the comparator CMP2 and the 1-bit TDC to obtain the corresponding binary digital codes.