CN223194398U - A motor control device - Google Patents

Abstract

The present application discloses a motor control device, including a logic envelope circuit, a processor, a chip monitoring circuit, an overcurrent monitoring circuit, an overvoltage monitoring circuit and a drive circuit; the pulse signal output end of the processor is connected to the logic envelope circuit; the processor outputs a pulse signal to the logic envelope circuit; the active short circuit ASC command port of the processor is connected to the command input port of the logic envelope circuit; the chip monitoring circuit is connected to the processor, and when a fault occurs in the monitoring processor, a fault signal is sent to the chip monitoring port of the logic envelope circuit; the output ends of the overcurrent monitoring circuit and the overvoltage monitoring circuit are both connected to the electrical parameter monitoring port of the logic envelope circuit; the output end of the logic envelope circuit is connected to the switch tube of the drive circuit, and the signal detection end of the drive circuit is connected to the drive chip detection input end of the logic envelope circuit; the logic envelope circuit outputs a pulse signal or a blocked pulse signal to the drive circuit, and the solution responds to the hardware, improves the speed and ensures safety.

Description

Motor control equipment

Technical Field

The application relates to the technical field of motor control, in particular to motor control equipment.

Background

The new energy automobile is driven by a motor. The operation of the motor is controlled by motor control equipment commonly known as a motor controller. The motor control apparatus includes a processor and a driving circuit. Specifically, the processor controls a switching tube of a driving circuit, and the driving circuit is used for converting energy of a power battery into alternating current to drive a motor to operate. The actual operation condition of the motor control device is complex, for example, various fault signals are sent to the processor, the processor outputs PWM signals according to different fault types, the PWM signals enter an active short circuit (Active Short Circuit, ASC) state, a control state or a wave-sealing state (6 power tubes of an upper bridge arm and a lower bridge arm are all switched off), the response delay problem exists, the safe state (ASC or wave-sealing) cannot be quickly entered, and when the processor fails or software operation is wrong, the safe state cannot be entered through software control, so that the safe operation of the motor control device cannot be ensured.

Disclosure of utility model

In view of the above, the present application provides a motor control apparatus capable of responding through a hardware circuit when a fault occurs, thereby improving the response speed and ensuring the safety of the motor control apparatus.

The application provides motor control equipment which comprises a logic wave sealing circuit, a processor, a chip monitoring circuit, an overcurrent monitoring circuit, an overvoltage monitoring circuit and a driving circuit, wherein a pulse signal output end of the processor is connected with the logic wave sealing circuit, the processor is used for outputting pulse signals to the logic wave sealing circuit, an active short circuit ASC command port of the processor is connected with a command input port of the logic wave sealing circuit, the chip monitoring circuit is connected with the processor and is used for monitoring the chip monitoring port of the logic wave sealing circuit when the processor fails, an output end of the overcurrent monitoring circuit and an output end of the overvoltage monitoring circuit are both connected with an electric parameter monitoring port of the logic wave sealing circuit, an output end of the logic wave sealing circuit is connected with a switching tube in the driving circuit, a signal detection end of the driving circuit is connected with a driving chip detection input end of the logic wave sealing circuit, and the logic wave sealing circuit is used for outputting the pulse signals to the driving circuit or blocking the pulse signals to the driving circuit.

The logic wave sealing circuit comprises a shutdown logic circuit, an active short-circuit ASC logic circuit, a shutdown path circuit and an active short-circuit ASC path circuit, wherein the input end of the shutdown logic circuit is connected with the output end of the chip monitoring circuit, the output end of the overcurrent monitoring circuit, the output end of the overvoltage monitoring circuit, the active short-circuit ASC command port of the processor and the signal detection end of the driving circuit, the input end of the active short-circuit ASC logic circuit is connected with the output end of the overvoltage monitoring circuit and the signal detection end of the driving circuit, the first input end of the shutdown path circuit is connected with the output end of the shutdown logic circuit, the second input end of the shutdown path circuit is connected with the pulse signal output end of the processor, and the first input end of the active short-circuit ASC path circuit is connected with the output end of the active short-circuit ASC logic circuit.

The shutdown logic circuit is configured to output a shutdown signal to a first input terminal of the shutdown path circuit according to a fault signal of the chip monitoring circuit, a signal of an output terminal of the overcurrent monitoring circuit, a signal of an output terminal of the overvoltage monitoring circuit, a signal of the active short-circuit ASC command port of the processor and a signal of a signal detection terminal of the driving circuit, and the active short-circuit ASC logic circuit is configured to output a short-circuit signal to the first input terminal of the active short-circuit ASC path circuit according to the signal of the output terminal of the overvoltage monitoring circuit and the signal of the signal detection terminal of the driving circuit.

The possible implementation mode of the shutdown path circuit comprises an upper bridge shutdown path circuit and a lower bridge shutdown path circuit, wherein a first input end of the upper bridge shutdown path circuit is connected with an upper bridge output end of the shutdown logic circuit, a second input end of the upper bridge shutdown path circuit is connected with an upper bridge pulse signal output end of the processor, a first input end of the lower bridge shutdown path circuit is connected with a lower bridge output end of the shutdown logic circuit, and a second input end of the lower bridge shutdown path circuit is connected with a lower bridge pulse signal output end of the processor.

A possible implementation manner of the active short-circuit ASC path circuit comprises an upper bridge active short-circuit ASC path circuit and a lower bridge active short-circuit ASC path circuit, wherein a first input end of the upper bridge active short-circuit ASC path circuit is connected with an upper bridge output end of the active short-circuit ASC logic circuit, a second input end of the upper bridge active short-circuit ASC path circuit is connected with an upper bridge output end of the turn-off path circuit, a first input end of the lower bridge active short-circuit ASC path circuit is connected with a lower bridge output end of the active short-circuit ASC logic circuit, and a second input end of the lower bridge active short-circuit ASC path circuit is connected with a lower bridge output end of the turn-off path circuit.

In one possible implementation manner, the turn-off logic circuit is configured to control the turn-off path circuit to block the pulse signal when the signal detection end of the driving circuit outputs a low level.

In one possible implementation manner, the active short-circuit ASC logic circuit is configured to control the lower bridge active short-circuit ASC path circuit of the active short-circuit ASC path circuit to actively short when the signal detection end of the driving circuit outputs a high level and the output end of the overvoltage detection circuit outputs a low level.

In one possible implementation manner, the turn-off logic circuit is configured to control the turn-off path circuit to block the pulse signal when the signal detection terminal of the driving circuit outputs a high level and the output terminal of the overcurrent detection circuit outputs a low level.

The active short circuit ASC logic circuit is used for outputting a high level at a signal detection end of the driving circuit, outputting a high level at an output end of the overvoltage detection circuit, outputting a high level at an output end of the overcurrent detection circuit, outputting a high level at a chip monitoring circuit, controlling an upper bridge active short circuit ASC path circuit to short circuit an upper bridge arm switch tube of the driving circuit when an upper bridge active short circuit ASC command low level is output at an active short circuit ASC command port of the processor, controlling a lower bridge active short circuit ASC path circuit to short circuit a lower bridge arm switch tube of the driving circuit when a lower bridge active short circuit ASC command low level is output at an active short circuit ASC command port of the processor, and controlling the lower bridge active short circuit path circuit to short circuit the lower bridge arm switch tube of the driving circuit when the signal detection end of the driving circuit outputs a high level, outputting a high level at an output end of the overvoltage detection circuit, outputting a high level at an output end of the overcurrent detection circuit, outputting a high level at an output end of the chip monitoring circuit.

A possible implementation mode is that the logic wave sealing circuit is further connected with a software enabling end of the processor, the logic wave sealing circuit is enabled to conduct active short circuit when the software enabling end outputs high level, and the logic wave sealing circuit is enabled to conduct wave sealing when the software enabling end outputs low level.

The motor control device provided by the embodiment of the application comprises a logic wave sealing circuit, wherein the logic wave sealing circuit comprises logic gates, logic operation can be carried out on signals of all monitoring circuits, wave sealing can be realized in time when faults occur, namely pulse signals output by a processor are blocked, and the pulse signals cannot drive a switching tube to act, so that the safety of a driving circuit is realized.

Drawings

Fig. 1 is a schematic diagram of a motor control apparatus according to an embodiment of the present application;

fig. 2 is a schematic diagram of still another motor control apparatus according to an embodiment of the present application;

fig. 3 is a schematic view of still another motor control apparatus according to an embodiment of the present application;

fig. 4 is a schematic diagram of another motor control apparatus according to an embodiment of the present application.

Detailed Description

In order that the above-recited objects, features and advantages of the present application will become more readily apparent, a more particular description of embodiments of the application will be rendered by reference to the appended drawings and appended drawings.

Referring to fig. 1, a schematic diagram of a motor control apparatus according to an embodiment of the present application is shown.

The motor control device provided by the embodiment of the application comprises a logic wave sealing circuit 100, a processor 200, a chip monitoring circuit 300, a driving circuit 400, an overcurrent monitoring circuit 500 and an overvoltage monitoring circuit 600.

Embodiments of the present application are not particularly limited to the implementation of the processor 200, and may be, for example, a single-chip microcomputer or a microprocessor.

The pulse signal output end of the processor 200 is connected with the logic wave sealing circuit 100, the processor 200 is used for outputting pulse signals to the logic wave sealing circuit 100, and the active short circuit ASC command port of the processor 200 is connected with the command input port of the logic wave sealing circuit 100. ASC is an abbreviation for active short circuit, and is hereinafter referred to simply as description for convenience of description.

The driving circuit 400 is generally a three-phase driving circuit, and the corresponding bridge arm circuit is a full-bridge inverter circuit, each phase of bridge arm includes an upper bridge arm and a lower bridge arm, and the three-phase bridge arm includes at least six switching tubes. The pulse signals corresponding to the six switching tubes are taken as PWM signals for example for description.

In fig. 1, the processor 200 outputs pulse signals corresponding to six switching transistors, i.e., PWM signals corresponding to a U-phase upper bridge, a V-phase upper bridge, a W-phase upper bridge, a U-phase lower bridge, a V-phase lower bridge, and a W-phase lower bridge of the three-phase bridge arm, respectively. It should be understood that the six pulse signals output by the processor 200 are not necessarily output to the driving circuit 400, and the logic wave sealing circuit 100 is required to perform logic operation according to each monitoring signal to determine whether to output the pulse signals sent by the processor 200 to the driving circuit 400, and when the monitoring signal determines that wave sealing is required, the logic wave sealing circuit 100 blocks the pulse signals, so that the driving circuit 400 does not work, and the safety of the motor control device can be effectively protected.

The pulse signals output by the logic wave sealing circuit 100 include pwmh_ U, PWMH _ V, PWMH _ W, PWML _ U, PWML _ V, PWML _w, which correspond to the driving signals of the switching transistors of the U-phase upper bridge, the V-phase upper bridge, the W-phase upper bridge, the U-phase lower bridge, the V-phase lower bridge, and the W-phase lower bridge of the driving circuit 400, respectively.

The chip monitoring circuit 300 is used for monitoring the monolithic work, and when the software runs out or other problems, the chip monitoring circuit 300 outputs a fault signal Micro fault. For example, the micro_failure low level indicates a failure, the micro_failure high level indicates a normal, and the chip monitor circuit 300 may be implemented using a watchdog circuit or chip.

The overcurrent monitoring circuit 500 is configured to monitor whether the three-phase current output from the motor control device is overcurrent, and output hv_oc when the three-phase current is overcurrent, where a low level indicates overcurrent and a high level indicates normal. The meaning of the high and low levels above is merely illustrative. It should be appreciated that the motor control device outputs three-phase currents to the motor.

The overvoltage monitoring circuit 600 is configured to monitor whether the bus voltage of the motor control device is overvoltage, and output hv_ov when overvoltage occurs, for example, hv_ov low level indicates overvoltage and hv_ov high level indicates normal. The meaning of the high and low levels above is merely illustrative.

The embodiments of the present application are not particularly limited to the specific implementation of the over-current monitoring circuit 500 and the over-voltage monitoring circuit 600, and it should be understood that the chip monitoring circuit 300, the over-current monitoring circuit 500 and the over-voltage monitoring circuit 600 are all in the prior art, and are not particularly limited herein.

The driving circuit 400 includes a driving chip in addition to the bridge arm circuit. The driving circuit 400 outputs a monitor signal of the driving chip, and hw_gflt_h and hw_gflt_l represent an upper bridge fault signal and a lower bridge fault signal of the driving chip, respectively, for example, a low level represents a fault and a high level represents a normal. Hw_gflt_h and hw_gflt_l are input signals to logic envelope circuit 100.

The active short-circuited ASC command ports sw_cmdh and sw_ CMDL of the processor 200 are command signals output from the processor 200, respectively, and are input to the command input port of the logic seal circuit 100. The SW_CMDH and the SW_ CMDL realize the functions of software encapsulation, upper bridge ASC or lower bridge ASC. For example, sw_ CMDH and sw_ CMDL are both low, and pulse signals are normally output. Sw_ CMDH and sw_ CMDL are both high to realize the seal. Sw_ CMDH is high and sw_ CMDL is low, the upper bridge ASC is implemented. Sw_ CMDH is low and sw_ CMDL is high, the lower bridge ASC is implemented.

The chip monitoring circuit 300 is connected to the processor 200, and the chip monitoring circuit 300 is configured to send a fault signal to the chip monitoring port of the logic wave sealing circuit 100 when the processor 200 fails.

The output end of the overcurrent monitoring circuit 500 and the output end of the overvoltage monitoring circuit 600 are both connected with the electrical parameter monitoring port of the logic wave sealing circuit 100, the output end of the logic wave sealing circuit 100 is connected with a switching tube in the driving circuit 400, and the signal detection end of the driving circuit 400 is connected with the detection input end of a driving chip of the logic wave sealing circuit 100.

The logic wave sealing circuit 100 is used for outputting a pulse signal to the driving circuit 400 or blocking the pulse signal to the driving circuit 400.

The logic wave sealing circuit 100 provided in the embodiment of the present application may be implemented by using logic gates, for example, but not limited to, a combination of an and gate, an not gate, an or gate, etc., and may further include passive devices, for example, including a resistor, a capacitor, etc., where the resistor may implement current limiting, and the combination of the resistor and the capacitor may implement delay, etc. When the lower bridge ASC is needed to be executed, the three switching tubes of the upper bridge are closed first, a period of time is delayed, and then the lower bridge ASC is entered, so that the phenomenon that the logic wave sealing circuit outputs an upper bridge driving signal and a lower bridge driving signal simultaneously at a high level is avoided. When the bridge ASC is on, the principle is the same as above, and the description is not repeated here.

The motor control device provided by the embodiment of the application comprises a logic wave sealing circuit, wherein the logic wave sealing circuit comprises logic gates, logic operation can be carried out on signals of all monitoring circuits, wave sealing can be realized in time when faults occur, namely pulse signals output by a processor are blocked, and the pulse signals cannot drive a switching tube to act, so that the safety of a driving circuit is realized. Because the logic wave-sealing circuit provided by the embodiment of the application is realized by the hardware logic gate circuit, compared with software control, the logic wave-sealing circuit has higher response speed and can protect in time when faults occur.

Referring to fig. 2, a schematic diagram of still another motor control apparatus according to an embodiment of the present application is shown.

The motor control device provided by the embodiment of the application is characterized in that the logic wave sealing circuit 100 is also connected with a software enabling end of the processor 200, and the software enabling end outputs enabling signals SW_GFLT_ASC_EN, and SW_GFLT_ASC_EN are switching signals for realizing whether wave sealing or active short circuit is realized.

For example, when sw_gflt_asc_en is high, the logic seal circuit 100 is enabled to perform active short-circuiting, and when sw_gflt_asc_en is low, the logic seal circuit 100 is enabled to perform seal.

The internal architecture of the logic envelope circuit is described in detail below with reference to the accompanying drawings.

Referring to fig. 3, a schematic diagram of still another motor control apparatus according to an embodiment of the present application is shown.

If the motor control device provided by the embodiment of the application does not distinguish the driving of the upper bridge arm and the lower bridge arm, the logic wave sealing circuit comprises a turn-off logic circuit 10, an active short circuit ASC logic circuit 20, a turn-off path circuit and an active short circuit ASC path circuit.

The input end of the turn-off logic circuit 10 is connected with the output end of the chip monitoring circuit, the output end of the overcurrent monitoring circuit, the output end of the overvoltage monitoring circuit, the ASC command port of the processor and the signal detection end of the driving circuit. I.e., the input signals of the shutdown logic 10 include micro_fault, hw_gflt_ H, HW _gflt_ L, HV _oc, and hv_ov.

An input terminal of the ASC logic circuit 20 is connected to an output terminal of the overvoltage monitor circuit and a signal detection terminal of the driving circuit. I.e., the input signal to ASC logic circuit 20 includes hw_gflt_ H, HW _gflt_l and hv_ov.

The first input end of the shutdown path circuit is connected with the output end of the shutdown logic circuit 10, and the second input end of the shutdown path circuit 10 is connected with the pulse signal output end of the processor.

The first input of the ASC path circuit is connected to the output of the ASC logic circuit 20 and the second input of the ASC path circuit is connected to the output of the shutdown path circuit.

And the turn-off logic circuit is used for outputting a turn-off signal to the first input end of the turn-off path circuit according to the fault signal of the chip monitoring circuit, the signal of the output end of the overcurrent monitoring circuit, the signal of the output end of the overvoltage monitoring circuit, the signal of the ASC command port of the processor and the signal of the signal detection end of the driving circuit.

And the ASC logic circuit is used for outputting a short-circuit signal to the first input end of the ASC path circuit according to the signal of the output end of the overvoltage monitoring circuit and the signal of the signal detection end of the driving circuit.

With continued reference to fig. 3, the off-path circuit includes an upper bridge off-path circuit 31 and a lower bridge off-path circuit 32.

The first input end of the upper bridge shutdown path circuit 31 is connected with the upper bridge output end of the shutdown logic circuit, and the second input end of the upper bridge shutdown path circuit 31 is connected with the upper bridge pulse signal output end of the processor.

A first input terminal of the lower bridge shutdown path circuit 32 is connected to a lower bridge output terminal of the shutdown logic circuit 10, and a second input terminal of the lower bridge shutdown path circuit 32 is connected to a lower bridge pulse signal output terminal of the processor.

The signal states of the outputs SHUTOFF _h and SHUTOFF _l of the shutdown logic 10 are jointly determined from the states of the inputs sw_cmd_ H, SW _cmd_ L, micro _failure, hw_oc, hw_ov, hw_gflt_ H, HW _gflt_l. Wherein SHUTOFF _h is input to the first input of the upper bridge shutdown path circuit 31 and SHUTOFF _l is input to the first input of the lower bridge shutdown path circuit 32.

The ASC path circuit includes an upper bridge ASC path circuit 41 and a lower bridge ASC path circuit 42.

The first input of the upper bridge ASC path circuit 41 is connected to the upper bridge output asc_h of the ASC logic circuit 20 and the second input of the upper bridge ASC path circuit 41 is connected to the upper bridge output of the off path circuit, i.e. to the output of the upper bridge off path circuit 31.

A first input of the lower bridge ASC path circuit 42 is connected to a lower bridge output asc_l of the ASC logic circuit 20, and a second input of the lower bridge ASC path circuit 42 is connected to a lower bridge output of the off path circuit, i.e. to an output of the lower bridge off path circuit 32.

In addition, the logic wave sealing circuit provided by the embodiment of the application can also receive the enabling signal from the processor, and particularly refer to fig. 4, which is a schematic diagram of another motor control device provided by the embodiment of the application.

In the motor control device provided by the embodiment of the application, the enable signal sw_gflt_asc_en output by the processor is connected to the input end of the ASC logic circuit 20.

The turn-off logic circuit 10 is used for controlling the turn-off path circuit to block the pulse signal when the signal detection end of the driving circuit outputs a low level.

The ASC logic circuit 20 is configured to control the active short circuit of the lower bridge ASC path circuit of the ASC path circuit when the signal detection terminal of the driving circuit outputs a high level and the output terminal of the overvoltage detection circuit outputs a low level.

The turn-off logic circuit 10 is configured to control the turn-off path circuit to block the output of the pulse signal when the signal detection terminal of the driving circuit outputs a high level and the output terminal of the overcurrent detection circuit outputs a low level.

The following specific working principle is performed by combining the truth tables of the logic circuits in the logic seal circuit.

TABLE 1

In table 1, the low level of each signal is represented by 0, and the high level is represented by 1. X represents 1 and 0.

Feng Bo denotes that the processor or the 6 power tubes of the three-phase bridge arm are all closed;

The upper bridge ASC represents that three power tubes of the three-phase upper bridge arm of the processor are opened, and three power tubes of the lower bridge arm are closed.

The lower bridge ASC represents that three power tubes of the three-phase upper bridge arm of the processor are closed, and the three power tubes of the lower bridge arm are opened.

PWM means that the pulse signal output by the logic wave sealing circuit follows the pulse signal output by the processor, namely the normal working state of the processor.

With continued reference to FIG. 4, specific operating logic is described in conjunction with FIG. 4 and the truth table.

The software upper and lower bridge ASC path receives the SW_CMD_L/H signal as a high level to enter the ASC, and the low level outputs a PWM signal which follows the PWM signal sent by the processor;

The logic wave-sealing circuit provided by the embodiment of the application also comprises a software ASC path, and the software ASC path is realized by the logic gate circuit. The software ASC path in turn includes a software upper bridge ASC path and a software lower bridge ASC path. It should be understood that the input ends of the software upper bridge ASC path and the software lower bridge ASC path are respectively connected with the upper bridge arm pulse signal and the lower bridge arm pulse signal output by the processor. The upper bridge off path and the lower bridge off path receive off control signals SHUTOFF _h and SHUTOFF _l respectively, the off paths are turned off when the low level is reached, the output PWM signals are all low level, the output PWM signals are turned on when the high level is reached, and the output PWM signals follow the PWM signals of the ASC path of the preceding-stage software.

The output PWM signal is in ASC state when ASC_H/L signal is high level, the receiving signal output PWM signal is following the front stage turn-off path to output PWM signal when low level, the state of the turn-off logic circuit 10 output SHUTOFF _H/L, micro _failure is determined according to the inputs SW_CMD_H/L, micro _failure, HW_OC, HW_OV, HW_GFLT_H/L, SW _GFLT_ASC_EN.

The state of the ASC logic circuit 20 output ASC H/L signal depends on the state of the inputs HW OC, HW OV, HW GFLT H/L, SW GFLT ASC EN and the final output PWM signal state of the logic envelope circuit corresponds to the truth table logic of table 1.

The motor control device provided by the embodiment of the application carries out level division on each fault signal, and the fault signals with high priority are directly subjected to wave sealing or ASC without monitoring the states of other signals.

Primary fault signal: HW_GFLT_ L, HW gflt_h.

Regardless of the states of the HV_OV, HV_OC, micro_failure, SW_CMDH and SW_ CMDL signals, when an upper bridge fault and a lower bridge fault occur to a driving chip in a driving circuit at the same time, an enabling output SHUTOFF _H/L of a shutdown logic circuit in a logic wave-sealing circuit is low level, an upper/lower bridge shutdown path circuit is controlled to output PWM signals to be low level, an ASC logic circuit is not enabled, the logic wave-sealing circuit enters a wave-sealing state, and upper and lower bridge power tubes of an inverter are all closed. When a lower bridge fault or an upper bridge fault occurs, the shutdown logic circuit enables the upper bridge shutdown path circuit and the lower bridge shutdown path circuit to output PWM signals as low level signals, and when the SW_GFLT_ASC_EN signal is enabled (high level), the ASC logic circuit enables the output ASC_H or ASC_L to be high level, controls the upper bridge ASC path circuit and the lower bridge ASC path circuit to work, and enters an upper bridge ASC or a lower bridge ASC, and the SW_GFLT_EN signal is not enabled (low level) and enters a wave sealing state.

And a secondary fault signal, namely HV_OV.

When no driving chip fault signal is generated, no matter the states of HV_OC, micro_fault, SW_CMDH and SW_ CMDL signals, and overvoltage occurs, the switching-off logic circuit outputs an upper bridge PWM signal as a low level signal, the ASC control circuit outputs ASC_L as a high level, and the ASC path circuit is controlled to enter a lower bridge ASC, namely the logic wave sealing circuit enters the lower bridge ASC.

And a three-stage fault signal, namely HV_OC.

When no driving chip and overvoltage fault signals exist, no matter the states of micro_fault, SW_CMDH and SW_ CMDL signals, and overcurrent occurs, the off path circuit receives SHUTOFF _H/L as a low level, the output PWM signals are low level, the ASC logic circuit outputs ASC_H/L as low level, and the logic wave sealing circuit enters a wave sealing state.

And a four-stage fault signal, namely micro_fault.

No driving chip fault signal, overvoltage fault signal and overcurrent fault signal, no matter the state of the software output SW_CMDH and SW_ CMDL signals, when Micro fault occurs, the off path circuit receives SHUTOFF _H/L as low level, the output PWM signal as low level, the ASC logic circuit outputs ASC_H/L as low level, and the logic wave sealing circuit enters into wave sealing state.

Five-stage control signals SW_CMDL and SW_ CMDH.

When the processor outputs SW_CMDL and SW_ CMDH which are low-level signals, the software ASC path is not enabled, the output PWM signal follows the PWM signal output by the processor, the off path circuit and the ASC path circuit are not enabled, the logic wave sealing circuit is in a PWM state, and the logic wave sealing circuit outputs the PWM signal output by the PWM signal following processor. When the sw_ CMDL output by the processor is low level and the sw_ CMDH is high level, the software upper bridge ASC path outputs are all high level, the software upper bridge ASC enters, the shut-down logic circuit outputs SHUTOFF _h/L are respectively high/low level, the lower bridge shut-down path circuit outputs are all low level, and the upper bridge shut-down path circuit outputs PWM signals which follow the PWM signals output by the upper bridge ASC path of the front-stage software to be high level. The ASC_H/L signals are low in level without change, the ASC path circuit outputs PWM signals which follow the PWM signals output by the front-stage turn-off path circuit, and the logic wave sealing circuit enters an upper bridge ASC state. Similarly, when sw_ CMDL is high and sw_ CMDH is low, the lower bridge ASC is entered, and when sw_ CMDL and sw_ CMDH are both high, the wave-blocking state is entered.

Through the description of the truth table and the working principle, it can be known that the motor control device provided by the embodiment of the application can perform different responses by the logic wave-sealing circuit when different fault types exist, so that the comprehensive protection of the driving circuit is realized.

It should be noted that, in the present description, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different manner from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. The motor control equipment is characterized by comprising a logic wave sealing circuit, a processor, a chip monitoring circuit, an overcurrent monitoring circuit, an overvoltage monitoring circuit and a driving circuit;

The pulse signal output end of the processor is connected with the logic wave sealing circuit, the processor is used for outputting pulse signals to the logic wave sealing circuit, and the active short circuit ASC command port of the processor is connected with the command input port of the logic wave sealing circuit;

the chip monitoring circuit is connected with the processor and is used for sending a fault signal to a chip monitoring port of the logic wave sealing circuit when the processor is monitored to be faulty;

The output end of the logic wave sealing circuit is connected with a switching tube in the driving circuit, and the signal detection end of the driving circuit is connected with the detection input end of a driving chip of the logic wave sealing circuit;

The logic wave sealing circuit is used for outputting the pulse signal to the driving circuit or blocking the pulse signal to the driving circuit.

2. The apparatus of claim 1, wherein the logic seal circuit comprises a shutdown logic circuit, an active short ASC logic circuit, a shutdown path circuit, and an active short ASC path circuit;

The input end of the turn-off logic circuit is connected with the chip monitoring circuit, the output end of the overcurrent monitoring circuit, the output end of the overvoltage monitoring circuit, the active short circuit ASC command port of the processor and the signal detection end of the driving circuit;

The input end of the active short circuit ASC logic circuit is connected with the output end of the overvoltage monitoring circuit and the signal detection end of the driving circuit;

The first input end of the turn-off path circuit is connected with the output end of the turn-off logic circuit, and the second input end of the turn-off path circuit is connected with the pulse signal output end of the processor;

And a first input end of the active short circuit ASC path circuit is connected with an output end of the active short circuit ASC logic circuit, and a second input end of the active short circuit ASC path circuit is connected with an output end of the turn-off path circuit.

3. The apparatus of claim 2, wherein the shutdown logic is configured to output a shutdown signal to the first input of the shutdown path circuit based on a fault signal of the chip monitor circuit, a signal of an output of the over-current monitor circuit, a signal of an output of the over-voltage monitor circuit, a signal of the active short circuit ASC command port of the processor, and a signal of a signal detection terminal of the drive circuit;

And the active short circuit ASC logic circuit is used for outputting a short circuit signal to the first input end of the active short circuit ASC path circuit according to the signal of the output end of the overvoltage monitoring circuit and the signal of the signal detection end of the driving circuit.

4. The apparatus of claim 2 or 3, wherein the off-path circuit comprises an upper bridge off-path circuit and a lower bridge off-path circuit;

The first input end of the upper bridge cut-off path circuit is connected with the upper bridge output end of the cut-off logic circuit, and the second input end of the upper bridge cut-off path circuit is connected with the upper bridge pulse signal output end of the processor;

the first input end of the lower bridge cut-off path circuit is connected with the lower bridge output end of the cut-off logic circuit, and the second input end of the lower bridge cut-off path circuit is connected with the lower bridge pulse signal output end of the processor.

5. The apparatus of claim 2 or 3 wherein the active shorting ASC path circuit comprises an upper bridge active shorting ASC path circuit and a lower bridge active shorting ASC path circuit;

The first input end of the upper bridge active short circuit ASC path circuit is connected with the upper bridge output end of the active short circuit ASC logic circuit, and the second input end of the upper bridge active short circuit ASC path circuit is connected with the upper bridge output end of the turn-off path circuit;

The first input end of the lower bridge active short circuit ASC path circuit is connected with the lower bridge output end of the active short circuit ASC logic circuit, and the second input end of the lower bridge active short circuit ASC path circuit is connected with the lower bridge output end of the turn-off path circuit.

6. A device as claimed in claim 3, wherein the shutdown logic is arranged to control the shutdown path circuit to block the pulse signal when the signal detection terminal of the drive circuit outputs a low level.

7. The apparatus of claim 5, wherein the active short ASC logic circuit is configured to control a lower bridge of the active short ASC path circuit to actively short when a signal detection terminal of the driving circuit outputs a high level and an output terminal of the overvoltage monitoring circuit outputs a low level.

8. The apparatus of claim 3, wherein the shutdown logic is configured to control the shutdown path circuit to block the pulse signal when the signal detection terminal of the drive circuit outputs a high level and the output terminal of the over-current monitor circuit outputs a low level.

9. The apparatus of claim 5, wherein the active short ASC logic circuit is configured to output a high level at a signal detection end of the driving circuit, an output end of the overvoltage monitoring circuit outputs a high level, an output end of the overcurrent monitoring circuit outputs a high level, the chip monitoring circuit outputs a high level, and when the active short ASC command port of the processor outputs an upper bridge active short ASC command low level, control the upper bridge active short ASC path circuit to short an upper bridge arm switching tube of the driving circuit;

The active short circuit ASC logic circuit is used for outputting a high level at a signal detection end of the driving circuit, outputting a high level at an output end of the overvoltage monitoring circuit, outputting a high level at an output end of the overcurrent monitoring circuit, outputting a high level by the chip monitoring circuit, and controlling the lower bridge active short circuit ASC path circuit to short-circuit a lower bridge arm switch tube of the driving circuit when an active short circuit ASC command port of the processor outputs a lower bridge active short circuit ASC command low level.

10. The device of claim 1, wherein the logic sealing circuit is further connected to a software enabling end of the processor, wherein the software enabling end enables the logic sealing circuit to perform active short circuit when outputting a high level, and enables the logic sealing circuit to perform sealing when outputting a low level.