CN223428829U - Solar cell and photovoltaic module - Google Patents

Abstract

The utility model provides a solar cell and a photovoltaic module, belonging to the field of photovoltaics. The solar cell includes a silicon substrate, the back side of which is provided with a discontinuously distributed tunneling oxide layer, which is divided into a plurality of P regions and a plurality of N regions arranged alternately at intervals; the P region includes a p+ doped polycrystalline silicon carbide layer and a p+ doped polycrystalline silicon layer in a direction away from the tunneling oxide layer; the N region is provided with an n+ doped polycrystalline silicon carbide layer; a back passivation layer and a back anti-reflection layer are stacked on the outer surface of the p+ doped polycrystalline silicon layer, the spacing region between the P region and the N region, and the outer surface of the n+ doped polycrystalline silicon carbide layer in a direction away from the silicon substrate; a first back metal electrode is provided on the P region, one end of the first back metal electrode forms an ohmic contact with the p+ doped polycrystalline silicon layer; and a second back metal electrode is provided on the N region, one end of the second back metal electrode forms an ohmic contact with the n+ doped polycrystalline silicon carbide layer.

Description

Solar cell and photovoltaic module

Technical Field

The utility model belongs to the technical field of production and manufacturing of photovoltaic modules, and particularly relates to a solar cell and a photovoltaic module.

Background

The PERC battery (emitter and back passivation battery) technology is a mainstream battery technology in the current market, the efficiency level of the PERC battery produced in mass at present can reach 23.5%, but the difficulty of improving the battery efficiency to more than 24% is high. The IBC battery (cross back contact battery) has no shading on the front surface, so that the battery efficiency can be easily over 24.5 percent, and if a passivation contact structure is overlapped, the efficiency can be over 26 percent, but the preparation process of the IBC battery is complex at present, and the IBC battery is not produced in large scale by the main flow route at present. The next generation of cell technology for PERC is currently widely recognized as either N-type TOPCon cells (tunnel oxide passivation contact cells) or heterojunction cells and IBC cell technology. The IBC cell technology can be stacked TOPCon or a heterojunction structure, such as a TBC back contact solar cell (TOPCon-IBC cell) is constructed, and the tunneling oxide passivation contact of the TOPCon technology and the interdigital back contact structure of the IBC technology are combined, so that the cell efficiency can be further improved. The current TBC battery technology is mostly prepared by deposition or printing mask and wet etching or printing paste diffusion, however, the wet etching process is complex, printing paste has more or less pollution problems and the same procedure is complex, and the battery efficiency is difficult to improve.

Therefore, how to further improve the photoelectric conversion efficiency of the solar cell is a technical problem to be solved.

Disclosure of utility model

Aiming at the defects of the prior art, the utility model aims to provide a solar cell and a photovoltaic module. The utility model provides a solar cell with a novel structure, which solves the problems of low efficiency caused by the combination of a metal electrode and a silicon substrate interface and the problem of conduction and leakage between PN, and has excellent photoelectric conversion efficiency. And the solar cell has a large process window and high mass productivity.

In order to achieve the aim of the utility model, the utility model adopts the following technical scheme:

In a first aspect, the utility model provides a solar cell, which comprises a silicon substrate, wherein a tunneling oxide layer which is discontinuously distributed is arranged on the back surface of the silicon substrate, the tunneling oxide layer is divided into a plurality of P regions and a plurality of N regions, and the P regions and the N regions are alternately arranged at intervals in sequence;

The P region is provided with a p+ doped layer, and the p+ doped layer comprises a p+ doped polycrystalline silicon carbide layer and a p+ doped polycrystalline silicon layer along the direction far away from the tunneling oxide layer;

A back passivation layer and a back antireflection layer are respectively arranged on the outer surface of the p+ doped polycrystalline silicon layer, the interval region between the P region and the N region and the outer surface of the n+ doped polycrystalline silicon carbide layer in a lamination manner along the direction far away from the silicon substrate;

The P region is provided with a first back metal electrode, one end of the first back metal electrode forms ohmic contact with the p+ doped polycrystalline silicon layer, the other end of the first back metal electrode extends out of the back anti-reflection layer on the P region, the N region is provided with a second back metal electrode, one end of the second back metal electrode forms ohmic contact with the n+ doped polycrystalline silicon carbide layer, and the other end of the second back metal electrode extends out of the back anti-reflection layer on the N region.

The utility model provides a solar cell with a novel structure, which solves the problems of low efficiency caused by the combination of a metal electrode and a silicon substrate interface and the conduction and leakage between PN junctions, and has excellent photoelectric conversion efficiency. And the solar cell has a large process window and high mass productivity.

The outer surface of the p+ doped polysilicon layer refers to the surface thereof that is not in contact with the p+ doped polysilicon carbide layer, and the outer surface of the n+ doped polysilicon carbide layer refers to the surface thereof that is not in contact with the N region of the tunnel oxide layer.

Preferably, the silicon substrate is an n-type silicon wafer.

The resistivity of the n-type silicon wafer is preferably 0.3 to 7Ω·cm, and may be, for example, 0.3 Ω·cm, 0.5 Ω·cm, 1 Ω·cm, 2 Ω·cm, 3 Ω·cm, 4 Ω·cm, 5 Ω·cm, 6 Ω·cm, or 7Ω·cm, and the like, and preferably 0.5 to 3.5 Ω·cm.

Preferably, the tunnel oxide layer comprises a silicon oxide layer.

Preferably, the thickness of the tunneling oxide layer is 0.5-3nm, for example, 0.5nm, 1nm, 1.5nm, 2nm, 2.5nm or 3nm, and preferably 1-2.5nm.

Preferably, the p+ doped polycrystalline silicon carbide layer is a p+ boron doped polycrystalline silicon carbide layer.

Preferably, the doping concentration of the doping element in the p+ doped polysilicon carbide layer is 3×10 ¹⁹-5×10²⁰cm^-3, for example, 3×10 ¹⁹cm^-3、5×10¹⁹cm^-3、1×10²⁰cm^-3、3×10²⁰cm^-3 or 5×10 ²⁰cm^-3.

Preferably, the thickness of the p+ doped polycrystalline silicon carbide layer is 30-100nm, for example, 30nm, 50nm, 70nm or 90nm, etc.

Preferably, the p+ doped polysilicon layer is a p+ boron doped polysilicon layer.

Preferably, the doping concentration of the doping element in the p+ doped polysilicon layer is 3×10 ¹⁹-5×10²⁰cm^-3, for example, it may be 3×10 ¹⁹cm^-3、5×10¹⁹cm^-3、1×10²⁰cm^-3、3×10²⁰cm^-3 or 5×10 ²⁰cm^-3.

Preferably, the thickness of the p+ doped polysilicon layer is 50-200nm, for example, 50nm, 100nm, 150nm or 200nm, etc.

Preferably, the n+ doped polycrystalline silicon carbide layer is an n+ phosphorus doped polycrystalline silicon carbide layer.

Preferably, the doping concentration of the doping element in the n+ doped polysilicon carbide layer is 4×10 ²⁰-2×10²¹cm^-3, for example, 4×10 ²⁰cm^-3、6×10²⁰cm^-3、8×10²⁰cm^-3、1×10²¹cm^-3 or 2×10 ²¹cm^-3.

Preferably, the thickness of the n+ doped polycrystalline silicon carbide layer is 30-100nm, for example, 30nm, 50nm, 70nm or 90nm, etc.

Preferably, the width of the discontinuity between adjacent said P-and N-regions is 10-60 μm, for example 10 μm, 20 μm, 30 μm, 40 μm, 50 μm or 60 μm etc.

Preferably, the front surface of the silicon substrate is of a suede structure, and the front surface is sequentially provided with a phosphorus diffusion lightly doped layer, a front surface passivation layer and a front surface anti-reflection layer along the direction away from the silicon substrate.

Preferably, the back passivation layer and the front passivation layer each independently include a silicon oxide layer and/or an aluminum oxide layer.

Preferably, the thickness of the back passivation layer and the front passivation layer is 2-10nm, for example, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm or 10nm, etc. independently.

Preferably, the back side anti-reflection layer and the front side anti-reflection layer each independently include any one or a combination of at least two of a silicon nitride layer, a silicon oxynitride layer, or a silicon oxide layer.

Preferably, the thickness of the back side antireflection layer and the front side antireflection layer is 60 to 150nm, for example, 60nm, 80nm, 100nm, 110nm, 130nm or 150nm, etc., and preferably 60 to 100nm, independently.

Preferably, the first back metal electrode and the second back metal electrode each independently comprise a silver electrode and/or an aluminum electrode.

Preferably, the surface phosphorus element concentration of the phosphorus-doped layer is 5×10 ¹⁷-5×10²⁰cm^-3, for example, 5×10 ¹⁷cm^-3、5×10¹⁸cm^-3、5×10¹⁹cm^-3 or 5×10 ²⁰cm^-3, and preferably 1×10 ¹⁸-1×10²⁰cm^-3.

Preferably, the diffusion sheet resistance of the phosphorus diffusion lightly doped layer is 200-500 Ω/sq, and can be, for example, 200 Ω/sq, 300 Ω/sq, 400 Ω/sq, 500 Ω/sq, or the like.

Preferably, the junction depth of the phosphorus-diffused lightly doped layer is 0.3-1.5 μm, and may be, for example, 0.3 μm, 0.5 μm, 0.7 μm, 0.9 μm, 1.2 μm or 1.5 μm.

In a second aspect, the present utility model provides a method for manufacturing a solar cell according to the first aspect, the method comprising the steps of:

(1) Sequentially growing a tunneling oxide layer, a p+ doped amorphous silicon carbide layer, a p+ doped amorphous silicon layer and a first mask layer on the back surface of the silicon substrate, and then performing patterning laser windowing and etching treatment to remove the first mask layer and the p+ doped amorphous silicon layer in the laser windowing region to form grooves distributed at intervals;

(2) Sequentially growing an n+ doped amorphous silicon layer and a second mask layer on the first mask layer processed in the step (1) and the p+ doped amorphous silicon carbide layer in the groove, then carrying out laser windowing and etching treatment at the junction of the P/N region to form a channel so as to isolate the P/N region, and simultaneously carrying out texturing treatment on the front surface of the silicon substrate and cleaning to remove the second mask layer, wherein the channel penetrates through the tunneling oxide layer, the p+ doped amorphous silicon carbide layer, the n+ doped amorphous silicon layer and the second mask layer at the junction of the P/N region;

(3) Performing phosphorus expansion on the silicon substrate subjected to the texturing in the step (2), then performing oxidation annealing treatment to convert the p+ doped amorphous silicon carbide layer, the p+ doped amorphous silicon layer and the n+ doped amorphous silicon layer on the back into a p+ doped polycrystalline silicon carbide layer, a p+ doped polycrystalline silicon layer and a PSG layer respectively, simultaneously converting the p+ doped amorphous silicon carbide layer connected with the n+ doped amorphous silicon layer into an n+ doped polycrystalline silicon carbide layer, and then removing the PSG layer and the first mask layer;

(4) And (3) sequentially growing a passivation layer and an anti-reflection layer on the front and back surfaces of the silicon substrate treated in the step (3), and then carrying out metallization treatment and sintering treatment to enable an N region and a P region on the back surface to respectively form a first back metal electrode and a second back metal electrode, wherein one end of the first back metal electrode forms ohmic contact with the p+ doped polycrystalline silicon layer, and one end of the second back metal electrode forms ohmic contact with the n+ doped polycrystalline silicon carbide layer, so that the solar cell is obtained.

The preparation method provided by the utility model has the advantages of simple process, large process window and strong mass productivity. In addition, the front and back passivation layers are formed for the non-diffused areas at intervals, so that interface recombination is effectively reduced, and passivation effect is ensured. In addition, during oxidation annealing treatment, the P-type amorphous silicon carbide connected with the n+ doped amorphous silicon layer can be directly converted into the n+ doped polycrystalline silicon carbide layer, so that n-type and P-type tunneling passivation contact structures are formed in one step, and the influence of primary environment on the tunneling oxide layer is reduced.

Preferably, the silicon substrate of step (1) is a double-sided polished n-type silicon wafer.

Preferably, the p+ doped amorphous silicon carbide layer in the step (1) is a single-layer film or a multi-layer film.

Preferably, the multilayer film comprises any one layer or a combination of at least two layers of intrinsic layer, lightly doped layer or heavily doped layer.

Preferably, the material of the first mask layer comprises silicon oxide.

Preferably, the thickness of the first mask layer is 20-100nm, for example, 20nm, 40nm, 60nm, 80nm or 100nm, etc.

Preferably, the growth methods of the tunnel oxide layer, the p+ doped amorphous silicon carbide layer, the p+ doped amorphous silicon layer and the first mask layer in the step (1) each independently include a PECVD method (plasma enhanced chemical vapor deposition method).

Preferably, the laser used in the patterning laser windowing in step (1) comprises an ultraviolet nanosecond laser or a picosecond laser.

Preferably, during the etching treatment in step (1), the etchant used includes any one or a combination of at least two of KOH, naOH, or TMAH.

Preferably, the thickness of the n+ doped amorphous silicon layer in the step (2) is 30-100nm, for example, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm or 100nm, etc.

Preferably, the n+ doped amorphous silicon layer in the step (2) is a single-layer film or a multi-layer film.

Preferably, when the n+ doped amorphous silicon layer of step (2) is a multilayer film, the multilayer film includes a lightly doped layer and a heavily doped layer.

Preferably, the material of the second mask layer in step (2) includes silicon oxide.

Preferably, the thickness of the second mask layer in the step (2) is 10-50nm, for example, 10nm, 20nm, 30nm, 40nm or 50nm may be used.

Preferably, the growing method of the n+ doped amorphous silicon layer and the second mask layer in the step (2) each independently includes a PECVD method.

Preferably, in the process of windowing the laser in step (2), the laser used includes green light or infrared band laser.

Preferably, the method of the etching treatment in the step (2) includes wet etching.

Preferably, during the phosphorus expansion of step (3), the phosphorus source used comprises phosphorus oxychloride.

Preferably, the temperature of the phosphorus expansion in step (3) is 800-900 ℃, and may be 800 ℃, 820 ℃, 840 ℃, 860 ℃, 880 ℃, 900 ℃ or the like.

Preferably, the atmosphere of the oxidation annealing treatment in the step (3) is an oxygen-containing atmosphere.

Preferably, the gas in the oxygen-containing atmosphere comprises oxygen and an inert gas. The inert gas may be, for example, nitrogen or the like.

Preferably, the temperature of the oxidation annealing treatment in step (3) is 900-1000 ℃, and may be 900 ℃, 920 ℃, 940 ℃, 960 ℃, 980 ℃, 1000 ℃ or the like.

Preferably, the method for growing the passivation layer in the step (4) includes a thermal oxidation method or an ALD method (atomic layer deposition method).

Preferably, the growth method of the anti-reflection layer in the step (4) comprises a PECVD method.

Preferably, the metallization in the step (4) includes any one of screen printing, laser transfer printing or electroplating.

Preferably, the peak temperature of the sintering treatment in step (4) is 650-750 ℃, and may be 650 ℃, 700 ℃, 750 ℃ or the like.

Preferably, after the sintering treatment in step (4), a post-treatment is further performed, and the post-treatment mode includes light injection annealing.

In the utility model, the step of light injection annealing can further improve the photoelectric conversion efficiency of the solar cell.

In a third aspect, the present utility model provides a photovoltaic module comprising a solar cell according to the first aspect.

The numerical ranges recited herein include not only the recited point values, but also any point values between the recited numerical ranges that are not recited, and are limited to, and for the sake of brevity, the utility model is not intended to be exhaustive of the specific point values that the recited range includes.

Compared with the prior art, the utility model has the following beneficial effects:

The utility model provides a solar cell with a novel structure, which solves the problems of low efficiency caused by the combination of a metal electrode and a silicon substrate interface and the problem of conduction and leakage between PN, and has excellent photoelectric conversion efficiency.

Drawings

Fig. 1 is a schematic structural diagram of a solar cell according to embodiment 1 of the present utility model.

The semiconductor device comprises a 1-n type silicon wafer, a 2-phosphorus diffusion lightly doped layer, a 3-front passivation layer, a 4-front anti-reflection layer, a 5-tunneling oxide layer, a 6-p+ doped polycrystalline silicon carbide layer, a 7-p+ doped polycrystalline silicon layer, an 8-n+ doped polycrystalline silicon carbide layer, a 9-back passivation layer, a 10-back anti-reflection layer, a 11-first back metal electrode and a 12-second back metal electrode.

Detailed Description

The technical scheme of the utility model is further described by the following specific embodiments. It will be apparent to those skilled in the art that the examples are merely to aid in understanding the utility model and are not to be construed as a specific limitation thereof.

Example 1

The embodiment provides a solar cell, the structure of which is shown in fig. 1, wherein the solar cell comprises an N-type silicon wafer 1 with resistivity of 1.5 Ω & cm, a tunneling oxide layer 5 which is discontinuously distributed is arranged on the back surface of the N-type silicon wafer 1, the tunneling oxide layer 5 is divided into a plurality of P regions and a plurality of N regions, the P regions and the N regions are alternately arranged in sequence at intervals, a p+ doped layer is arranged on the P region, the p+ doped layer comprises a p+ doped polycrystalline silicon carbide layer 6 and a p+ doped polycrystalline silicon layer 7 along the direction far away from the tunneling oxide layer 5, and an n+ doped polycrystalline silicon carbide layer 8 is arranged on the N region.

The tunneling oxide layer 5 is a silicon oxide layer with the thickness of 1.5nm, the p+ doped polycrystalline silicon carbide layer 6 is a p+ boron doped polycrystalline silicon carbide layer with the doping concentration of 1×10 ²⁰cm^-3 and the thickness of 60nm, the p+ doped polycrystalline silicon layer 7 is a p+ boron doped polycrystalline silicon layer with the doping concentration of 1×10 ²⁰cm^-3 and the thickness of 120nm, the n+ doped polycrystalline silicon carbide layer 8 is an n+ phosphorus doped polycrystalline silicon carbide layer with the doping concentration of 1×10 ²¹cm^-3 and the thickness of 60nm, and the n+ doped polycrystalline silicon carbide layer 8 and the p+ doped polycrystalline silicon carbide layer 6 have the same thickness.

The outer surface of the p+ doped polysilicon layer 7, the interval region (width: 30 μm) between the P region and the N region, and the back passivation layer 9 and the back anti-reflection layer 10 are laminated on the outer surface of the n+ doped polysilicon layer along the direction away from the N-type silicon wafer 1.

The back passivation layer 9 is a silicon oxide layer with the thickness of 3.5nm, and the back anti-reflection layer 10 comprises a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer with the thickness of 100nm.

The back passivation layer 9 and the back anti-reflection layer 10 which are arranged on the p+ doped polysilicon layer 7 are provided with first grooves at part, a first back metal electrode 11 is arranged in the first grooves, one end of the first back metal electrode 11 forms ohmic contact with the p+ doped polysilicon layer 7, the other end extends out of the back anti-reflection layer 10, the back passivation layer 9 and the back anti-reflection layer 10 which are arranged on the n+ doped polysilicon layer 8 are provided with second grooves at part, a second back metal electrode 12 is arranged in the second grooves, one end of the second back metal electrode 12 forms ohmic contact with the n+ doped polysilicon layer 8, and the other end extends out of the back anti-reflection layer 10, wherein the first back metal electrode 11 is a silver electrode, and the second back metal electrode 12 is a silver electrode.

The front surface of the n-type silicon wafer 1 is of a suede structure, a phosphorus-doped light-doped layer 2, a front surface passivation layer 3 and a front surface anti-reflection layer 4 are sequentially arranged on the front surface along the direction away from the n-type silicon wafer 1, wherein the surface phosphorus element concentration of the phosphorus-doped light-doped layer 2 is 1 multiplied by 10 ¹⁹cm^-3, the diffusion sheet resistance is 400 omega/sq, the junction depth is 1 mu m, the front surface passivation layer 3 is a silicon oxide layer, the thickness is 3.5nm, the front surface anti-reflection layer 4 comprises a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer, and the thickness is 80nm.

The embodiment also provides a preparation method of the TBC back contact solar cell, which comprises the following steps:

(1) And (3) carrying out alkali polishing on the n-type silicon wafer, removing the front and back mechanical damage layers, then adopting an RCA cleaning method to carry out cleaning treatment, then adopting a PECVD method to sequentially grow a tunneling oxide layer, a p+ doped amorphous silicon carbide layer, a p+ doped amorphous silicon layer and a first mask layer on the back of the n-type silicon wafer, then carrying out patterning laser windowing by utilizing ultraviolet skin second laser, and carrying out etching treatment on a laser windowing region by utilizing KOH, so that the first mask layer and the p+ doped amorphous silicon layer of the laser windowing region are removed, and forming grooves which are distributed at intervals, wherein the width of each groove is 600 mu m.

The p+ doped amorphous silicon carbide layer comprises an intrinsic amorphous silicon carbide layer with the thickness of 20nm and a p+ lightly doped amorphous silicon carbide layer with the thickness of 40nm along the direction far away from the tunneling oxide layer, and the first mask layer is made of silicon oxide and has the thickness of 40nm.

(2) And (2) sequentially growing an n+ phosphorus doped amorphous silicon layer with the thickness of 50nm and a second mask layer with the thickness of 20nm on the first mask layer processed in the step (1) and the p+ doped amorphous silicon carbide layer in the first slot by adopting a PECVD method, then carrying out laser windowing on the junction of the P/N region by utilizing ultraviolet nanosecond laser with the wavelength of 532nm, carrying out wet etching on the second mask layer, the n+ phosphorus doped amorphous silicon layer and the p+ doped amorphous silicon carbide layer at the laser windowing, forming a channel with the width of 30 mu m to disconnect and isolate the P/N region, and simultaneously carrying out texturing treatment on the front surface of an N-type silicon wafer, and cleaning to remove the second mask layer.

The second mask layer is made of silicon oxide, and the channel penetrates through the tunneling oxide layer, the p+ doped amorphous silicon carbide layer, the n+ phosphorus doped amorphous silicon layer and the second mask layer at the junction of the P/N region.

(3) And (3) under the condition of 840 ℃, phosphorus oxychloride is used as a phosphorus source, phosphorus expansion is carried out on the n-type silicon wafer subjected to the texturing in the step (2), then oxidation annealing treatment is carried out in an oxygen-containing atmosphere consisting of nitrogen and oxygen, the oxidation annealing treatment process is gradient annealing and comprises primary annealing at the temperature of 910 ℃ and secondary annealing at the temperature of 940 ℃, so that a phosphorus expansion lightly doped layer is formed on the front surface of the n-type silicon wafer, a p+ doped amorphous silicon carbide layer, a p+ doped amorphous silicon layer and an n+ phosphorus doped amorphous silicon layer on the back surface are respectively converted into a p+ doped polycrystalline silicon carbide layer, a p+ doped polycrystalline silicon layer and a PSG layer, and meanwhile, the p+ doped amorphous silicon carbide layer connected with the n+ phosphorus doped amorphous silicon layer is converted into an n+ doped polycrystalline silicon carbide layer.

(4) And removing the PSG layer by using hydrofluoric acid, and then removing the first mask layer by adopting an RCA cleaning method.

(5) And (3) respectively growing passivation layers on the front and back surfaces of the n-type silicon wafer treated in the step (4) by adopting a thermal oxidation method, and respectively and sequentially growing a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer on the passivation layers on the front and back surfaces of the n-type silicon wafer by adopting a PECVD method to serve as an anti-reflection layer.

(6) Printing silver paste on the N area of the back of the N-type silicon wafer processed in the step (5) through a screen printing method, printing silver paste on the P area, respectively forming patterned metal electrodes, then conducting contact treatment on the metal electrodes at 750 ℃ to obtain a first back metal electrode and a second back metal electrode, enabling one end of the first back metal electrode to form ohmic contact with the p+ doped polycrystalline silicon layer, enabling one end of the second back metal electrode to form ohmic contact with the n+ doped polycrystalline silicon carbide layer, and conducting post treatment through a light injection annealing method to finally obtain the solar cell.

Example 2

The embodiment provides a solar cell, which comprises an N-type silicon wafer with resistivity of 1 ohm cm, wherein a tunneling oxide layer which is discontinuously distributed is arranged on the back surface of the N-type silicon wafer, the tunneling oxide layer is divided into a plurality of P regions and a plurality of N regions, p+ doped layers are sequentially arranged on the P regions at intervals alternately, the p+ doped layers comprise p+ doped polycrystalline silicon carbide layers and p+ doped polycrystalline silicon layers along the direction away from the tunneling oxide layer, and n+ doped polycrystalline silicon carbide layers are arranged on the N regions.

The tunneling oxide layer is a silicon oxide layer with the thickness of 0.5nm, the p+ doped polycrystalline silicon carbide layer is a p+ boron doped polycrystalline silicon carbide layer with the doping concentration of 3×10 ¹⁹cm^-3 and the thickness of 30nm, the p+ doped polycrystalline silicon layer is a p+ boron doped polycrystalline silicon layer with the doping concentration of 3×10 ¹⁹cm^-3 and the thickness of 50nm, the n+ doped polycrystalline silicon carbide layer is an n+ phosphorus doped polycrystalline silicon carbide layer with the doping concentration of 4×10 ²⁰cm^-3 and the thickness of 30nm, and the n+ doped polycrystalline silicon carbide layer and the p+ doped polycrystalline silicon carbide layer have the same thickness.

And a back passivation layer and a back anti-reflection layer are respectively and repeatedly arranged on the outer surface of the p+ doped polycrystalline silicon layer, the interval region (the width is 10 mu m) between the P region and the N region and the outer surface of the n+ doped polycrystalline silicon carbide layer along the direction far away from the N-type silicon wafer.

The back passivation layer is an aluminum oxide layer with the thickness of 2nm, and the back anti-reflection layer comprises a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer with the thickness of 60nm.

The back passivation layer and the back antireflection layer arranged on the n+ doped polycrystalline silicon layer are provided with second grooves in part, a second back metal electrode is arranged in the second grooves, one end of the second back metal electrode forms ohmic contact with the n+ doped polycrystalline silicon carbide layer, and the other end of the second back metal electrode extends out of the back antireflection layer, wherein the first back metal electrode is a silver electrode, and the second back metal electrode is a silver electrode.

The front surface of the n-type silicon wafer is of a suede structure, a phosphorus-doped light-doped layer, a front passivation layer and a front surface antireflection layer are sequentially arranged on the front surface along the direction far away from the n-type silicon wafer, wherein the surface phosphorus element concentration of the phosphorus-doped light-doped layer is 5 multiplied by 10 ¹⁷cm^-3, the diffusion sheet resistance is 500 Ω/sq, the junction depth is 0.5 mu m, the front surface passivation layer is an aluminum oxide layer with the thickness of 2nm, and the front surface antireflection layer comprises a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer with the thickness of 60nm.

The embodiment also provides a preparation method of the TBC back contact solar cell, which comprises the following steps:

(1) And (3) carrying out alkali polishing on the n-type silicon wafer, removing the front and back mechanical damage layers, then adopting an RCA cleaning method to carry out cleaning treatment, then adopting a PECVD method to sequentially grow a tunneling oxide layer, a p+ doped amorphous silicon carbide layer, a p+ doped amorphous silicon layer and a first mask layer on the back of the n-type silicon wafer, then carrying out patterning laser windowing by utilizing ultraviolet skin second laser, and carrying out etching treatment on a laser windowing region by utilizing KOH, so that the first mask layer and the p+ doped amorphous silicon layer of the laser windowing region are removed, and forming grooves which are distributed at intervals, wherein the width of each groove is 100 mu m.

The first mask layer is made of silicon oxide and has a thickness of 20nm.

(2) And (2) sequentially growing an n+ phosphorus doped amorphous silicon layer with the thickness of 30nm and a second mask layer with the thickness of 10nm on the first mask layer processed in the step (1) and the p+ doped amorphous silicon carbide layer in the first slot by adopting a PECVD method, then carrying out laser windowing on the junction of the P/N region by utilizing ultraviolet nanosecond laser with the wavelength of 532nm, carrying out wet etching on the second mask layer, the n+ phosphorus doped amorphous silicon layer and the p+ doped amorphous silicon carbide layer at the laser windowing, forming a channel with the width of 10 mu m to disconnect and isolate the P/N region, and simultaneously carrying out texturing treatment on the front surface of an N-type silicon wafer, and cleaning to remove the second mask layer.

The second mask layer is made of silicon oxide, and the channel penetrates through the tunneling oxide layer, the p+ doped amorphous silicon carbide layer, the n+ phosphorus doped amorphous silicon layer and the second mask layer at the junction of the P/N region.

(3) And (3) under the condition of 800 ℃, phosphorus oxychloride is used as a phosphorus source, phosphorus expansion is carried out on the n-type silicon wafer subjected to the texturing in the step (2), then oxidation annealing treatment is carried out in an oxygen-containing atmosphere consisting of nitrogen and oxygen, the oxidation annealing treatment process is gradient annealing and comprises primary annealing at the temperature of 900 ℃ and secondary annealing at the temperature of 970 ℃, so that a phosphorus expansion lightly doped layer is formed on the front surface of the n-type silicon wafer, a p+ doped amorphous silicon carbide layer, a p+ doped amorphous silicon layer and an n+ phosphorus doped amorphous silicon layer on the back surface are respectively converted into a p+ doped polycrystalline silicon carbide layer, a p+ doped polycrystalline silicon layer and a PSG layer, and meanwhile, the p+ doped amorphous silicon carbide layer connected with the n+ phosphorus doped amorphous silicon layer is converted into an n+ doped polycrystalline silicon carbide layer.

(4) And removing the PSG layer by using hydrofluoric acid, and then removing the first mask layer by adopting an RCA cleaning method.

(5) And (3) respectively growing passivation layers on the front and back surfaces of the n-type silicon wafer treated in the step (4) by adopting a thermal oxidation method, and respectively and sequentially growing a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer on the passivation layers on the front and back surfaces of the n-type silicon wafer by adopting a PECVD method to serve as an anti-reflection layer.

(6) Printing silver paste on the N area of the back of the N-type silicon wafer processed in the step (5) through a screen printing method, printing silver-aluminum paste on the P area, respectively forming patterned metal electrodes, then conducting contact treatment on the metal electrodes at 730 ℃ to obtain a first back metal electrode and a second back metal electrode, enabling one end of the first back metal electrode to form ohmic contact with the p+ doped polycrystalline silicon layer, enabling one end of the second back metal electrode to form ohmic contact with the n+ doped polycrystalline silicon carbide layer, and conducting post treatment through a light injection annealing method to finally obtain the solar cell.

Example 3

The embodiment provides a solar cell, which comprises an N-type silicon wafer with resistivity of 2 omega cm, wherein a tunneling oxide layer is arranged on the back surface of the N-type silicon wafer, the tunneling oxide layer is divided into a plurality of P regions and a plurality of N regions, the P regions and the N regions are sequentially and alternately arranged at intervals, a p+ doped layer is arranged on the P region, the p+ doped layer comprises a p+ doped polycrystalline silicon carbide layer and a p+ doped polycrystalline silicon layer along the direction far away from the tunneling oxide layer, and an n+ doped polycrystalline silicon carbide layer is arranged on the N.

The tunneling oxide layer is a silicon oxide layer with the thickness of 3nm, the p+ doped polycrystalline silicon carbide layer is a p+ boron doped polycrystalline silicon carbide layer with the doping concentration of 5 multiplied by 10 ²⁰cm^-3 with the thickness of 100nm, the p+ doped polycrystalline silicon layer is a p+ boron doped polycrystalline silicon layer with the doping concentration of 5 multiplied by 10 ²⁰cm^-3 with the thickness of 200nm, and the n+ doped polycrystalline silicon carbide layer is an n+ phosphorus doped polycrystalline silicon carbide layer with the doping concentration of 2 multiplied by 10 ²¹cm^-3 with the thickness of 100nm.

And a back passivation layer and a back anti-reflection layer are respectively and repeatedly arranged on the outer surface of the p+ doped polycrystalline silicon layer, the interval region (the width is 60 mu m) between the P region and the N region and the outer surface of the n+ doped polycrystalline silicon carbide layer along the direction far away from the N-type silicon wafer.

The back passivation layer is a silicon oxide layer with the thickness of 10nm, and the back anti-reflection layer comprises a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer with the thickness of 90nm.

The back passivation layer and the back antireflection layer arranged on the n+ doped polycrystalline silicon layer are provided with second grooves in part, a second back metal electrode is arranged in the second grooves, one end of the second back metal electrode forms ohmic contact with the n+ doped polycrystalline silicon carbide layer, and the other end of the second back metal electrode extends out of the back antireflection layer, wherein the first back metal electrode is a silver electrode, and the second back metal electrode is a silver electrode.

The front surface of the n-type silicon wafer is of a suede structure, a phosphorus-doped light-doped layer, a front passivation layer and a front surface antireflection layer are sequentially arranged on the front surface along the direction away from the n-type silicon wafer, wherein the surface phosphorus element concentration of the phosphorus-doped light-doped layer is 5 multiplied by 10 ²⁰cm^-3, the diffusion sheet resistance is 200 omega/sq, the junction depth is 1.5 mu m, the front surface passivation layer is made of silicon oxide and has the thickness of 10nm, and the back surface antireflection layer comprises a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer and has the thickness of 90nm.

The embodiment also provides a preparation method of the TBC back contact solar cell, which comprises the following steps:

(1) And (3) carrying out alkali polishing on the n-type silicon wafer, removing the front and back mechanical damage layers, then adopting an RCA cleaning method to carry out cleaning treatment, then adopting a PECVD method to sequentially grow a tunneling oxide layer, a p+ doped amorphous silicon carbide layer, a p+ doped amorphous silicon layer and a first mask layer on the back of the n-type silicon wafer, then carrying out patterning laser windowing by utilizing ultraviolet skin second laser, and carrying out etching treatment on a laser windowing region by utilizing KOH, so that the first mask layer and the p+ doped amorphous silicon layer of the laser windowing region are removed, and forming grooves which are distributed at intervals, wherein the width of each groove is 1000 mu m.

The first mask layer is made of silicon oxide and has a thickness of 100nm.

(2) And (2) sequentially growing an n+ phosphorus doped amorphous silicon layer with the thickness of 100nm and a second mask layer with the thickness of 50nm on the first mask layer processed in the step (1) and the p+ doped amorphous silicon carbide layer in the first slot by adopting a PECVD method, then carrying out laser windowing on the junction of the P/N region by utilizing ultraviolet nanosecond laser with the wavelength of 532nm, carrying out wet etching on the second mask layer, the n+ phosphorus doped amorphous silicon layer and the p+ doped amorphous silicon carbide layer at the laser windowing, forming a channel with the width of 60 mu m to disconnect and isolate the P/N region, and simultaneously carrying out texturing treatment on the front surface of an N-type silicon wafer, and cleaning to remove the second mask layer.

The second mask layer is made of silicon oxide, and the channel penetrates through the tunneling oxide layer, the p+ doped amorphous silicon carbide layer, the n+ phosphorus doped amorphous silicon layer and the second mask layer at the junction of the P/N region.

(3) And (3) under the condition of 900 ℃, phosphorus oxychloride is used as a phosphorus source, phosphorus expansion is carried out on the n-type silicon wafer subjected to the texturing in the step (2), then oxidation annealing treatment is carried out in an oxygen-containing atmosphere consisting of nitrogen and oxygen, the oxidation annealing treatment process is gradient annealing and comprises primary annealing at the temperature of 930 ℃ and secondary annealing at the temperature of 1000 ℃, so that a phosphorus expansion lightly doped layer is formed on the front surface of the n-type silicon wafer, a p+ doped amorphous silicon carbide layer, a p+ doped amorphous silicon layer and an n+ phosphorus doped amorphous silicon layer on the back surface are respectively converted into a p+ doped polycrystalline silicon carbide layer, a p+ doped polycrystalline silicon layer and a PSG layer, and meanwhile, the p+ doped amorphous silicon carbide layer connected with the n+ phosphorus doped amorphous silicon layer is converted into an n+ doped polycrystalline silicon carbide layer.

(4) And removing the PSG layer by using hydrofluoric acid, and then removing the first mask layer by adopting an RCA cleaning method.

(5) And (3) respectively growing passivation layers on the front and back surfaces of the n-type silicon wafer treated in the step (4) by adopting a thermal oxidation method, and respectively and sequentially growing a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer on the passivation layers on the front and back surfaces of the n-type silicon wafer by adopting a PECVD method to serve as an anti-reflection layer.

(6) Printing silver paste on the N area of the back of the N-type silicon wafer processed in the step (5) through a screen printing method, printing silver-aluminum paste on the P area, respectively forming patterned metal electrodes, then carrying out contact treatment on the metal electrodes at 520 ℃ to obtain a first back metal electrode and a second back metal electrode, wherein one end of the first back metal electrode forms ohmic contact with the p+ doped polysilicon layer, one end of the second back metal electrode forms ohmic contact with the n+ doped polysilicon layer, and then carrying out post treatment through a light injection annealing method to finally obtain the solar cell.

Example 4

The difference between this embodiment and embodiment 1 is that the thickness of the tunnel oxide layer is 5nm.

The remaining product structure and parameters remained the same as in example 1.

Example 5

This example differs from example 1 in that the total thickness of the p+ doped polycrystalline silicon carbide layer is 20nm.

The remaining product structure and parameters remained the same as in example 1.

Example 6

This example differs from example 1 in that the total thickness of the p+ doped polycrystalline silicon carbide layer is 120nm.

The remaining product structure and parameters remained the same as in example 1.

Example 7

The present embodiment differs from embodiment 1 in that the thickness of the p+ doped polysilicon layer is 30nm.

The remaining product structure and parameters remained the same as in example 1.

Example 8

The difference between this embodiment and embodiment 1 is that the thickness of the p+ doped polysilicon layer is 220nm.

The remaining product structure and parameters remained the same as in example 1.

Comparative example 1

This comparative example differs from example 1 in that no p+ -doped polysilicon layer is provided, i.e., the growth of the p+ -doped amorphous silicon layer is not performed in step (1).

The remaining product structure and parameters remained the same as in example 1.

Comparative example 2

This comparative example differs from example 1 in that no p+ -doped polycrystalline silicon carbide layer is provided, i.e., no growth of the p+ -doped amorphous silicon carbide layer is performed in step (1).

The remaining product structure and parameters remained the same as in example 1.

Comparative example 3

This comparative example differs from example 1 in that the p+ doped polysilicon layer is replaced with a p+ doped polysilicon layer.

The remaining product structure and parameters remained the same as in example 1.

Comparative example 4

This comparative example differs from example 1 in that the P and N regions are closely bonded, i.e., the tunnel oxide layer is a continuous layer.

The remaining product structure and parameters remained the same as in example 1.

Performance testing

The TBC back contact solar cells prepared in the examples and the comparative examples are subjected to photoelectric performance test under the conditions of light intensity of 1000W/m ² and test temperature of 25+/-2 ℃.

The test results are shown in Table 1.

TABLE 1

Analysis:

From the above, the TBC back contact solar cell provided by the utility model solves the problems of low efficiency caused by the combination of the metal electrode and the silicon substrate interface and the problem of conduction and leakage between PN, and has excellent photoelectric conversion efficiency.

As can be seen from examples 1 and 4, if the thickness of the tunnel oxide layer is too thick, the doping concentrations of the P region and the N region to the silicon substrate are too low, the series resistance is high, and the contact is poor.

As can be seen from examples 1 and 5-6, if the thickness of the p+ doped polysilicon carbide layer is too small, the metal electrodes in the P region and the N region are both easy to burn through, directly contact the silicon substrate, destroy the tunneling layer, and affect passivation and contact, and if the thickness of the p+ doped polysilicon carbide layer is too large, the parasitic absorption is high and the current is low.

It is known from examples 1 and 7-8 that if the thickness of the p+ doped polysilicon layer is too small, the metal electrode in the P region is easy to burn through, directly contacts the silicon substrate, damages the tunneling layer, and affects passivation and contact, and if the thickness of the p+ doped polysilicon layer is too large, the parasitic absorption is high and the current is low.

As can be seen from example 1 and comparative example 1, if the p+ doped polysilicon layer is not provided, the metal electrode of the P region is easy to burn through, directly contacts the silicon substrate, damages the tunneling layer, and affects passivation and contact.

As can be seen from examples 1 and 2, if the p+ doped polysilicon carbide layer is not provided, the metal electrodes in the P region and the N region are easy to burn through, directly contact the silicon substrate, damage the tunneling layer, and affect passivation and contact.

As can be seen from examples 1 and 3, if the p+ doped polysilicon layer is replaced with the p+ doped polysilicon layer, that is, the p+ doped amorphous silicon carbide layer in step (1) is replaced with the p+ doped amorphous silicon layer, then the p+ doped amorphous silicon layer reacts with the base due to the etching treatment in step (1), so that only the remaining p+ doped polysilicon layer exists in the N region, and is subsequently converted into a small amount of n+ doped polysilicon layer, which results in that the N region slurry directly burns through the contact silicon substrate, the dark current density J0 is extremely high, and the contact is extremely large.

As is clear from example 1 and comparative example 4, if the P region and the N region are closely attached, the P region and the N region are directly turned on, and the electron holes are directly recombined, which is extremely low in efficiency.

The applicant states that the process of the utility model is illustrated by the above examples, but the utility model is not limited to, i.e. does not mean that the utility model must be carried out in dependence on the above process steps. It should be apparent to those skilled in the art that any modification of the present utility model, equivalent substitution of selected raw materials, addition of auxiliary components, selection of specific modes, etc. fall within the scope of the present utility model and the scope of disclosure.

Claims (10)

1. The solar cell is characterized by comprising a silicon substrate, wherein a tunneling oxide layer which is discontinuously distributed is arranged on the back surface of the silicon substrate, the tunneling oxide layer is divided into a plurality of P regions and a plurality of N regions, and the P regions and the N regions are alternately arranged at intervals in sequence;

The P region is provided with a p+ doped layer, and the p+ doped layer comprises a p+ doped polycrystalline silicon carbide layer and a p+ doped polycrystalline silicon layer along the direction far away from the tunneling oxide layer;

A back passivation layer and a back antireflection layer are respectively arranged on the outer surface of the p+ doped polycrystalline silicon layer, the interval region between the P region and the N region and the outer surface of the n+ doped polycrystalline silicon carbide layer in a lamination manner along the direction far away from the silicon substrate;

The P region is provided with a first back metal electrode, one end of the first back metal electrode forms ohmic contact with the p+ doped polycrystalline silicon layer, the other end of the first back metal electrode extends out of the back anti-reflection layer on the P region, the N region is provided with a second back metal electrode, one end of the second back metal electrode forms ohmic contact with the n+ doped polycrystalline silicon carbide layer, and the other end of the second back metal electrode extends out of the back anti-reflection layer on the N region.

2. The solar cell of claim 1, wherein the silicon substrate is an n-type silicon wafer;

the resistivity of the n-type silicon wafer is 0.3-7Ω & cm.

3. The solar cell of claim 1, wherein the tunnel oxide layer comprises a silicon oxide layer;

The thickness of the tunneling oxide layer is 0.5-3nm.

4. The solar cell of claim 1, wherein the p+ doped polycrystalline silicon carbide layer is a p+ boron doped polycrystalline silicon carbide layer;

the thickness of the p+ doped polycrystalline silicon carbide layer is 30-100nm.

5. The solar cell of claim 1, wherein the p+ doped polysilicon layer is a p+ boron doped polysilicon layer;

the thickness of the p+ doped polysilicon layer is 50-200nm.

6. The solar cell of claim 1, wherein the n+ doped polycrystalline silicon carbide layer is an n+ phosphorus doped polycrystalline silicon carbide layer;

The thickness of the n+ doped polycrystalline silicon carbide layer is 30-100nm;

The width of the break between adjacent P and N regions is 10-60 μm.

7. The solar cell according to claim 1, wherein the front surface of the silicon substrate is of a suede structure, and a phosphorus-doped lightly doped layer, a front passivation layer and a front anti-reflection layer are sequentially arranged on the front surface along a direction away from the silicon substrate;

The back passivation layer and the front passivation layer each independently include a silicon oxide layer and/or an aluminum oxide layer;

The thickness of the back passivation layer and the front passivation layer are each independently 2-10nm.

8. The solar cell of claim 7, wherein the back side anti-reflection layer and the front side anti-reflection layer each independently comprise any one or a combination of at least two of a silicon nitride layer, a silicon oxynitride layer, or a silicon oxide layer;

The thickness of the back side antireflection layer and the front side antireflection layer are respectively and independently 60-150nm;

the first back metal electrode and the second back metal electrode each independently include a silver electrode and/or an aluminum electrode.

9. The solar cell of claim 7, wherein the diffusion sheet resistance of the phosphorus-diffused lightly doped layer is 200-500 Ω/sq;

the junction depth of the phosphorus-doped light-doped layer is 0.3-1.5 mu m.

10. A photovoltaic module comprising a solar cell according to any one of claims 1-9.