CN2631038Y - Integrated Circuit Package Assembly in Bare Die Form - Google Patents
Integrated Circuit Package Assembly in Bare Die Form Download PDFInfo
- Publication number
- CN2631038Y CN2631038Y CN03206602.3U CN03206602U CN2631038Y CN 2631038 Y CN2631038 Y CN 2631038Y CN 03206602 U CN03206602 U CN 03206602U CN 2631038 Y CN2631038 Y CN 2631038Y
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- Prior art keywords
- integrated circuit
- clubfoot
- circuit package
- crystalline form
- wafer
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- 201000011228 clubfoot Diseases 0.000 claims description 55
- 238000012856 packing Methods 0.000 claims description 52
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A bare die type integrated circuit package assembly. The utility model provides an integrated circuit package assembly with good surface bonding alignment effect, vertical high-density stacking and thin thickness, which comprises a chip, a metal lead frame and an insulating package colloid; the wafer is provided with a front surface and a corresponding back surface, wherein a plurality of electrode ends are formed on the front surface; the metal lead frame comprises a plurality of bent pins, and each bent pin forms an extension end; the insulating packaging colloid is combined with the chip and the bent pin; the packaging colloid is provided with a first surface and a second surface; the back surface of the chip is exposed on one of the first and second surfaces of the encapsulant to be in a bare die shape; the periphery of one of the first and second surfaces of the packaging colloid forms a plurality of spacing gap slots for accommodating and limiting the extending end of the bent pin.
Description
Technical field
The utility model belongs to the integrated circuit package assembling, particularly a kind of integrated circuit package assembling of naked crystalline form attitude.
Background technology
In traditional integrated circuit package assembling, commonly be electrically conducted medium as wafer in the package assembling with lead frame (lead frame), utilize lead frame to finish the integrated circuit package assembling except the requirement that should meet unidirectional surface combination, do not increasing under the external printed circuit board surface combination area state or under the condition, needing in the specific occasion can be vertically to piling up in conjunction with (stack mounting).
As shown in Figure 1, known with lead frame as connecting medium and can be vertically comprising positive 11 wafers 10 that form electrode tips 12, have lead frame, number metal bonding wire 40 and packing colloid 30 that several connect end 21 pins 20 in forming to the integrated circuit package assembling 1 that piles up combination.
Lead frame count pin 20 in connect the end 21 glutinous fronts 11 of being located at wafer 10; Number metal bonding wires 40 be electrically connected at the electrode tip 12 of wafer 10 and lead frame pin 20 in connect end 21, and form packing colloid 30 to connect end 21 in sealing wafer 10 and the lead frame pin 20 with pressing mold (molding), and make connect in the pin 20 end 21 have be revealed in packing colloid 30 first surfaces 31 with as first to surperficial contact point appear the surface 23, the elongated end 22 of pin 20 is to be extended and be bent into the J-shaped pin by packing colloid 30 first surfaces 31 sides, elongated end 22 is the second surface 32 that is formed at packing colloid 30, with as second to surperficial contact point.Therefore, several integrated circuit package assemblings 1 are can be vertically to piling up.Yet, the elongated end 22 of several pins 20 of lead frame is by packing colloid 30 unsettled stretching out, after shaping, any collision all may make the elongated end 22 of pin 20 crooked, causes surface engagement bad, so the thickness of pin 20 is enough thick, to alleviate crooked degree, so, relatedly make that integrated circuit package assembling 1 thickness is bigger, unsuitable high-density laminated.
Another kind of known integrated circuit package assembling, as United States Patent (USP) the 5th, it is exposed that 894, No. 108 patents have disclosed chip back surface, with the design of the thickness that reduces the overall package assembly, its wafer system is revealed in outside the packing colloid, but the steadiness of its pin is easy to come off, and only can makes unidirectional surface engagement be not as firm as the pin of aforementioned conventional structure, can't pile up utilization, the utilization field is limited.
Summary of the invention
The purpose of this utility model provide a kind of surface engagement contraposition effective, can be vertically to the integrated circuit package assembling of the naked crystalline form attitude of high-density laminated, thin thickness.
The utility model comprises wafer, metal lead wire frame and insulation-encapsulated colloid; Wafer has the positive and corresponding back side that forms several electrode tips; Metal lead wire frame comprises several clubfoots, and each clubfoot forms elongated end; The insulation-encapsulated colloid is in conjunction with wafer and clubfoot; Packing colloid has first surface and second surface; The surface that the back side of wafer system one of is revealed in first and second surface of packing colloid and be naked crystalline form attitude; Surface perimeter one of in first and second surface of packing colloid forms the spacing gap slot that several were installed with and limited the clubfoot elongated end.
Wherein:
Packing colloid is not more than 0.6cm by first surface to the thickness of second surface system.
Packing colloid is not more than 0.4cm by first surface to the thickness of second surface system.
The degree of depth of spacing gap slot is not more than the thickness of corresponding clubfoot elongated end.
Spacing gap slot is the opening expansion shape with oblique amplification sidewall.
Each clubfoot have corresponding elongated end in connect end, in connect the end have be revealed in the packing colloid first surface appear the surface.
Connect end in the clubfoot and have end so as to electrically conducting with the chip electrode end; End system be formed at in connect that end appears plane inequality, surface and complete packed colloid coats.
The end that connects end in the clubfoot is attached at built-in paster.
Be connected with several metal bonding wires between the end that connects end in the clubfoot and the electrode tip of wafer.
The chip electrode end is provided with conductive projection to electrically connect chip electrode end and clubfoot.
Because the utility model comprises wafer, metal lead wire frame and insulation-encapsulated colloid; Wafer has the positive and corresponding back side that forms several electrode tips; Metal lead wire frame comprises several clubfoots, and each clubfoot forms elongated end; The insulation-encapsulated colloid is in conjunction with wafer and clubfoot; Packing colloid has first surface and second surface; The surface that the back side of wafer system one of is revealed in first and second surface of packing colloid and be naked crystalline form attitude; Surface perimeter one of in first and second surface of packing colloid forms the spacing gap slot that several were installed with and limited the clubfoot elongated end.Appear and the spacing short slot mouth of packing colloid by chip back surface, make the clubfoot elongated end be installed with and be defined in the spacing short slot mouth of packing colloid, can constitute can be vertically to piling up and integral body is ultra-thin form, but under equal height high density vertically to the integrated circuit package assembling that piles up more a plurality of naked crystalline form attitudes; Not only the surface engagement contraposition is effective, and can be vertically to high-density laminated, thin thickness, thereby reaches the purpose of this utility model.
Description of drawings
Fig. 1, be known integrated circuit package assembling structural representation cutaway view.
Fig. 2, be the utility model embodiment one structural representation cutaway view.
Fig. 3, be the utility model embodiment one structural representation vertical view.
Fig. 4, be the utility model embodiment one structural representation upward view.
Fig. 5, be A portion partial enlarged drawing (demonstration gap slot) among Fig. 2.
Fig. 6, splice and close the user mode schematic diagram for several the utility model embodiment a pile.
Fig. 7, be the utility model embodiment one encapsulation process schematic diagram.
Fig. 8, be the utility model embodiment two structural representation cutaway views.
Embodiment
As Fig. 2, Fig. 3, shown in Figure 4, the integrated circuit package assembling 100 of the naked crystalline form attitude of the utility model comprises wafer 110, metal lead wire frame and insulation-encapsulated colloid 130.
Wafer 110 is to be selected from microprocessor, microcontroller, various memory body, Application Specific Integrated Circuit or image processing wafer, and wafer 110 has the front 111 and the corresponding back side 113 that forms the integrated circuit layout.Wafer 110 fronts 111 are to form several electrode tips (electrode) 112, and as the projection (bump) of plain cushion shape weld pad (bondingpad) or projection, the electrode tip 112 of wafer 110 is to be electrically conducted to lead frame.
Lead frame is the metal that copper, iron or alloy etc. have suitable ductility, it comprises several clubfoots 120, clubfoot 120 takes the shape of the letter U, each clubfoot 120 divide into be positioned at packing colloid 130 inside and outside connect end 121 and elongated end 122, in connect end 121 have be revealed in packing colloid 130 first surfaces 131 appear surface 123, in to connect end 121 be to electrically conduct to the electrode tip 112 of wafer 110 with its end 124.As Fig. 2, shown in Figure 3, preferable system utilizes metal bonding wires 140 such as several gold threads or aluminum steel to be connected in to connect in the clubfoot 120 between the electrode tip 112 of the end 124 of end 121 and wafer 110, end 124 be formed at in connect end 121 and appear 123 planes inequality, surface,, can the be complete packed colloid 130 in end 124 has preferable steadiness so that coating, in connect end 121 to appear the surface 123 be the first surface 131 that is revealed in packing colloid 130, can be for first to surface engagement; As Fig. 2, shown in Figure 4, the elongated end 122 of clubfoot 120 is second surface 132 peripheries that extended and be bent to packing colloid 130 by the side of packing colloid 130, for second to surface engagement.
As Fig. 5, shown in Figure 7, packing colloid 130 second surfaces 132 peripheries form several spacing gap slots 133 when pressing mold, be installed with and limit clubfoot 120 elongated ends 122 by spacing gap slot 133, to reach the accurately effect of contraposition surface engagement of clubfoot 120, more can reach vertical to high-density laminated utilization, therefore, can reduce clubfoot 120 needed structural strengths, thereby the thickness of lead frame can be reduced to about 0.127cm, and known J-shaped pin thickness requirement is 0.2cm, and the degree of depth of spacing gap slot 133 is preferable with the thickness that is not more than corresponding clubfoot 120 elongated ends 120.As shown in Figure 5, spacing gap slot 133 is the opening expansion shape with oblique amplification sidewall, when helping surface engagement, the 122 guiding contrapositions of clubfoot 120 elongated ends, that is to say, even the elongated end 122 of clubfoot 120 has a little deflection, when surface engagement (surface mounting), the elongated end 122 of clubfoot 120 can correctly be guided by oblique sidewall and be revised to spacing gap slot 133, under the design of clubfoot 120 dense arrangement, elongated end 122 width of clubfoot 120 should slightly be narrower than the width that connects end 121 in the clubfoot 120.
The integrated circuit package assembling 1 of the naked crystalline form attitude of the utility model appears by wafer 110 back sides 113 and the design of the clubfoot 120 that takes the shape of the letter U, can constitute can be vertically to piling up and integral body is ultra-thin form.
As shown in Figure 7, the utility model is in manufacture process, wafer 110 back sides 113 are attached on the externally positioned type adhesive tape (external tape) 150 with lead frame system, after electrically connecting wafer 110 and lead frame, insert stamper mould in the lump together with externally positioned type adhesive tape 150, spacing gap slot 133 is shaped when forming packing colloid 130, after tearing off externally positioned type adhesive tape 150, just the elongated end 122 of lead frame clubfoot 120 can be bent in the spacing gap slot 133 of packing colloid 130, and the elongated end 122 that makes clubfoot 120 with the second surface 132 of contact packing colloid 130 for preferable.
Embodiment two
As shown in Figure 8, the integrated circuit package assembling 200 of the naked crystalline form attitude of the utility model comprises wafer 210, metal lead wire frame and insulation-encapsulated colloid 230.
Wafer 210 is to be selected from microprocessor, microcontroller, various memory body, Application Specific Integrated Circuit or image processing wafer, and wafer 210 has the front 211 and the corresponding back side 213 that forms the integrated circuit layout.Wafer 210 fronts 211 are to form several electrode tips (electrode) 212.
Packing colloid 230 is to be formed with pressing mold (molding) technology by thermoset insulating resin, and packing colloid 230 cordings have first surface 231 and second surface 232.
Lead frame is the metal that copper, iron or alloy etc. have suitable ductility, and it comprises several clubfoots 220, and clubfoot 220 takes the shape of the letter U, each clubfoot 220 divide into be positioned at packing colloid 230 inside and outside connect end 221 and elongated end 222.Preferably connecing end in the clubfoot 220 221 is to be pasted with built-in paster (internal tape) 242, connect in the clubfoot 220 end 221 have manifest packing colloid 230 second surfaces 232 appear surface 223; The elongated end 222 of clubfoot 220 is the spacing gap slot 233 that is extended and be bent to first surface 231 peripheries of packing colloid 230 by the side of packing colloid 230.
The back side 213 of wafer 210 is to be revealed in the first surface 231 of packing colloid 230 and to be naked crystalline form attitude; Connecing end 221 in the clubfoot 220, to appear the surface 223 be to be formed at packing colloid 230 second surfaces 232 peripheries, and the elongated end 222 of clubfoot 220 is to be bent to packing colloid 230 first surfaces 231 peripheries.Connect end 221 end 224 in the clubfoot 220 and be formed at in connect end 221 and appear planes inequality, surface 223; Wafer 210 electrode tips 212 utilize cover crystalline substance (flip chip) or in draw finger (the inner lead bonding) technology of closing and electrically connect with the end 224 that connects end 221 in conductive projection (bump) 241 and the lead frame clubfoot 220.
Claims (10)
1, a kind of integrated circuit package assembling of naked crystalline form attitude, it comprises wafer, metal lead wire frame and insulation-encapsulated colloid; Wafer has the positive and corresponding back side that forms several electrode tips; Metal lead wire frame comprises several clubfoots, and each clubfoot forms elongated end; The insulation-encapsulated colloid is in conjunction with wafer and clubfoot; Packing colloid has first surface and second surface; The surface that the back side system that it is characterized in that described wafer one of is revealed in first and second surface of packing colloid and be naked crystalline form attitude; Surface perimeter one of in first and second surface of packing colloid forms the spacing gap slot that several were installed with and limited the clubfoot elongated end.
2, the integrated circuit package assembling of naked crystalline form attitude according to claim 1 is characterized in that described packing colloid is not more than 0.6cm by first surface to the thickness of second surface system.
3, the integrated circuit package assembling of naked crystalline form attitude according to claim 1 is characterized in that described packing colloid is not more than 0.4cm by first surface to the thickness of second surface system.
4, the integrated circuit package assembling of naked crystalline form attitude according to claim 1 is characterized in that the degree of depth of described spacing gap slot is not more than the thickness of corresponding clubfoot elongated end.
5, the integrated circuit package assembling of naked crystalline form attitude according to claim 1 is characterized in that described spacing gap slot is the opening expansion shape with oblique amplification sidewall.
6, the integrated circuit package assembling of naked crystalline form attitude according to claim 1, it is characterized in that described each clubfoot have corresponding elongated end in connect end, in connect the end have be revealed in the packing colloid first surface appear the surface.
7, the integrated circuit package assembling of naked crystalline form attitude according to claim 6 is characterized in that connecing in the described clubfoot end and has end so as to electrically conducting with the chip electrode end; End system be formed at in connect that end appears plane inequality, surface and complete packed colloid coats.
8, the integrated circuit package assembling of naked crystalline form attitude according to claim 7 is characterized in that the end that connects end in the described clubfoot is attached at built-in paster.
9,, be connected with several metal bonding wires between the end that it is characterized in that connecing in the described clubfoot end and the electrode tip of wafer according to the integrated circuit package assembling of claim 1 or 7 described naked crystalline form attitudes.
10, the integrated circuit package assembling of naked crystalline form attitude according to claim 1 is characterized in that described chip electrode end is provided with conductive projection to electrically connect chip electrode end and clubfoot.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN03206602.3U CN2631038Y (en) | 2003-07-29 | 2003-07-29 | Integrated Circuit Package Assembly in Bare Die Form |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN03206602.3U CN2631038Y (en) | 2003-07-29 | 2003-07-29 | Integrated Circuit Package Assembly in Bare Die Form |
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| Publication Number | Publication Date |
|---|---|
| CN2631038Y true CN2631038Y (en) | 2004-08-04 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN03206602.3U Expired - Lifetime CN2631038Y (en) | 2003-07-29 | 2003-07-29 | Integrated Circuit Package Assembly in Bare Die Form |
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| CN (1) | CN2631038Y (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101449375B (en) * | 2006-06-29 | 2012-01-18 | 英特尔公司 | Apparatus, system and method for wireless connection in integrated circuit package |
| CN101755336B (en) * | 2007-07-24 | 2013-08-28 | 美光科技公司 | Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods |
-
2003
- 2003-07-29 CN CN03206602.3U patent/CN2631038Y/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101449375B (en) * | 2006-06-29 | 2012-01-18 | 英特尔公司 | Apparatus, system and method for wireless connection in integrated circuit package |
| CN101755336B (en) * | 2007-07-24 | 2013-08-28 | 美光科技公司 | Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods |
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