CN2710107Y - Magnetoresistive random access memory circuit - Google Patents

Abstract

A magnetoresistive random access memory circuit comprising the following components: the magnetic resistance type memory unit is provided with a fixed magnetic axis layer, a free magnetic axis layer and an insulating layer arranged between the fixed magnetic axis layer and the free magnetic axis layer. The first switch device is coupled to one end of the fixed magnetic axis layer and is provided with a first control gate. The second switching device is coupled to the free magnetic axis layer and has a second control gate. The bit line is coupled to the second switch device for providing a read current during a read operation. The first programming line is coupled to the other end of the fixed magnetic axis layer for providing a programming current when performing a programming operation. The second programming line is coupled to the first switching device. The word line is coupled to the first control gate and the second control gate for providing an enable signal to turn on the first switch device and the second switch device.

Description

Magnetoresistive random access memory circuit

technical field

The utility model relates to a storage array, in particular to a storage array of a magnetoresistive random access memory.

Background technique

Magneto-resistive random access memory (Magnetic Random Access Memory, hereinafter referred to as MRAM) is a metal magnetic material, its radiation resistance is much higher than that of semiconductor materials, and it belongs to non-volatile random access memory (Non-volatile Random Access Memory) , when the computer is powered off or shut down, it can still maintain storage.

MRAM uses magnetoresistance characteristics to store and record information, and has the characteristics of low energy consumption, non-volatility, and no limit on the number of reads and writes. The basic principle of its operation is the same as storing data on a hard disk. The data is stored as 0 or 1 based on the magnetic direction. The stored data is permanent and will not change the magnetic data until it is affected by an external magnetic field.

Figure 1 is an architectural diagram showing a conventional MRAM array. The tops of MRAM cells 10A and 10B are coupled to bit line B _n , while the bottoms are coupled to electrode 12 . The gates of the transistors 14 are coupled to the word lines (W _m , W _m+1 ), the sources are grounded, and the drains are respectively coupled to the corresponding electrodes 12 . There is an insulating layer 13 between the data lines ( 16A, 16B) for writing data and the electrodes 12 for isolating the data lines 16A, 16B and the electrodes 12 .

2A and 2B are detailed structural diagrams showing the MRAM cell 10 . Current can flow vertically from a free magnetic axis layer 102 through an insulating layer (tunnel junction) 104 to (or pass through) the fixed magnetic axis layer 106 . The magnetic axis direction of the free magnetic axis layer 102 can be changed by the influence of other magnetic fields, while the magnetic axis direction of the fixed magnetic axis layer 106 is fixed, and the magnetic axis directions are shown as 108A and 108B in FIGS. 2A and 2B respectively. When the magnetic axis directions of the free magnetic axis layer 102 and the fixed magnetic axis layer 106 are in the same direction (as shown in FIG. When they are in different directions, the MRAM cell will have the characteristic of high resistance. Referring to FIG. 1 , the direction of the magnetic axis of the free magnetic axis layer 102 is changed by the magnetic field generated by the data lines 16A, 16B combined with the magnetic field generated by the bit lines.

The spin reversal magnetic field of each MRAM cell is jointly synthesized by the current magnetic field flowing through the bit line _Bn and the data line. Through this operation, only the magnetic axes of the selected MRAM cells will be reversed, and the recording operation can be performed smoothly. As for the unselected memory cells, only one of the bit line or the data line will be applied with a current magnetic field, so a sufficient inversion magnetic field cannot be formed, so the information writing operation cannot be performed.

The magnetic fields generated by the currents of the above-mentioned bit lines and data lines must be precisely designed to enable the MRAM array to perform programming operations normally. Referring to FIG. 3 , FIG. 3 is a graph showing the relationship between the magnetic field provided by the bit line and the data line and the switching condition of the MRAM. The transverse magnetic field H _t is provided by the current of the bit line, and the longitudinal magnetic field H ₁ is provided by the current of the data line, and in the absence of the transverse magnetic field H _t , when the longitudinal magnetic field H ₁ is H ₀ , it will cause The MRAM cell switches its conduction level. If there is a transverse magnetic field H _t , the critical value for switching the MRAM cell will be reduced. Therefore, applying a longitudinal magnetic field H ₁ smaller than H ₀ can make the MRAM cell switch its conduction state.

In the region A formed by the dotted line, the MRAM cell is in the first conduction state (take high impedance as an example), and in the part outside the region A, the MRAM cell will be switched to another conduction state (taken as high impedance) under the influence of the magnetic field low impedance as an example).

When reading MRAM data, take the MRAM unit 10A as an example, the word line Wm turns on the transistor 14 at this time, and according to the conduction state of the MRAM unit 10A, it can be determined whether the current provided by the bit line _Bn can pass through the MRAM The cell 10A and the transistor 14 flow to the ground point, so as to read the data stored in the MRAM cell 10A.

In the writing step, since the magnitude of the magnetic field is inversely proportional to the center distance of the cross-section of the current, under the structure of the traditional MRAM array, if there is a programming current on the data line 16A, the magnetic field generated by the data line 16A can not only change the MRAM cell 10A On state, located in the MRAM array, parallel to the data line 16A and the entire row of MRAM cells where the MRAM cell 10A is located, the magnetic axis direction will also be affected by the magnetic field generated by the data line 16A, even the MRAM cell 10B located in another row It will also be affected, therefore, the magnetic field supplied by the data line 16A should not be too large.

In addition, when the magnetic field supplied by the data line 16A is too small, the conduction state of the MRAM unit 10A cannot be switched. Therefore, the currents of the bit lines and the data lines of the traditional MRAM array must be precisely designed to enable the MRAM array to perform programming operations normally.

That is, if the magnetic field supplied by the data line 16A is too large, although the MRAM cell 10A can write data, other MRAM cells may also be written with data, resulting in programming disturbance. And when the magnetic field supplied by the data line 16A is too small, the effect of writing data to a specific MRAM unit cannot be achieved.

However, if the currents of the bit lines and data lines must be controlled so accurately, when there is external magnetic field interference, or the external environment changes (such as temperature, humidity, etc.), it will inevitably cause programming errors, which shows that the traditional method requires precise control. The MRAM architecture of programming current has the disadvantage of poor reliability.

Therefore, Taiwan Semiconductor Manufacturing Company proposes a magnetoresistive random access memory circuit to overcome the above disadvantages. FIG. 4 is a schematic diagram showing the architecture of a magnetoresistive random access memory cell (MRAM cell) proposed by Taiwan Semiconductor Manufacturing Company.

The free magnetic axis layers of the MRAM cells 40A and 40B are electrically connected to the bit line _Bn arranged in a predetermined direction, and the fixed magnetic axis layers of the MRAM cells 40A and 40B are electrically connected to the data lines 42A and 42B, respectively. Since the distance between the free magnetic axis layer and the data line is only a few angstroms (in the range of about 8-15 angstroms), a large magnetic field can be received. Therefore, compared with the conventional technology, only a small amount of programming current I _W is needed to change the direction of the magnetic axis of the free magnetic axis layer 102 , thus achieving the effect of power saving. In addition, referring to FIG. 4 , the distance between the data line 42A and the MRAM unit 40A is much smaller than the distance between the data line 42A and the MRAM unit 40B, so the influence of the data line 42A on the MRAM unit 40A is much greater than the influence on the MRAM unit 40B, so it will not change the adjacent The impedance of the MRAM cell 40B causes programming errors.

FIG. 5 is a structural diagram showing a magnetoresistive random access memory array (MRAM) circuit as shown in FIG. 4 . In FIG. 5 , in order to simplify the diagram, the data lines are not shown. In fact, the data lines and the fixed magnetic axis layer of the MRAM unit can be regarded as one.

When data is to be written into the MRAM cell 50 , the peripheral circuits of the memory array select the word line W _m , float the bit line B _n , and supply the programming current I _W from the programming line PL. Since the word line W _m is at a high level at this time, the transistors 52A and 52B are turned on, so the programming current I _W flows through the MRAM unit 50 to change the conduction state of the MRAM unit 50 to achieve the purpose of writing data.

When the data stored in the MRAM unit 50 is to be read, the peripheral circuit selects the word line _Wm to which the MRAM unit 50 belongs, and the programming line PL, PL is grounded, and at this time, the read current _Ir is provided on the bit line _Bn to make It flows to the grounded programming lines PL, PL through the MRAM unit 50 and the turned-on transistors 52A, 52B, and then the data stored in the MRAM unit 50 is obtained according to the voltage value detected on the bit line Bn.

However, when the programming operation is performed in the above circuit, the programming current must flow through the transistors 52A and 52B. Since the programming current is quite large, the area of the transistors 52A and 52B must be increased to withstand a large amount of programming current. However, this will increase the size of the entire storage array, making the development of reducing the size of the MRAM storage array encounter a technical bottleneck.

Contents of the invention

In view of this, in order to solve the above problems, the main purpose of the present invention is to provide a magnetoresistive random access memory array circuit, which can effectively reduce the size of the current MRAM memory array.

In order to achieve the above purpose, the utility model proposes a magnetoresistive random access memory circuit, which includes the following components. The magnetoresistive memory unit has a fixed magnetic axis layer, a free magnetic axis layer, and an insulating layer arranged between the fixed magnetic axis layer and the free magnetic axis layer. The first switch device is coupled to one end of the fixed magnetic axis layer and has a first control gate. The second switch device is coupled to the free magnetic axis layer and has a second control gate. The bit line is coupled to the second switch device for providing a read current during a read operation. The first programming line is coupled to the other end of the fixed magnetic axis layer, and is used for providing a programming current when performing a programming operation. The second programming line is coupled to the first switch device. The word line is coupled to the first control gate and the second control gate for providing an enable signal to turn on the first switch device and the second switch device.

In addition, the utility model proposes a magnetoresistive random access memory circuit, which includes the following components. The magnetoresistive memory unit has a fixed magnetic axis layer, a free magnetic axis layer, and an insulating layer arranged between the fixed magnetic axis layer and the free magnetic axis layer. The first operation line is coupled to one end of the fixed magnetic axis layer, and is used for providing a read current during a read operation and a programming current during a program. The first switch device is coupled to the free magnetic axis layer and has a first control gate. The second switch device is coupled to the other end of the fixed magnetic axis layer and has a second control gate. The first selection line is coupled to the first control gate for providing a first selection signal. The second selection line is coupled to the second control gate for providing a second selection signal. The second operating line is coupled to the first switch device and the second switch device.

In addition, the utility model proposes a magnetoresistive random access memory circuit, which includes the following components. A plurality of magnetoresistive memory units have a fixed magnetic axis layer, a free magnetic axis layer, and an insulating layer arranged between the fixed magnetic axis layer and the free magnetic axis layer. The first operation line is coupled to one end of the fixed magnetic axis layer, and is used for providing a read current during a read operation and a programming current during a program. A plurality of word lines, coupled to the free magnetic axis layer, are used for providing a read current during a read operation. A plurality of first switching devices are coupled to two ends of a fixed magnetic axis layer of a magnetoresistive memory unit. The plurality of second switch devices are coupled to two ends of the fixed magnetic axis layer of another magnetoresistive memory unit. A plurality of programming lines are coupled between the first switch device and the second switch device. The first word line is coupled to the first switch device. And the second word line is coupled to the above-mentioned second switch device.

Description of drawings

Figure 1 is a diagram showing the architecture of a conventional MRAM array.

2A and 2B are detailed structural diagrams showing the MRAM cell 10 .

FIG. 3 is a graph showing the relationship between the magnetic field provided by the bit line and the data line and the switching condition of the MRAM.

FIG. 4 is a schematic diagram showing the architecture of another conventional magnetoresistive random access memory cell (MRAM cell).

FIG. 5 is a structural diagram showing a magnetoresistive random access memory array (MRAM) circuit as shown in FIG. 4 .

FIG. 6 is a structural diagram showing a magnetoresistive random access memory (MRAM) unit according to an embodiment of the present invention.

FIG. 7 is a structural diagram showing a magnetoresistive random access memory array (MRAM) circuit according to the first embodiment of the present invention.

FIG. 8 is a structural diagram showing a magnetoresistive random access memory array (MRAM) circuit according to a second embodiment of the present invention.

FIG. 9 is a structural diagram showing a magnetoresistive random access memory array (MRAM) circuit according to a third embodiment of the present invention.

Symbol Description:

10A, 10B, 40A, 40B, 50, 60, 70A, 70B, 80A, 80B, 90A, 90B: MRAM cells;

12: electrode; 13, 104: insulating layer;

14, 52A, 52B, 62, 64, 72A, 72B, 74A, 74B, 82A, 82B, 84A, 84B, 92A, 92B, 94A, 94B: transistors;

16A, 16B, 42A, 42B: data line;

102, 106: electromagnetic layer;

108A, 108B: labels;

A: area;

B _n , B1～B4: bit lines, operation lines;

H _t : transverse magnetic field;

H ₁ , H ₀ : longitudinal magnetic field;

I _W : programming current; I _r : reading current;

PL, PL, P1~P4: programming line;

W _m , W1~W3, W1~W3: character line, selection line.

Detailed ways

Referring to FIG. 6 , FIG. 6 is a structural diagram showing a magnetoresistive random access memory (MRAM) unit according to an embodiment of the present invention. The MRAM unit 60 comprises a fixed magnetic axis layer 106, a free magnetic axis layer 102, and an insulating layer (magnetictunneling junction) 104 arranged between the fixed magnetic axis layer 106 and the free magnetic axis layer 102, the magnetoresistance (magneto- resistance) is determined by the directions of the magnetic axes of the fixed magnetic axis layer 106 and the free magnetic axis layer 102 . When the magnetic axis directions of the free magnetic axis layer 102 and the fixed magnetic axis layer 106 are in the same direction, the MRAM unit will have low resistance, and when the free magnetic axis layer 102 and the fixed magnetic axis layer 106 are in different directions, then the MRAM The cell will then have the characteristic of having high resistance.

The NMOS transistor 62 is coupled to the free magnetic axis layer 102 for controlling the read current _Ir to flow through the MRAM unit 60 during the read operation. The NMOS transistor 64 is coupled to the fixed magnetic axis layer 106 for controlling the programming current _Iw provided by the programming line PL to flow through the MRAM cell 60 during the programming operation. Here, the size of the NMOS transistor 62 is smaller than that of the NMOS transistor 64 because the programming current _Iw is much larger than the reading current _Ir , about two times to two hundred times. Compared with the conventional technology, referring to FIG. 4 and FIG. 5 , the transistors 52A and 52B are both disposed on the current path of the programming current _Iw , so the required size of the conventional technology is larger. Therefore, the MRAM unit design according to the embodiment of the present invention can effectively reduce the size of the MRAM array.

The design of the magnetoresistive random access memory array and peripheral circuits according to the embodiment of the present invention will be introduced below.

first embodiment

FIG. 7 is a structural diagram showing a magnetoresistive random access memory array (MRAM) circuit according to the first embodiment of the present invention. Wherein, W1-W3 and W1-W3 are word lines, P1-P4 are programming lines, and B1-B4 are bit lines.

The sources of the NMOS transistors 72A and 72B are respectively coupled to the free magnetic axis layer 102 of the magnetoresistive memory cells 70A and 70B, their gates are respectively coupled to the word lines W2 and W2, and their drains are respectively coupled to the bit Lines B3 and B2. In addition, the drains of the NMOS transistors 74A and 74B are respectively coupled to the fixed magnetic axis layer 106 of the magnetoresistive memory cells 70A and 70B, their gates are also respectively coupled to the word lines W2 and W2, and their sources are respectively coupled to Connect to programming lines P3 and P4. The programming lines P2 and P3 are respectively coupled to the fixed magnetic axis layer 106 of the magnetoresistive memory cells 70A and 70B.

When data is to be written into the MRAM cell 70A, the word line W2 is selected to turn on the NMOS transistor 74A, and the programming current _Iw is provided from the programming line P3 and the programming line P4 is grounded. Therefore, the programming current _Iw flows through the fixed magnetic axis layer 106 of the MRAM cell 70A, and flows to the ground point through the NMOS transistor 74A and the programming line P4. When the programming current _Iw flows through the MRAM unit 70A, the magnetic field generated by it will change the conduction state of the MRAM unit 70A to achieve the purpose of writing data. It should be particularly noted that since the impedance encountered when the programming current _Iw flows through the MRAM cell is much higher than that directly flowing into the ground point through the fixed magnetic axis layer 106 and the NMOS transistor 74A, most of the programming current _Iw Both flow into the ground through the fixed magnetic axis layer 106 and the NMOS transistor 74A.

When the data stored in the MRAM unit 70A is to be read, the word line W2 is selected to turn on the NMOS transistor 72A and the NMOS transistor 74A, and the read current _Ir provided by the bit line B3 flows to the connected terminal via the MRAM unit 70A. The location, and other lines are all grounded, and the data currently stored in the MRAM unit 70A can be obtained according to the detected voltage of the bit line B3.

second embodiment

FIG. 8 is a structural diagram showing a magnetoresistive random access memory array (MRAM) circuit according to a second embodiment of the present invention. Wherein, W1-W2 and W1-W2 are selection lines, and B1-B2 and B1-B2 are operation lines.

The drains of the NMOS transistors 82A and 82B are respectively coupled to the free magnetic axis layer 102 of the magnetoresistive memory cells 80A and 80B, the gates of which are both coupled to the selection line W2, and the sources are respectively coupled to the operating lines B2 and 80B. B1. In addition, the drains of the NMOS transistors 84A and 84B are respectively coupled to the fixed magnetic axis layer 106 of the magnetoresistive memory cells 80A and 80B, the gates of which are both coupled to the selection line W2, and the sources are also respectively coupled to the operation Line B2 and B1. The operation lines B1 and B2 are respectively coupled to the fixed magnetic axis layer 106 of the magnetoresistive memory cells 80A and 80B.

When data is to be written into the MRAM cell 80A, the selection line W2 is selected to turn on the NMOS transistor 84A, and the operation line B2 provides the programming current _Iw and grounds the operation line B2. Therefore, the programming current _Iw flows through the fixed magnetic axis layer 106 of the MRAM cell 80A, and flows to the ground point through the NMOS transistor 84A and the operation line B2. When the programming current _Iw flows through the MRAM unit 80A, the magnetic field generated by it will change the conduction state of the MRAM unit 80A to achieve the purpose of writing data.

When the data stored in the MRAM unit 80A is to be read, the selection line W2 is selected to turn on the NMOS transistor 82A, and the read current _Ir provided by the operation line B2 flows to the connected terminal via the MRAM unit 80A and the NMOS transistor 82A. location, and according to the detected voltage of the operating line B2, the data currently stored in the MRAM unit 80A can be obtained.

third embodiment

FIG. 9 is a structural diagram showing a magnetoresistive random access memory array (MRAM) circuit according to a third embodiment of the present invention. Wherein, W1-W2 and W1-W2 are word lines, P1-P3 are programming lines, and B1-B2 are bit lines.

The sources of the NMOS transistors 92A and 94A are respectively coupled to the fixed magnetic axis layers of the magnetoresistive memory cells 90A and 90B, their gates are respectively coupled to the word lines W1 and W1, and their drains are respectively coupled to the programming line P1. with P2. In addition, the drains of the NMOS transistors 92B and 94B are respectively coupled to the fixed magnetic axis layers of the magnetoresistive memory cells 90A and 90B, their gates are also respectively coupled to the word lines W1 and W1, and their sources are respectively coupled to to programming lines P2 and P3. Here, the bit lines B1 and B2 are respectively coupled to the free magnetic axis layers of the magnetoresistive memory cells 90A and 90B, and the programming line P2 is coupled to the connection point of the NMOS transistors 92B and 94A.

The word lines W1 and W1 are respectively used to control the on and off of the NMOS transistors 92A and 92B and the NMOS transistors 94A and 94B. Compared with the conventional technology shown in FIG. 4 , the MRAM array circuit according to the third embodiment of the present invention uses a smaller number of programming lines and increases word lines. Since the programming lines and the NMOS transistors need to be contacted through contact windows, however, since the contact windows require a larger area, the area of the entire memory array increases due to a large number of contact windows. In this embodiment, different word lines are used to control the memory cells of the same row (column). Since the word lines do not require the design of contact windows, they have less impact on the volume of the entire memory array compared to the programming lines. Therefore, the area of the storage array is effectively reduced.

When data is to be written into the MRAM cell 90B, the peripheral circuits of the memory array select the word line W1 and float the bit line B2, and the programming current I _W is supplied from the programming line P2. Since the word line W1 is at a high level at this time, the transistors 94A and 94B are turned on, so the programming current _IW flows through the MRAM unit 90B to change the conduction state of the MRAM unit 90B to achieve the purpose of writing data.

When the data stored in the MRAM unit 90B is to be read, the peripheral circuit selects the word line W1 to which the MRAM unit 90B belongs, and the programming lines P1 and P3 are grounded. At this time, the read current _Ir is provided on the bit line B2 to pass through The MRAM unit 90B and the turned-on transistors 94A, 94B flow to the grounded programming lines P2, P3, and then the data stored in the MRAM unit 90B is obtained according to the voltage value detected on the bit line B2.

In addition, according to the magnetoresistive random access memory array circuits described in the first embodiment, the second embodiment and the third embodiment of the present invention, the switches used are not limited to NMOS transistors, if the circuit is changed to The level of the turn-on switch signal can also use a PMOS transistor as a switch, which cannot be used to limit the scope of the present invention.

To sum up, according to the magnetoresistive random access memory array circuit described in the present invention, in the first embodiment and the second embodiment, it is possible to use smaller-sized switch components according to the actual needs of the circuit, and In the third embodiment, the programming lines which occupy a relatively large area are replaced by adding word lines which require a relatively small area. The circuits disclosed in the above embodiments can effectively reduce the size of the current MRAM storage array.

Claims (20)

1. A magnetoresistive random access memory circuit, characterized in that it comprises: A magnetoresistive memory unit has a fixed magnetic axis layer, a free magnetic axis layer, and an insulating layer arranged between the fixed magnetic axis layer and the free magnetic axis layer. The magnetoresistive memory unit has a first conductive pass status; A first switch device, coupled to one end of the fixed magnetic axis layer, and has a first control gate; A second switch device, coupled to the above-mentioned free magnetic axis layer, and has a second control gate; a bit line, coupled to the second switch device, for providing a read current during a read operation; A first programming line, coupled to the other end of the fixed magnetic axis layer, for providing a programming current when performing a programming action; a second programming line coupled to the first switching device; and A word line, coupled to the first control gate and the second control gate, is used to provide an enable signal to turn on the first switch device and the second switch device. 2. The magnetoresistive random access memory circuit according to claim 1, characterized in that: when performing a programming operation, the second programming line is grounded, and the enabling signal turns on the first switching device and the second switching device. Two switching devices, so that the programming current flows to the second programming line through the fixed magnetic axis layer and the second switching device, and the magnetic field generated when the programming current flows through the fixed magnetic axis layer changes the free magnetic axis layer The direction of the magnetic axis makes the conduction state of the magnetoresistive memory unit change from the first conduction state to a second conduction state. 3. The magnetoresistive random access memory circuit according to claim 1, characterized in that: when performing a read operation, the first programming line and the second programming line are grounded, and the enabling signal turns on the The first switching device and the second switching device make the read current flow to the first programming line and the second programming line through the second switching device, the magnetoresistive memory unit and the first switching device, and according to the bit The voltage level of the element line reads the data stored in the magnetoresistive memory unit. 4. The magnetoresistive random access memory circuit according to claim 1, wherein the programming current is twice to two hundred times the reading current. 5. The MRRAM circuit as claimed in claim 1, wherein a size of the first switching device is larger than a size of the second switching device. 6. The magnetoresistive random access memory circuit according to claim 1, wherein the first conduction state is a high impedance state. 7. The magnetoresistive random access memory circuit according to claim 6, wherein the second conduction state is a low impedance state. 8. The magnetoresistive random access memory circuit according to claim 1, wherein the first switching device and the second switching device are transistors. 9. The magnetoresistive random access memory circuit according to claim 8, wherein the first switching device and the second switching device are NMOS transistors. 10. The magnetoresistive random access memory circuit according to claim 8, wherein the first switching device and the second switching device are PMOS transistors. 11. A magnetoresistive random access memory circuit comprising: A magnetoresistive memory unit has a fixed magnetic axis layer, a free magnetic axis layer, and an insulating layer arranged between the fixed magnetic axis layer and the free magnetic axis layer. The magnetoresistive memory unit has a first conductive pass status; A first operating line, coupled to one end of the fixed magnetic axis layer, for providing a reading current during a reading operation and a programming current during programming; A first switch device, coupled to the above-mentioned free magnetic axis layer, and has a first control gate; A second switch device, coupled to the other end of the fixed magnetic axis layer, and has a second control gate; a first selection line, coupled to the first control gate, for providing a first selection signal; a second selection line, coupled to the second control gate, for providing a second selection signal; and A second operating line is coupled to the first switch device and the second switch device. 12. The magnetoresistive random access memory circuit according to claim 11, characterized in that: when performing a programming operation, the second operation line is grounded, and the second selection signal turns on the second switch device, making the programming current flow to the second operating line through the fixed magnetic axis layer and the second switch device, and the magnetic field generated when the programming current flows through the fixed magnetic axis layer changes the direction of the magnetic axis of the free magnetic axis layer , so that the conduction state of the magnetoresistive memory unit is changed from the first conduction state to a second conduction state. 13. The magnetoresistive random access memory circuit according to claim 11, characterized in that: when performing a read operation, the second operating line is grounded, and the first selection signal turns on the first switching device making the read current flow to the second operating line via the magnetoresistive memory unit and the first switch device, and reading data stored in the magnetoresistive memory unit according to the voltage level of the first operating line . 14. The magnetoresistive random access memory circuit according to claim 11, wherein the programming current is twice to two hundred times the reading current. 15. The MRRAM circuit as claimed in claim 11, wherein the size of the first switching device is smaller than that of the second switching device. 16. The magnetoresistive random access memory circuit according to claim 11, wherein the first conduction state is a high impedance state. 17. The magnetoresistive random access memory circuit according to claim 16, wherein the second conduction state is a low impedance state. 18. The magnetoresistive random access memory circuit according to claim 11, wherein the first switching device and the second switching device are transistors. 19. A magnetoresistive random access memory circuit comprising: A first magnetoresistive memory unit having a first fixed magnetic axis layer, a first free magnetic axis layer, and a first insulating layer disposed between the first fixed magnetic axis layer and the first free magnetic axis layer ; a first bit line, coupled to the first free magnetic axis layer, for providing a read current during a read operation; A first switch device, coupled to one end of the first fixed magnetic axis layer, and having a first control gate; A second switch device, coupled to the other end of the first fixed magnetic axis layer, and has a second control gate; a first programming line, coupled to the first switching device, for providing a programming current when executing a programming action; A second magnetoresistive memory unit, having a second fixed magnetic axis layer, a second free magnetic axis layer, and a second insulating layer disposed between the second fixed magnetic axis layer and the second free magnetic axis layer ; A second bit line, coupled to the second free magnetic axis layer, for providing a read current during a read operation; A third switch device, coupled to one end of the second fixed magnetic axis layer, and has a third control gate; A fourth switch device, coupled to the other end of the second fixed magnetic axis layer, and has a fourth control gate; a second programming line, coupled to the second switch device and the third switch device; a third programming line coupled to the fourth switching device; a first word line, coupled to the first control gate and the second control gate, for providing an enabling signal to turn on the first switching device and the second switching device; and A second word line, coupled to the third control gate and the fourth control gate, is used to provide the enabling signal to turn on the third switching device and the fourth switching device. 20. The MRRAM circuit according to claim 19, wherein the first switching device, the second switching device, the third switching device and the fourth switching device are transistors.

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