DE10010456B4 - Device for reference voltage generation in ferroelectric memories - Google Patents

Abstract

ferroelectric Memory arrangement in which crossing each other at the ferroelectric memory cells Bit and word lines (CLT, BLC and WLT, WLC) and patch lines PL are provided and acted upon by logic "0" and logic "1" Reference cells at the end of the word line (WLT, WLC), to which also the ferroelectric memory cells are connected along a Reference bit line (BLTREF, BLCREF) are arranged, characterized the ferroelectric memory arrangement has a "selective read" memory forms, where a "pulsed plate "(PL) is arranged parallel to the bit line (BL), wherein per Plateleitung (PL) eight bit lines (BLT, BLC) and two reference bit lines provided and per reference bit line a reference cell (R1T, R2T and R1C and R2C) each for a logical "0" and a logical "1" with the true wordline (WLT) and the complementary Word line (WLC) are coupled.

Description

This invention relates to a ferroelectric memory device in which bit and word lines and platelet lines crossing each other at the ferroelectric memory cells are provided, and logic cells "0" and logic "1" are applied at the end of the word line to which the ferroelectric memory cells are also connected a reference bit line for generating a reference voltage are arranged. Such a ferroelectric memory device is known from the DE 199 21 259 A1 known.

In order to read out the stored information during storage and to evaluate its information content, a reference voltage is required in addition to the actual signal. In the case of DRAM memory chips, the reference voltage results automatically from the bit line BL pre-charged to a center voltage VBLEQ. This fact is in the impulse diagrams of the enclosed 1A and 1B each represented for a logical "1" and a logical "0".

at By contrast, ferroelectric memories cause both a logical "0" and a logic "1" of the information signal to increase the bit line voltage, so that the reference level for the Reading used differential amplifier must be generated.

The pulse timing diagrams of the enclosed 2A and 2 B respectively illustrate the ratios for a logical "0" and a logical "1" on the bitline. The reference voltage U _{Ref to} be generated must be generated so that it lies approximately in the middle between the voltage levels for the logical "0" and the logic "1".

Known solutions are in "1999 Symposium on VLSI Circuits ", Page 97, ff, in which a) the reference voltage either via a external voltage source is fed or b) via a few of dummy cells is generated at the end of the bit line.

The solutions proposed in the prior art have the following disadvantages:
A voltage generator behaves differently in the case of technological fluctuations than memory cells and thus can not achieve the optimum voltage.

Reference or dummy cells on the bit line can age differently than the actual memory cells due to a large number of accesses. In the worst case, it may happen that the reference or dummy cell 10 is accessed ¹⁵ times and then the generated reference voltage is compared with a not yet used memory cell.

In the from the DE 199 21 259 A1 known ferroelectric memory Plateleitungen are performed parallel to the word line. This requires a slow access, since all bits are connected to the Plateleitung with active word line. Further, the platelines are formed in a direction intersecting the bit lines and reference bit lines, and moreover, the number of sense amplifiers is equal to the number of bit lines. So all bits along the word line are activated.

It It is therefore an object of the invention to provide a ferroelectric memory device with a device for reference voltage generation formed from reference cells so specify that a very fast and space-efficient memory be made possible with age-free reference voltage generation can.

The Task is solved according to the claim.

According to one essential aspect is the above object in a generic ferroelectric Memory arrangement solved, which is characterized in that the ferroelectric memory device a "selective read "memory forms, where a "pulsed plate "parallel is arranged to the bit line, wherein per Plateleitung eight bit lines and provided two reference bit lines and per reference bit line a reference cell for each a logical "0" and a logical "1" with the true word line and the complementary Word line are coupled.

at the invention is for a "selective read" memory, a "pulsed plate" parallel to the bit line and only 8 bits are read per active word line. In each case, a reference cell for a logical "0" and a logical "1" respectively arranged on the true word line and the complementary word line. That in the aforementioned Publication "199 Symposium on VLSI Circuits " Problem that a pulsed Plateleitung in an architecture with a parallel to the bit line out Plateleitung interference at causes unselected cell capacitors is in the invention solved by that the Plateleitungsweite to a very small number, namely the mentioned 8 bit lines and the 2 reference bits is limited.

The core of the present invention thus lies in the combination of the measures, on the one hand to use reference cells for generating the reference voltage to properly map technological fluctuations and further to arrange these reference cells along the word line so that they are addressed as often as the actual memory cells.

following The invention will be explained in more detail with reference to the drawing. Show it:

1 a pulse timing diagram for explaining the reference voltage generation in DRAMs,

2 a pulse timing diagram for explaining the reference voltage position in ferroelectric memories,

3 a circuit diagram of an embodiment of a device according to the invention for reference voltage generation in ferroelectric memories and

4A , B, C Pulse timing diagrams for explaining the function of in 3 shown circuit.

The momentum diagrams of 1 and 2 have already been explained.

3 shows an example of a circuit arrangement of a ferroelectric memory in MOS technology, in which a "pulsed plate" PL <0> is arranged parallel to the bit line and forms a "selective read" memory in which only 8 bits per active word line are read. In 3 By way of example, it is assumed that a "1" is stored in the leftmost cell on the left. At the end of each word line WLT, WLC reference or dummy cells R1T, R2T and R1C, R2C are arranged. These reference cells are each arranged along a reference bit line BLTREF1, BLTREF2, BLCREF1, BLCREF2. The reference cells R1T, R2T are short-circuited with the clock signal φ1 via a first MOS switch S1 and connected to the word line WLT. The reference cells R1C and R2C are short-circuited to each other via a second MOS switch S2 with the clock signal φ2. This connection produces the desired reference voltage on the bit line BL. The wordline activates the memory cell but is not connected to the bitline.

The pulse timing diagrams in 4A , B and C each show signals which are in the in 3 shown circuit arrangement with the reference voltage generation according to the invention occur. The process starts at time t1 ( 4B ) with the leading edge of the word line signal WLT. After a certain time delay MUX C goes low, then comes the leading edge of the clock signal φ1, which turns on the MOS switch S1, and thus the two reference cells R1T and R2T by the dummy bit line interconnects.

The left part of the 4C shows the information signal "1" on the true bit line BLT and the reference voltage generated by means of the inventive reference cells R1T and R2T during the time of the clock φ1.

Claims (3)

A ferroelectric memory device in which bit and word lines crossing each other at the ferroelectric memory cells (CLT, BLC and WLT, WLC) and platelines PL are provided and reference cells loaded with logic "0" and logic "1" at the end of the word line (WLT, WLC ), to which the ferroelectric memory cells are also connected, are arranged along a reference bit line (BLTREF, BLCREF), characterized in that the ferroelectric memory arrangement forms a "selective read" memory in which a "pulsed plate" (PL) runs parallel to the 8 bit lines (BLT, BLC) and two reference bit lines per reference line, and one reference cell (R1T, R2T and R1C and R2C) for each logical "0" and logic "1" bit line (BL) "are coupled to the true word line (WLT) and the complementary word line (WLC). Ferroelectric memory arrangement according to claim 1, characterized in that the segmentation of the eight bit lines and the two reference bit lines per plateline along the word line (WLT, WLC) repeated. Ferroelectric memory arrangement according to claim 1 or 2, characterized in that the with the true word line (WLT) coupled reference cells (R1T, R2T) with a first clock signal (φ1), with the the complementary one Bit line (BLC) is clocked via a first MOS switch (S1) are shorted together, and that with the complementary Word line (WLC) connected reference cells (R1C, R2C) with a second clock signal (φ2), with which the true bit lines and the two reference bit lines (BLT) are clocked via one second MOS switch (S2) are shorted together.