DE102004045727B3 - Microcontroller or microprocessor with interface circuit has demultiplexer, registers in parallel and multiplexer for processing signals including page control bits - Google Patents

Abstract

The interface circuit (20) receives several signals from a bus line (21) connected to an interface in the microprocessor. The signals include page control bits (33), address data from system bus (32), address signals (addr[x:0]) and data signals (data). The system bus data signals are fed to a multiplexer (30) connected to a page register (23) with an output (25) to an external module (14). A feedback circuit consists of a demultiplexer (28), registers in parallel (25a-25c) and a multiplexer (29) for processing signals including page control bits.

Description

system comprising a microcontroller or microprocessor and an interface device, and methods of operating such a system

The The invention relates to a system comprising a microcontroller or Microprocessor and an interface device, and a method for Operate such a system.

conventional digital arithmetic circuits (e.g., on a microchip arranged microcontroller or microprocessor systems) have one or more (central) control or computing units on (Central Processing Units (CPUs), or CPU "cores").

The CPU or CPUs are - over one System bus (and possibly one or more other bus systems) - with one or multiple (external or internal) storage devices connected, e.g. a program and a data storage device ("program memory", and "data memory").

The "program memory" contains in particular the sequence of commands to be processed by the CPU core or cores, So the program (and possibly in addition corresponding - from to be used by the CPU cores - data constants).

Of the Program memory may e.g. from an EPROM (erasable PROM) Read-only memory) or EEPROM (Electrically Erasable PROM or Electric erasable Read-only memory), in particular a flash EEPROM component.

Thereby can be achieved that the program even if interrupted Power is stored on the appropriate storage facilities.

For frequently changing Programs can - alternatively - e.g. also RAMs (RAM = Random Access Memory), in particular DRAMs are used as program memory by an external programmer Mass storage can be loaded.

in the above-mentioned "Datastores" can e.g. the - in particular from the CPU cores when executing the program, if necessary, variables to be modified be saved.

Of the Data storage may e.g. of one or more RAM devices, in particular e.g. a corresponding DRAM device Dynamic Random Access Memory (DRAM), or SRAM (Static Random Access) device Memory) are formed.

The CPU or CPUs can - over the above-mentioned System bus, and an interface device connected to it - on (or more) external module (s) to be connected, in particular corresponding peripheral, externally from o.g. Microchip arranged modules, the e.g. above corresponding further bus systems with the interface device communicate.

Around To achieve relatively short access times, that of the CPU used address space be relatively small, especially smaller, as the address space needed or used by the (external) modules.

Around for the above-mentioned Modules - virtually - each needed - relative big - address space available too an address space extension method can be used, in particular a so-called paging method.

It is - as in 1 is illustrated - to one of a CPU 1 used and, for example, together with corresponding data via a corresponding bus 3 transmitted address addr [x: 0] one eg in a corresponding page register 2 stored page address addr [y: x + 1] added (and the extended total address addr [y: 0] - together with the data - to the corresponding module 4 transfer).

If you want to access a register that is outside the current page, the Page register 2 be reprogrammed.

This is in particular e.g. then disadvantageous when an interrupt is performed should.

The Concept of the interrupt may e.g. used to problems which are not provided in the normal program sequence to process.

at an interrupt, the program flow is interrupted, and in a certain service routine (interrupt service routine (ISR)) jumped. After the instructions of the routine have been processed, i.d.R. in the interrupted program.

• – Auslesen des im Page-Register abgespeicherten Werts;
• – Zwischen-Speichern des ausgelesenen Page-Register-Werts, insbesondere in einer der o.g. Speicher-Einrichtungen;
• – Programmieren eines neuen Page-Register-Werts in das Page-Register;
• – Ausführen des eigentlichen Interrupts;
• – Auslesen des zwischen-gespeicherten (alten) Page-Register-Werts;
• – Rück-Programmieren des alten Page-Register-Werts in das Page-Register.

If the above-mentioned paging concept is used, the following steps must be performed by the interrupt service routine.

• - reading the value stored in the page register;
• - intermediate storage of the read page register value, in particular in one of the above-mentioned memory devices;
• - programming a new page register value into the page register;
• - execute the actual interrupt;
• - reading out the intermediate stored (old) page register value;
• - Re-program the old page register value into the page register.

This is expensive, and can take a relatively long time to complete to take.

The Document US 2002/0087500 A1 shows a data management system which has a shared memory having, in several pages with each predetermined, fixed Divided length is. Part of the shared memory is for several so-called "Page Latches "reserved.

Everyone Page Latch is assigned to a specific page. With help a page latches will - during the Access to the associated page - the consistency of the on the the respective page stored data.

In the publication US 4,669,043 Software-controlled page tables are shown, in which it is noted whether a page is present in a memory and the page was last used / described, and a "message passing" method for the shared use of code and data.

The Invention has for its object, a novel system comprising a Microcontroller or microprocessor and an interface device, and a novel method of operating such a system to disposal in particular a system and method in which an interrupt of the microcontroller or microprocessor faster back to the page address before the interrupt can be.

she achieves this and other goals through the objects of claims 1 and 7.

advantageous Further developments of the invention are specified in the subclaims.

in the Following, the invention will be explained in more detail with reference to embodiments and the accompanying drawings. In the drawing shows:

1 a schematic representation of a CPU, a module connected thereto, and a page register for illustrating a paging method according to the prior art;

2 a schematic representation of a microcontroller or microprocessor system according to an embodiment of the present invention; and

3 a schematic detail representation of in 2 shown module and the in 2 shown interface device of the microcontroller or microprocessor system, illustrating a paging method according to an embodiment of the present invention.

In 2 is a schematic representation of a microcontroller or microprocessor system 10 shown according to an embodiment of the invention.

In the microcontroller or microprocessor system 10 For example, it can be an 8-bit microcontroller or microprocessor system 10 act (or any other microcontroller or microprocessor system, such as a corresponding 16-bit or 32-bit microcontroller or microprocessor system, etc.).

The microcontroller or microprocessor system 10 has one or more, on a corresponding microchip 15 arranged (central) control or computing units 11 on (Central Processing Units (CPUs), or CPU "cores").

The CPU 11 or the CPUs are - via a system bus 16 (and possibly one or more other bus systems) - with one or more internal (on the same microchip 15 like the CPU 11 provided) storage facilities 17 connected, as well as - eg via the system bus 16 , and one or more corresponding memory controllers ("memory controller") 12 - with one or more external (on a different microchip, than the CPU 11 provided) storage facilities 18 ,

The storage facilities 17 . 18 For example, they may act as program storage means, and / or data storage means ("program storage", and "data storage").

The "program memory" contains in particular the sequence of the CPU or CPUs 11 to be processed commands, so the program (and possibly additionally appropriate - of the or the CPUs 11 to be used - data constants).

The - eg of the memory device 17 formed - program memory can be formed for example by an EPROM (Erasable PROM or erasable read-only memory) or EEPROM (Electrically Erasable PROM or electrically erasable read-only memory), in particular a flash EEPROM device.

Thereby can be achieved that the program even if interrupted Power is stored on the appropriate storage facilities.

For frequently changing Programs can - alternatively - e.g. also RAMs (RAM = Random Access Memory), in particular DRAMs are used as program memory by an external programmer Mass storage can be loaded.

In the above - eg from the storage facility 18 formed - "data memory" can, for example, the - in particular of the or the CPUs 11 Variables to be modified when the program is executed.

Of the Data storage may e.g. of one or more RAM devices, in particular e.g. a corresponding DRAM device Dynamic Random Access Memory (DRAM), or SRAM (Static Random Access) device Memory) are formed.

The CPU or CPUs 11 can - eg via the above-mentioned system bus 16 (and possibly one or more other bus systems), and one to the system bus 16 (or the other bus systems) connected, internal, on the microchip 15 provided interface device 19 - to one (or more) external module (s) 14 be connected, and - as will be explained in more detail below - each via a corresponding - external (separately from the microchip 15 eg on a different microchip, than the CPU 11 provided) - Interface device 20 ,

The interface device 20 can via a corresponding (external) bus system 21 to the interface device 19 - and with it the system bus 16 - be connected (so between the CPU 11 , and the interface device 20 via corresponding address, control, and data sub-buses of the bus system 21 or the system bus 16 corresponding address, control and user data can be exchanged (eg - as explained in more detail below, and in 3 corresponding address data addr [x: 0], corresponding payload data, and corresponding control data (eg page control bits, page register programming data ("data for addr [y: x + 1] "), etc.))).

The interface device 20 can - as in 2 dashed lines - eg on and the same board as the module 14 (or alternatively on a separate board), and / or on the same microchip as the module 14 (or alternatively on a separate microchip), etc., etc.

The interface facilities 20 and / or the modules 14 can each be similar or identical respectively set up or set up so that the microprocessor system 10 - if required - to any other modules 14 with corresponding, respectively associated further interface devices 20 can be extended (in 2 shown in dashed lines).

The one from the CPU 11 (or the CPUs) can be relatively small, in particular smaller than that of the (external) module (s) 14 each required or used address space (eg, to achieve relatively short access times, and / or due to the CPU 11 used instruction set (eg, due to the use of short, little space-consuming, commands ("short addressing"))).

In order for the module (s) 14 - To provide virtual - the respectively required - relatively large - address space, a special, in the following explained in more detail address space expansion or paging method can be used.

It is - as in 3 is illustrated (and similarly similar to conventional methods) to one of the CPU (s) 11 and, for example, together with corresponding payload data from the CPU (s) 11 over the system bus 16 , and the connected bus system 21 to the interface device 20 transmitted address data addr [x: 0] in the interface device 20 (in the special manner explained below) one in one in the interface device 20 provided page register 23 saved page address addr [y: x + 1] added.

The Page address addr [y: x + 1] may be e.g. between 1 and 64 bits, in particular e.g. between 1 and 32 bits, e.g. between 1 and 8 bits, for example 2 bits.

The - extended - total address addr [y: 0] (more precisely: the address data addr [x: 0], together with the address extension address (page address) data addr [y: x + 1 ]) - as well as in 3 is illustrated - together with the above-mentioned payload data - to the module 14 - especially the module kernel 14a - transmitted (eg via an additional bus system 24 ).

For controlling the execution of the special address space extension or paging method used in the present exemplary embodiment, it is possible, for example, to use the in 3 shown - in each case in the corresponding interface devices 20 provided - Page-Steuer-Einrichtung 22 be used.

This points - except the above-mentioned page register 23 - several more registers 25a . 25b . 25c or ST0, ST1,..., STn, eg a number n of further registers 25a . 25b . 25c or ST0, ST1,..., STn (where n can be, for example, between 1 and 16, in particular, for example,> 2 or> 3, for example = 4, etc.).

The number n of other registers 25a . 25b . 25c or ST0, ST1, ..., STn need not necessarily after completion of the production of the interface device 20 be fixed, but can alternatively - eg by means of corresponding fuses, etc. - scalable selected or set (so after the preparation of the interface device 20 , and before commissioning the microprocessor system 10 - depending on the respective requirements - the number of further registers 25a . 25b . 25c or ST0, ST1, ..., STn (up to a predetermined maximum number) can be freely selected).

The number of other registers 25a . 25b . 25c or ST0, ST1, ..., STn, for example, can be chosen to be the same size as the number of interrupts that the module 14 must serve, or - alternatively - also eg smaller (see below).

In the page register 23 , and the other registers 25a . 25b . 25c or ST0, ST1,..., STn can be stored (or be storable) in each case (exactly) the same number of bits, for example - correspondingly identical to the page to be stored there (as will be explained in more detail below) Addresses addr [y: x + 1] - between 1 and 64 bits, in particular eg between 1 and 32 bits, eg between 1 and 8 bits, for example in each case 2 bits (PAGE bits [1: 0]), or in each case 4 Bits, or 8 bits each, etc., etc.

At the page register 23 , and the other registers 25a . 25b . 25c or ST0, ST1,..., STn may thus be, for example, corresponding to the page size, for example by 2-bit registers (or in each case by 4-bit registers, 8-bit registers, etc. , etc.) act.

How out 3 is the page register 23 - via appropriate lines 25 - To corresponding address data lines 26 of the bus system 24 connected (so that the above-mentioned address extension address (page address) data addr [y: x + 1] to the module 14 can be transferred), and - over to the lines 25 connected cables 27 - to a demultiplexer 28 ,

The demultiplexer 28 has a number n of outputs (advantageously the above number n of other registers 25a . 25b . 25c or ST0, ST1, ..., STn).

The first output of the demultiplexer 28 is via corresponding lines to the input of the first of the other registers 25a or ST0, the second output of the demultiplexer 28 via corresponding lines to the input of the second of the other registers 25b or ST1, etc., and the nth output of the demultiplexer 28 via corresponding lines to the input of the nth of the other registers 25c or STn.

Depending on the corresponding control lines 33 - or connected cables 34 Pending page control bits may be either the first, or the second, etc., or the nth of the further registers 25a . 25b . 25c or ST0, ST1, ..., STn - via the demultiplexer 28 - with the above mentioned lines 25 . 27 (and thus the page register 23 ), so that - as explained in more detail below - the in the page register 23 stored page address addr [y: x + 1] - optionally - either in the first of the other registers 25a or ST0, or in the second of the other registers 25b or ST1, etc., or in the nth of the other registers 25c or STn can be stored.

How out 3 is further apparent, is an output of the first of the other registers 25a or ST0 via corresponding lines to a first input of a multiplexer 29 connected, an output of the second of the further registers 25b or ST1 via corresponding lines to a second input of the multiplexer 29 , etc., and an output of the nth of the other registers 25c or STn via corresponding lines with an n-th input of the multiplexer 29 ,

The output of the multiplexer 29 is via appropriate lines 31 with a first input of another multiplexer 30 connected to the second input - via corresponding lines 32 - the above-mentioned page register programming data ("data for addr [y: x + 1]") can be created.

The wires 32 can eg be part of the above-mentioned data sub-bus of the bus system 21 his (the page register 23 is thus assigned its own address, so it can by means of the above-mentioned address sub-bus of the bus system 21 transmitted signal - the page register 23 is thus readable and writable via the normal data path).

Depending on the corresponding control lines 33 - or connected cables 35 . 36 Pending page control bits may be either the first, or the second, etc., or the nth of the further registers 25a . 25b . 25c or ST0, ST1, ..., STn - via the multiplexer 29 - with the above mentioned lines 31 , and on - over the other multiplexer 30 - with the page register 23 be connected, so that - as will be explained in more detail below - either either in the first of the other registers 25a or ST0, or in the second of the other registers 25b or ST1, etc., or in the nth of the other registers 25c or STn stored page address addr [y: x + 1] in the page register 23 can be stored.

Alternatively - depending on the corresponding control lines 33 , in particular the cables connected thereto 36 adjacent page control bits ("page control bits") - the above-mentioned lines 32 - via the further multiplexer 30 - with the page register 23 be connected, so that - as will be explained in more detail below - optionally also on the lines 32 Page register register data ("data for addr [y: x + 1]") in the page register 23 can be stored.

As - on the wires 33 (and thus also on the connected to these lines 34 . 35 . 36 ) - page control bits ("page control bits"), for example, corresponding register or memory number bits (storage number bits (STNR bits)) can be used, and - in parallel - eg corresponding operation control -Bits (Operation Bits (OP bits)).

The number x of STNR bits may depend on the respective number n of other registers 25a . 25b . 25c or ST0, ST1, ..., STn be selected, in particular such that by the STNR bits each selected further register 25a . 25b . 25c or ST0, ST1, ..., STn can be uniquely identified (see above that is 2 ^x ≥ n).

For example can between 1 and 8 STNR bits, e.g. between 1 and 4 STNR bits, in particular more than 1 or 2 STNR bits, for example e.g. 2 STNR bits [5: 4], etc.

The above - eg 4 - further registers 25a . 25b . 25c (ie corresponding registers ST0, ST1, ST2, ST3) can then be selected, for example, as shown in the following Table 1:

Tabelle 1

Table 1

The STNR bits can be used to indicate which of the other registers 25a . 25b . 25c or ST0, ST1, ..., STn should be used in the respectively performed - defined by the operation control bits (operation bits (OP bits)) - operation.

The Number of OP bits may be dependent from the respective number of different operations to be performed chosen be.

For example can be provided between 1 and 4 OP bits, in particular more than 1 OP bit, e.g. 2 OP bits [7: 6].

With The OP bits can be displayed, which of several different ones Operations performed in each case shall be.

The each to be performed Operation can then be through the op bits e.g. as shown in the following Table 2, and as follows explained in more detail selected become:

Tabelle 2

Table 2

In the "manual" or "normal" or "standard" page mode illustrated in the first row of Table 2 (OP bit [7] = 0, and irrespective of the state of the OP bit [6]), the additional multiplexers 30 controlled by the op bits so that the wires 32 with the page register 23 connected, and the wires 31 from the page register 23 separated (and the demultiplexer 28 and possibly the multiplexer 29 so that the wires 27 and possibly the lines 31 from the other registers 25a . 25b . 25c or ST0, ST1, ..., STn are separated).

This ensures that - regardless of the other registers 25a . 25b . 25c or ST0, ST1, ..., STn stored values - (and similarly similar to conventional paging methods) on the lines 32 applied Page register programming data ("data for addr [y: x + 1]") as a new page register value in the page register 23 can be stored (without the old page register value in one of the other registers 25a . 25b . 25c or ST0, ST1, ..., STn is stored).

In the "page programming and backup mode" illustrated in the second row of Table 2 (OP bit [7] = 1, and OP bit [6] = 0) becomes the other multiplexer 30 - also (as with "manual" or "normal" or "standard" page mode) - controlled by the OP bits so that the lines 32 with the page register 23 connected, and the wires 31 from the page register 23 separated (and possibly the multiplexer 29 so that, if necessary, the lines 31 from the other registers 25a . 25b . 25c or ST0, ST1, ..., STn are separated).

However, unlike the "manual" or "normal" or "standard" page mode, the demultiplexer will be used 28 in the page programming and backup mode, through the op bits so controlled that the lines 27 (and thus also the connected to these lines 25 ) with the other registers selected by the STNR bits 25a . 25b . 25c or ST0, ST1, ..., STn (eg, if the STNR bits _ are "00") with the further register ST0, and if the STNR bits = "01", with the further register ST1, etc.).

This ensures that the in the page register 23 stored old page register value in the other register selected by the STNR bits 25a . 25b . 25c or ST0, ST1, ..., STn can be stored, and at the same time or in parallel (or a short time later, for example, only two or one or a half clock period later) on the lines 32 applied Page register programming data ("data for addr [y: x + 1]") as a new page register value in the page register 23 can be stored.

In the "page reprogramming mode" illustrated in the third row of Table 2 (OP bit [7] = 1, and OP bit [6] = 1) becomes the other multiplexer 30 Unlike the "manual" or "normal" or "standard" page mode, and unlike the "page programming and backup mode" - controlled by the op bits so that the lines 31 with the page register 23 connected, and the wires 32 from the page register 23 separated (and possibly the demultiplexer 28 so that the wires 27 from the other registers 25a . 25b . 25c or ST0, ST1, ..., STn are separated).

Furthermore, the multiplexer 29 in the page reprogramming mode, through the op bits so controlled that the lines 31 (and thus - via the multiplexer 30 - also the page register 23 ) with the other registers selected by the STNR bits 25a . 25b . 25c or ST0, ST1, ..., STn are connected (eg, if the STNR bits = "00") to the further register ST0, and if the STNR bits = "01", to the further register ST1, etc.).

It is thereby achieved that the further register selected in the STNR bits 25a . 25b . 25c or ST0, ST1, ..., STn stored (old) page register value back into the page register 23 written, ie (again) can be stored there.

Should - in particular in the case of an interrupt - access to one outside the current one - by the one in the page register 23 stored page range (ie, a memory area lying on a new page defined by a new page register value) can first be stored in the "Page Programming and Backup Mode" described above. (OP bit [7] = 1, and OP bit [6] = 0) in the Page register 23 stored page register value in the further register selected by the STNR bits 25a . 25b . 25c or ST0, ST1, ..., STn are stored, and at the same time or in parallel (or a short time later) from the CPU 11 on the lines 32 applied page register programming data ("data for addr [y: x + 1]") as the new page register value in the page register 23 ,

Thereafter, the actual interrupt may be executed, and then in the above-described "page reprogramming mode" (OP bit [7] = 1, and OP bit [6] = 1) the one selected in the STNR bits register 25a . 25b . 25c or ST0, ST1, ..., STn stored (old) page register value back into the page register 23 to be written.

When next can in the actual - through the interrupt interrupted program to be continued.

This can in the paging method according to the present embodiment much faster than conventional paging methods.

The reason for this is, inter alia, that in the above-mentioned procedure in comparison with the prior art in the case of the interrupt corresponding - caused by the CPU, conventional - read operations for reading the last used page register value (which then over the system bus 16 , or the bus system 21 bypassed corresponding bus systems) are bypassed.

Instead will - like explained above - an automatic, local intermediate storage of the last used page register value.

The above - provided in the prior art - caused by the CPU read operations cause the CPU is held relatively long, as these only the - over the buses 16 . 21 corresponding bus systems transmitted - wait for the result of the reading operation.

In the procedure described above, to execute the interrupt, instead, only the CPU is used 11 caused conventional (non-CPU or low-maintenance) write operations to be necessary (and no - to corresponding data traffic on the bus systems 16 . 21 corresponding bus systems leading - read operations).

Alternatively, in the present exemplary embodiment-optionally additionally-a method correspondingly similar to that used in conventional paging methods may also be used (in the course of which, for example, the last-used page register value is not in one of the above-mentioned further registers 25a . 25b . 25c is stored, but - by means of appropriate read operations - from the CPU 11 requested, over the buses 21 . 16 transferred, and in a corresponding memory device (eg one of the above storage facilities 18 . 17 ) (and later read out there again) will be).

For example can be one, similar to that like traditional ones Paging method running for relatively long and / or relative little important interrupts are used, and the one described above - special - (no CPU reading operations using) e.g. for relative short and / or relatively important interrupts.

The number of other registers 25a . 25b . 25c or ST0, ST1, ..., STn may then be less than the number of interrupts that the module 14 must serve.

As can be seen from the above, a modular structure (in particular a modular system by further modules) can be achieved by the paging method according to the present exemplary embodiment 14 expandable structure) of the microprocessor system 10 be achieved: the control of the paging procedure is the sole responsibility of the CPU 11 or the CPUs 11 , and the respective interface devices 20 (or the respective provided page control facilities 22 ); the respective modules 14 can (continue) work in their respective original address space.

1

CPU

2

Page register

3

bus

4

module

10

Microprocessor system

11

CPU

12

Memory control means

14

module

14a

Module Kernel

15

microchip

16

System bus

17

Memory means

18

Memory means

19

Interface means

20

Interface means

21

Bus system

22

Page control device

23

Page register

24

Bus system

25

cables

25a

register

25b

register

25c

register

26

cables

27

cables

28

demultiplexer

29

multiplexer

30

multiplexer

31

cables

32

cables

33

cables

34

cables

35

cables

36

cables

Claims (7)

System comprising a microcontroller or microprocessor ( 10 ) and an external interface device connected thereto via an external bus ( 20 ), The external interface device ( 20 ) via an additional bus system ( 24 ) with an external module ( 14 ). the interface device has a first and at least one further, second memory device ( 23 . 25a ) for storing each page address (addr [y: x + 1]), Wherein a page address is loaded into the first memory device via the external bus, wherein in the case of an interrupt of the microcontroller or microprocessor a control signal and a new page address are sent to the interface device via the external bus and The control signal causes the page address stored in the first memory device to be written to the second memory device and then the new page address to be loaded into the first memory device, wherein in each case if an address (addr) x: 0]) is sent via the external bus to the interface device, the interface device an extended address, consisting of each stored in the first memory device page address and the address, via the additional bus system the external module transmits. The system of claim 1, wherein the interface device comprises more than two further memory devices ( 25a . 25b . 25c ) having. The system of claim 2, wherein the interface device comprises more than three further memory devices ( 25a . 25b . 25c ) having. A system according to any one of claims 2 or 3, wherein the interface means a demultiplexer. A system according to any one of claims 2 to 4, wherein the interface means having a multiplexer. System according to one of the preceding claims, in which the interface device ( 20 ) externally from a microcontroller or microprocessor chip ( 15 ) is arranged. Method for operating a system after a the claims 1 to 6, the method comprising the steps of: - Load a page address in the first memory device via the external bus, - Send a control signal and a new page address via the external bus to the interface device in the event of an interrupt the microcontroller or microprocessor, wherein the control signal causes the stored in the first memory device Page address is written to the second memory device and then the new page address in the first memory device is loaded - in which in each case, if an address (addr [x: 0]) via the external bus to the Interface device is sent, the interface device an extended address consisting of the respectively in the first memory device stored page address and the address, via the additional bus system to the external Module transmits.