DE102005002339A1 - Adapter arrangement for connection to drive interface, connects control computer with register set in auxiliary device, where individual registers of set are associated to address decoder and one register is designed as E-A-port - Google Patents

Abstract

The arrangement connects the control computer with a standard register set in an auxiliary device to be controlled, where individual registers of the register set are associated to an address decoder. The registers are arranged downstream of interface lines. One of the register is designed as an E-A-port. The registers are provided for read and write access. A connection control is implemented in the arrangement.

Description

The The invention relates to input and output devices that conform to a standardized Drive interface can be connected. The underlying Interface standards: ATA / ATAPI and High Speed Serial ATA Attachment (SATA). The invention is used in computer systems for controlling Processes and technical equipment (embedded systems) are used, to computers, preferably personal computers (PCs), with the controlled Connect facilities.

It has been common for some time Hardware and software from the field of personal computers (PCs) to Control to use any facilities. It exists always the problem, the devices to be controlled with the computer connect to. The conventional ones solutions are based on developing appropriate adapters to a Extension bus of the computer to be connected. Furthermore you have the usual E-A interfaces (RS-232, IEEE 1284, USB, etc.). The essential Requirements for such solutions Both low hardware costs, decent development costs and concerns low latency and reaction times (from the occurrence of a request to the program-side treatment or the program-side release until becoming effective in the hardware). By using an expansion bus (ISA, PCI and successor) you can have extreme time requirements fulfill, but the development costs are high (circuit design), and the hardware becomes comparatively expensive. (Significant cost shares arise u. a. by the need for multi-level circuit boards and to use extremely miniaturized, highly integrated circuits. Occasionally, those required by standardization bodies royalties added). With recourse to the usual E-A interfaces, the hardware is inexpensive, but it arise mostly extreme latency and reaction times (milliseconds to microseconds). Modern interfaces (eg USB) also require a lot of effort for the Development of the associated software.

The The aim of the invention is to use existing interfaces to deal with comparatively low expenses (in Hardware and software) and make it possible to to ensure low latency and reaction times (microseconds).

The The object of the invention is to provide circuit arrangements (interface adapter) indicate over The arbitrary devices to be controlled with the usual in the PC field Drive interfaces ATA / TAPI and Serial ATA can be connected.

The defects the known solutions their cause is that the about to be controlled devices Interfaces are connected, their adaptation and program-side Support one comparatively high effort or the very long latency and have reaction times.

According to the invention Problem solved by the cited in the claims circuits.

The Invention acts such that at least one Part of the standard provided Interface register is used as input and output registers. Other interface registers can be used for addressing purposes. Inventive interface adapter can be operated in such a way that the Configuration control software (BIOS, operating system) do not recognize can that one such device is connected. This becomes the interface adapter not affected by the system configuration and management arrangements, is therefore freely available to the respective application programs. The The program-side interface is based on elementary input and output commands. Thus, the latency and reaction times correspond to the respective Command execution times. In addition to such elementary E-A access, standard command protocols can also be used supports become. This will make it possible Interfaceadapter according to the invention over the standardized interface to connect Serial ATA (SATA) and Exploit operating modes that are over the simple programmed input and output go out, z. B. the Bus master operation and automatic DMA operation (ADMA).

For connecting any devices to be controlled (universal input and output) an existing in almost any PC interface is exploited, without causing conflicts with the actual (intended) use of this interface. As a result of the actual determination of such interfaces (connection of drives) one can expect a comparatively long lifetime of the interface standards and corresponding availability of relevant hardware. To equip the PC with additional interfaces, commercially available ATA interface cards can be used, which are significantly cheaper compared to special EA plug-in cards. Due to the simple operation, the circuits are not too expensive. Inventive interface adapters can, for. B. with marketable programmable Circuits are built and housed on inexpensive circuit boards. It is possible to equip PCs of the usual types with interface adapters according to the invention, which can be installed like drives. In addition, such interface adapters can be accommodated on PC modules, which are intended for use in embedded systems. This gives such a module application properties of a real microcontroller, z. B. a variety of freely programmable universal I / O connections. Since the program-side interfaces are not based on several software layers (such as, for example, in the case of USB and network interfaces), the accesses to interface adapters according to the invention can be programmed in an elementary manner, and it is possible to ensure latency and reaction times in the microsecond range. The basic input and output (port I / O) is supported in each of the common operating systems. Therefore, the use of interface adapters according to the invention does not require excessive programming development effort. In addition, more advanced modes can be exploited that are supported by the typical control circuitry of the PCs. Thus, the automatic DMA operation (ADMA) allows autonomous execution of entire command sequences in the hardware - that is, without intervention of the processor.

One embodiment The invention is illustrated in the drawing and will be described below described in more detail.

It demonstrate

1 the signals of the conventional (parallel) ATA interface,

2 and 3 the addressing and assignment of the standard register set,

4 the flow of elementary read and write accesses,

5 the original and the inventive use of the interface standard,

6 a generally usable design of the address decoder,

7 the design of a simple I / O port,

8th the wiring of the address decoder with a blocking line,

9 the suppression of register accesses by means of the time step,

10 the suppression of register accesses via a signature recognition circuit,

11 to 13 an example of the structure of the signature recognition circuit,

14 and 15 Details of the address decoding circuits,

16 and 17 appropriate usage of standard register addresses,

18 the construction of a universal I / O port,

19 the connection of several I / O ports,

20 the use of the feature register as an additional address register,

21 the connection of a RAM,

22 the connection of an I / O bus system,

23 to 26 the development of the interface adapter for single bit accesses,

27 and 28 the connection of a read-only memory with identification data,

29 to 33 the connection of several devices to one interface,

34 the operation of the standard 48-bit addressing,

35 to 39 Circuit solutions of extended addressing,

40 to 52 the development of the interface adapter in order to support standard command protocols and for connection to high-speed bit serial interfaces (Serial ATA),

52 to 54 the principle of command execution,

55 to 59 various variants of the command run control, especially the influencing of the command execution time,

60 to 62 Further developments of the interface adapter in order to support data transmission,

63 a variant of the constructive (mechanical) structure,

64 to 70 Interface adapter with interface switching,

71 an interface adapter with interface switching on a PC module,

72 a programmable circuit with interface adapter.

• 1. 1532D: AT Attachment-7 with Packet Interface (ATA/ATAPI – 7). Vorläufige Dokumentation (Draft Documents): d1532v1r4b (Band 1), d1532v2r4b (Band 2), d1532v3r4a (Band 3).
• 2. 1697D: AT Attachment-8 Serial Transport (ATA8-ST). Vorläufige Dokumentation (Draft Document): D1697r0-ATA8-ST.

The relevant standards are being handled by the ANSI Committee T13. The exemplary embodiment is based on the following standards:

• 1. 1532D: AT Attachment-7 with Packet Interface (ATA / ATAPI-7). Preliminary Documentation (Draft Documents): d1532v1r4b (volume 1), d1532v2r4b (volume 2), d1532v3r4a (volume 3).
• 2. 1697D: AT Attachment-8 Serial Transport (ATA8-ST). Draft Document: D1697r0-ATA8-ST.

1 illustrates the signals of the conventional (parallel) ATA interface. The interface is used to access from the processor (host) to a register set, which is housed in the connected devices. The interface signals CS1, CS0, DA2, DA1 and DA0 are used to select one register from this register set. There are 9 permissible register addresses, which can be accessed on a total of 12 registers.

The 2 and 3 show a typical assignment of this register set. Data register accesses are carried out in a width of 16 bits (via the data lines DD15 ... 0), all other accesses in a width of 8 bits (via the data lines DD7 ... 0).

• – Kommandoregisterblock. 8 Registeradressen, 10 Register. CS1- = 1, CS0- = 0 (Auswahl mit CS0).
• – Steuerregisterblock. 1 Registeradresse, 2 Register. CS1- = 0, CS0- = 1 (Auswahl mit CS1).

The register file is divided into two blocks:

• - Command register block. 8 register addresses, 10 registers. CS1- = 1, CS0- = 0 (selection with CS0).
• - Control register block. 1 register address, 2 registers. CS1- = 0, CS0- = 1 (selection with CS1).

On invalid Register addresses are allowed the devices do not react (write attempts are ignored when reading attempts the data lines remain high-ohmic).

#:

Inhalt kommandoabhängig,

res:

reserviert,

va:

veraltet (von ATA/ATAPI-4 an bedeutungslos),

R:

nur Lesen,

W:

nur Schreiben,

R/W:

Lesen und Schreiben,

1...5:

Zugriffsbeschränkungen.

The abbreviations in 3 mean:

#:

Content dependent on command,

res:

reserved,

va:

outdated (from ATA / ATAPI-4 to meaningless),

R:

just read,

W:

only writing,

R / W:

Read and write,

1 ... 5:

Access restrictions.

1:

Zugriffe dürfen nur dann ausgeführt werden, wenn DRQ gesetzt ist,

2:

Schreibzugriffe sind nur möglich, wenn BSY und DRQ beide 0 sind. Ein gelesener Registerinhalt ist nur dann gültig, wenn BSY = 0 ist.

3:

der gelesene Registerinhalt ist nur dann gültig, wenn BSY und DRQ beide 0 sind und ERR gesetzt ist,

4:

Zugriffe sind immer möglich, aber wenn BSY gesetzt ist, sind die anderen gelesenen Bits ungültig,

5:

Zugriffe sind immer möglich.

In the 3 access restrictions 1 ... 5 depend mainly on the device state:

1:

Accesses may only be executed if DRQ is set,

2:

Write accesses are only possible if BSY and DRQ are both 0. A read register content is valid only if BSY = 0.

3:

the read register contents are valid only if BSY and DRQ are both 0 and ERR is set,

4:

Accesses are always possible, but if BSY is set, the other bits read are invalid,

5:

Access is always possible.

4 illustrates the flow of elementary read and write accesses. This type of access is referred to as programmed input and output (Programmed I / O; PIO).

• PIO 0: Zykluszeit: 600 ns; maximale Datenrate: 1,66 MBytes/s (Registerzugriffe; 8 Bits) bzw. 3,32 MBytes/s (Datenzugriffe; l6 Bits).
• PIO 4: Zykluszeit: 120 ns; maximale Datenrate: 8,33 MBytes/s (Registerzugriffe; 8 Bits) bzw. 16,66 MBytes/s (Datenzugriffe; l6 Bits). Diese Betriebsart ergibt nahezu die (in E-A-Zugriffen praktisch nutzbare) Datenrate des PCI-Bus, die Schnittstellen hardware im Adapter ist aber kaum komplizierter als ein herkömmlicher ISA-Busanschluß.

There are different operating modes (PIO 0 to PIO 4). They only differ in the time characteristics. Examples:

• PIO 0: cycle time: 600 ns; maximum data rate: 1.66 MBytes / s (register accesses, 8 bits) or 3.32 MBytes / s (data accesses, 16 bits).
• PIO 4: cycle time: 120 ns; maximum data rate: 8.33 MBytes / s (register accesses, 8 bits) and 16.66 MBytes / s (data accesses, 16 bits). This mode gives almost the (in EA accesses practically usable) data rate of the PCI bus, but the hardware interfaces in the adapter is hardly more complicated than a conventional ISA bus connection.

Interface signals Register assignments and access sequences are in those of the technical Committee ANSI T13 extensively described, so that one detailed explanation can be omitted.

5 illustrates both the original and the inventive use of said interface standard.

With conventional use of the interface ( 5 above) contains the controlling computer 1 (hereinafter also referred to as PC (personal computer) or host) a terminal controller (interface controller) 2 , via a standard interface 3 drives 4 (eg hard disks) are connected downstream. Every drive 4 contains a connection control 5 and a downstream standard register set 6 , In use according to the invention ( 5 below) gets to the standard interface 3 an interface adapter 7 connected to the via I / O ports 8th any devices to be controlled 9 can be connected downstream.

at conventional Using the interface, you can connect one or two drives.

• 1. ein einziger Interfaceadapter 7,
• 2. mehrere Interfaceadapter 7,
• 3. ein Laufwerk 4 und ein oder mehrere Interfaceadapter 7,
• 4. zwei oder mehrere Laufwerke 4 und ein oder mehrere Interfaceadapter 7.

When used according to the invention arise - depending on the design of the interface adapter 7 - various connection options:

• 1. a single interface adapter 7 .
• 2. multiple interface adapters 7 .
• 3. a drive 4 and one or more interface adapters 7 .
• 4. two or more drives 4 and one or more interface adapters 7 ,

6 shows a generally usable design of the in the terminal control 5 arranged address decoder for the register set 6 , The interface lines CS1, CS0, DA2, DA1 and DA0 are connected to AND gates 10 and 11 as well as to a decoder 12 connected. The decoder 12 and the AND gate 11 are the access permission lines 13 the standard register (see the 2 and 3 ) downstream. The decoding of addresses is one of the foundations of digital technology, so that a closer description is not required. AND gate 10 is also connected with the interface signals DMARQ and DMACK, to prevent the assignment of the other connected interface lines from being evaluated by the address decoder during ongoing DMA accesses. This is a general requirement, which results from the principles of the interface and also does not need to be explained.

7 illustrates the design of a simple I / O port 8th , It consists of an output register 14 and an input register 15 attached to one of the access permission lines 13 the said address decoder are connected. From the PC to the relevant register of the register set 6 (see the 2 and 3 ) and is a write access (DIOW active), the assignment of the data bus lines (eg DD7 ... 0) to the output register 14 accepted. If it is a read access (DIOR active), the input assignment to the input register becomes the leading edge of the DIOR signal 15 taken over and switched on the data bus lines.

A but such arrangement is due to the usual (per se intended) use of this Interfaces in usual PCs not readily operational.

• 1. infolge der Wirkungen der Systemsoftware (vor allem der Konfigurationsabläufe),
• 2. wenn Interfaceadapter und Laufwerke) am gleichen Kabel betrieben werden,
• 3. bei bestimmungsgemäßer Nutzung der Interfacesteuerung 2 im PC.

It is to be counted on several conflict cases:

• 1. due to the effects of the system software (especially the configuration processes),
• 2. if interface adapters and drives are operated on the same cable,
• 3. in the case of the intended use of the interface control 2 in the PC.

The conflicts arise because of the interface itself only for the connection of drives and is not designed as a universal E-A interface.

The system software attempts to boot up the existing in the PC ATA interface controller 2 to configure. Because of the fundamental importance of the ATA interfaces as a drive interface, these processes are typically deeply embedded in the system software (BIOS, operating system), so they can - unlike conventional device drivers - not be put out of action simply by uninstalling.

If an ATA interface controller is detected, the software searches for connected drives. EA facilities similar to the 6 and 7 are initially addressed as a drive. This can lead to conflicts as the system configuration progresses.

Around to prevent this, the address decoder with a blocking line wired. This blocking line is switched on by switching on the PC to the end of the configuration processes activated.

8th illustrates how an address decoder according to 6 with a blocking line 16 is connected. With active blocking line 16 all register accesses are suppressed. Access attempts are ineffective.

9 shows how the register accesses can be suppressed for the duration of the configuration processes. For this purpose, that is the address decoder 17 upstream blocking line 16 at a time step 18 connected. The time step 18 can be performed for example as a monostable multivibrator. It is activated when the hardware is reset on the PC and is set to switch off only after the configuration process has finished (typically after a few seconds).

The solution according to 9 is simple in terms of circuitry. The time to be set depends very much on the type of PC and the respective configuration software. 10 shows therefore a further interpretation in which the blocking line 16 to a signature recognition circuit 19 shot. It is activated during the hardware reset of the PC and remains active until a certain characteristic sequence of accesses (the signature) arrives. The output of the signature is typically caused by the particular application software, which thus the sole control of the interface adapter 7 takes over.

The principle of signature recognition is based on executing a very specific sequence of accesses, which differs significantly from the usual access sequences during normal operation, but which, on the other hand, does not affect normal operation. The 11 to 13 illustrate an exemplary layout of the signature recognition circuit 19 ,

According to 11 are a sequential read-only memory 19 , a length counter 20 , a comparator 21 and control circuits 22 . 23 intended. 12 shows the structure of the control circuit 22 which decodes the signature accesses. In the example, the signature consists of several consecutive write accesses to the interface register No. 5 (cylinder No. high; 2 ). Any such access results in a pulse on the SIGNA-TURE ACCESS line and causes the signature check to be turned on (SIGNATURE CHECK). Each write access with a different address and any read access switches the signature check off again (SIGNATURE CHECK becomes inactive). 13 shows the structure of the control circuit 23 who is the blocking line 16 is downstream. It contains a non-equal flip-flop 24 and a release flip flop 25 , The blocking line 16 is at the inverted output of the enable flip flop 25 connected.

There must be a certain number of write accesses to be done, with each access to provide a specific data occupancy. All data allocations are in sequential read-only memory 19 contain. This can z. B. be executed as a feedback shift register, which advances with each clock to the next bit pattern, or as a conventional ROM array, the z. B. from the length counter 20 can be addressed. The software transmits the signature with a sequence of write accesses to the said interface register No. 5. In each access, the data byte transmitted via the data bus lines DD7... 0 is supplied with the desired value from the sequential read-only memory 19 compared. It also becomes the content of the length counter 20 increased by one. If another access is executed, SIGNATURE CHECK becomes inactive, and the sequential read-only memory 19 as well as the length counter 20 will be reset.

Initially, non-equal flip-flops 24 and Sperrflipflop 25 deleted. This will cause the blocking line 16 activated. Detects the comparator 21 an inequality, the inequality flip-flop becomes 24 set. When the last data byte has been transferred (LAST BYTE), the outputs of the comparator become 21 and the non-equal flip-flop 24 evaluated. Only if equality is detected in all transmissions is the inequality flip-flop 22 not set. This condition causes the release flip-flop to be set 25 and thus deactivating the blocking line 16 , The blocking line 16 can never be active again afterwards. Under all other conditions (inequality, write accesses to other addresses, arbitrary read accesses) the release flip flop remains 25 reset because either the inequality flip-flop 24 or (by deactivating SIGNATURE CHECK) the entire signature evaluation was aborted.

14 illustrates another embodiment of the address decode circuits 17 that conflicts with other drives on the same cable, with the interface controller 2 in the PC and typically also avoids with the configuration software. In this case, only those standard register addresses are used that have nothing to do with commands, states, etc. These registers are provided as standard for read and write accesses (without accompanying control effects or the like). Accesses to such register addresses are made by the interface adapter 2 only passed on, so there are no special tax procedures. In the execution after 14 only the addresses 2 to 6 in the command register block (see. 2 ) evaluated. In addition, the device and head selection register becomes 26 (Address 6) used in its original function (device selection). This allows two devices (drive + interface adapter or two interface adapters) to be operated on one cable. In the example, the drive is configured as master (device 0) and the interface adapter as slave (device 1). The special standard signal games of the interface, which inform the master about the presence of a slave, are not supported. The master thus sees itself as the only device on the cable (masteronly configuration).

From the device and head selection registers 26 Only bit position 4 (DEV = device selection) must be implemented on the hardware side. Device selection: Master: DEV = 0, Slave: DEV = 1. Accesses to this register are always executed. This is a special address decoder 27 intended. The other registers, on the other hand, can only be accessed if the slave device has been selected (DEV = 1). In 14 became the address decoder 17 across from 6 modified so that only registers are selected that can be safely accessed in accordance with ATA standard. Thus, four 8-bit ports are accessible.

To increase the number of supported I / O ports, see 15 the address decoder 27 downstream device and head selection registers 26 extended by additional bit positions that accommodate a port selection address. Each output line of the address decoder 17 can thus be a Portadreßdecoder 28 be followed.

An advantageous design results when the Portadreßdecoder 28 be designed so that they only respond to port addresses greater than or equal to one, so that one in the device and head selection register 26 entered port address zero remains ineffective. In addition, the device and head selection register 26 accessible only for write access. Read access to this register is ineffective. Provide ineffective read access - via the interface controller 2 in the PC - always a fixed value FFH back to the program. Many configuration processes initially check the presence of a drive by entering the value 0H into the low order bits of the device and head select register 26 and by further trial and error read and write accesses. The described design ensures, on the one hand, that "nothing" - ie FFH - is always read back, and, on the other hand, that sample accesses to other register addresses have no unwanted side effects (the EA registers that are actually present can not be influenced by such configuration processes). ,

The 16 and 17 illustrate appropriate usage of standard register addresses. The device and head selection register is used according to 15 for selecting the interface adapter (bit 4) and for addressing I / O ports (bits 3 ... 0). The actual I / O ports are accessible via register addresses, which are designed according to standard only for simple read and write accesses without any special effects.

General usage:

• 1. the port selection address in the device and head selection register 26 load,
• 2. over one of the standard register addresses 2 ... 5 access the respective port register.

16 shows a version containing only universal I / O ports ( 18 . 19 ). Each port has an access width of 8 bits. It consists of a direction register and a data register. In the division according to 16 Two such ports can be addressed via a single port selection address. In total, more than 15 valid port addresses can address 4 •• 15 = 60 universal 8-bit ports.

According to 17 At most only 2 •• 15 = 30 8-bit universal ports can be addressed since two of the standard register addresses are provided to address special peripherals. This concerns, among other things, analog-to-digital converters, power circuits, memory and timers. With 15 port addresses 2 •• 15 = 30 bytes can be made accessible for read and write access.

18 illustrates the construction of a universal I / O port from a single bit position. The entire port consists of eight such circuits. Each I / O port of such a port can be individually switched between input and output.

• 1. Bit im Richtungsregister 29 = 0: Eingang,
• 2. Bit im Richtungsregister 29 = 1: Ausgang.

In each bit position is ever a flip-flop of a direction register 29 and a data register 30 intended. The data register 30 are about tri-state drivers 31 the I / O connections 32 downstream. The permission inputs of the tri-state drivers 31 are with the respective bit positions of the direction register 29 connected. In the example, the following assignment applies:

• 1st bit in the direction register 29 = 0: input,
• 2nd bit in the direction register 29 = 1: output.

Each of the registers 29 . 30 can via port selection signals of a Portadreßdecoders 28 (see. 15 ) are selected for loading (data transfer from the data bus lines DD7 ... 0 with write control signal DIOW-).

• 1. Richtungsregister = Zylinder-Nr. hoch (Adresse 5),
• 2. Datenregister = Zylinder-Nr. niedrig (Adresse 4).

With the in 18 shown wiring results in the following assignment (see. 2 ):

• 1st direction register = cylinder no. high (address 5),
• 2nd data register = cylinder no. low (address 4).

To the signal assignment of the I / O connections 32 to read (input), these are in the example via tri-state Buskoppelbrufen 33 connected to the data bus lines DD7 ... 0. The connection takes place when the relevant register is selected (eg via address decoder signal PORTS4_1) and active read control signal DIOR-.

According to 19 may be a decoder arrangement of address decoder circuits 17 and port address decoders 28 (see. 15 ) several I / O ports 35 be followed. These can be both universal I / O ports and registers associated with multiple peripheral devices, e.g. For example, with analog-to-digital converters, with timer circuits, with memories, etc. Basically, this is inside the interface adapter 7 provide a data bus with access control and select lines to which any input and output registers can be connected. The principle solution of the EA-side expansion in the interface adapter 2 corresponds in itself to the EA extension of conventional microprocessor systems and thus need not be described in detail.

By sharing the standard data register (cf. 2 ) may be the interface adapter 2 be extended to 16-bit accesses. This is the address decoder 17 to modify that, too an address assignment CS1- = 1 and CS0- and DA2, DA1 DA0 = 0 leads to the activation of a register select line which is another port address decoder 28 is downstream. In an arrangement according to 19 become the relevant IO ports 35 connected to all data bus lines DD15 ... 0.

It There are peripheral devices that occupy a larger address space (eg, 64 kbytes and more). To support such address spaces, both E-A ports or port registers as well as other standard registers as additional address registers be used.

20 shows the use of the previously unused function feature register (see 2 and 3 ) as an additional address register. For this purpose, the address decoder 17 changed accordingly. The register is loadable with write accesses and provides up to 8 bits, which can be used to extend the port address. To these address lines are designed accordingly Portadreßdecoder 28 connected (cf. 15 ).

In 21 is represented as a ram 36 can be connected, which has a storage capacity of, for example, 64 kbytes. The access width is one byte. As EA ports are (see. 19 ) a bidirectional 8-bit data port 37 and a 16-bit address register 38 intended. The address register 36 is loaded via data register accesses. A program-side memory access consists of loading the address and the subsequent data access. To speed up accesses to successive addresses, the address register 38 be designed as a counter. In the case of data accesses (selection via PORT RAM DATA), each pulse on the lines DIOR- or DIOW- then causes the contents of the address register 38 increased by one.

22 shows a further development of the solution of 21 , Here are some IO ports as data ports 39 , Addressports 40 and control ports 41 designed and with the connectors (bus slots) of an I / O bus system 42 connected. The signal games of the I / O bus system 42 are accessed by the program on the I / O ports 39 . 40 and 41 emulated (emulated). The typical access procedure: transfer address - set access type - access (with data transport). With the EA bus system 42 it will typically be one of the industry standard bus systems, z. B. the usual in conventional PCs ISA bus or the PCI bus. It goes without saying that the access emulation can not achieve the data rate of "real" bus systems, but the purpose of such an arrangement is, above all, to support the use of special peripheral plug-in cards (measuring and testing technology, process control, etc.) In cases where it is less about the absolute data rate, but especially on low latencies and easy access from the application software (response via simple port drivers, no conflicts with caches, with the virtual memory of the operating system, with Bus bridges, etc.).

In typical control applications, it is often necessary to set individual bit positions of the I / O ports to zero or to one on the program. While many microcontrollers have corresponding commands (eg SET BIT, CLEAR BIT), such functions must be emulated on the PC in the software. The 23 to 26 illustrate a development of the interface adapter 7 , which makes it possible to support such single bit accesses on the hardware side. For this purpose, one of the standard register addresses (cf. 2 ) exploited. According to 23 In the case of a write access to this register address, the port address, the desired assignment of the selected bit (bit value) and the bit address are transmitted in the respective data byte. As a result, a single access is sufficient to set each bit in each of the ports to zero or to one. A typical application: the software controls a data transfer. For this, the data port address was entered in the device and head selection register 26 entered. Such data transfer processes usually still require the switching of control lines. This can be done with the here described single bit accesses. Since it is not necessary to do this, especially the device and head selection register 26 reload (port selection), results in a higher speed of data transmission.

In the example of 24 the address of the function attribute register (cf. 2 ) used to initiate the bit accesses. For this purpose, a corresponding address decoder 43 the selection input of a selection circuit (multiplexer) 44 downstream of the address decoder 17 is upstream. The data bus lines (DD2... 0) provided for bit addressing are connected to a bit address decoder 45 connected via the OR gate 46 Biterlaubnisleitungen 47 are downstream. The further circuit arrangement of the Portadreßdecodierung results from the comparison with 15 ,

If a corresponding access (with the address of the function feature register) is executed, then the address decoder switches 43 (BIT ACCESS) via the multiplexer 44 instead of the outputs of the device and head select register 26 the data bus lines DD2 ... 0 to the address decoder 17 , Furthermore, the bit address decoder excites 45 via the OR gates 46 the relevant permit authority 47 , If no bit access takes place (BIT ACCESS inactive), the OR gates are used 46 all permit permission lines 47 activated, so that in the concerned the ports all bits are written simultaneously.

25 shows a bit position of a modified for single bit access universal I / O ports (see. 18 ). The data inputs of the register flip flops 29 . 30 is a bit-selection multiplexer 48 upstream, the clock signal inputs are via blocking gates 49 with the respective outputs of the Portadreßdecoder 28 (see. 15 ) connected. In the case of single-bit access (BIT ACCESS active), the data bus line DD3 is switched to all data inputs so that their occupancy (cf. 23 ) is taken over into the selected flip-flop. The flip-flop selection is made via the blocking gate 49 by conjunctive linking of the respective permit authorization line 47 with the respective output of the Portadreßdecoder 28 , In the case of single-bit access, both the bit and the port selection are determined by the respective data bus occupancy (cf. 24 ). Otherwise, via the OR gates 46 (see. 24 ) All bit select signals 47 active, so that then the entire register is loaded at once.

One particular advantage of this interpretation is that the setting and delete of bits not on operations the type of reading - changing - writing back (Read - Modify - Write) is returned ( as this z. B. is common in many microcontrollers). Thus one can Set and delete accesses harmless completely follow each other (eg to a certain pulse pattern to produce). On the other hand, it is necessary before each bit change only the pin assignment read back, so it may u. a. happen that - at fast Access sequences - the previously issued occupancy at the subsequent reading not yet correct has set (due to the capacitive load on the terminals), that is wrong read back becomes.

The arrangement of 24 can according to 26 to be able to read the port selected for single-bit access.

The arrangement of 24 is a portaddress holding register 50 extended that the multiplexer 44 upstream. It is then loaded when a write access is made to the standard bit address selection register address (BIT ACCESS). In the arrangement of 26 must the port address keep register 50 be a latch register, so that already during the writing process each bit position to be written can be decoded. Upon read accesses to said register address, the address decoder becomes 17 over the multiplexer 44 on the in port address records 50 stored port address switched. In such access the entire port occupancy is read. Querying single bits is a matter of software. However, the query takes place exclusively inside the processor (in the PC) and requires - at the working speeds of today's processors - only little time. The advantage of the arrangement according to 26 consists mainly in that a reloading of the device and head selection register 26 is not required to address a port intended for single bit operations.

In practice, it is often beneficial if the software can detect what kind of interface adapter 7 connected. This can be done with the interface adapter 7 according to 27 with a read-only memory 51 equipped with some of the I / O ports (cf. 21 ). The read-only memory 51 contains identification data, the type and equipment of the respective interface adapter 7 mark. It is important that the software uses the read-only memory 51 can be found in all corresponding adapter types.

In a first embodiment is the read-only memory 51 accessible in all interface adapters via the same port addresses. In very simple adapters contains the read-only memory 51 just a single byte representing a kind of type number of the interface adapter. The arrangement of 27 then simplifies to a simple data port 37 which can only be read and switches the said fixed value to the data bus lines DD7... 0 in the case of read accesses.

In a further embodiment, fixed standard register addresses are used to access the read only memory 51 access. For this purpose, for example, the address of the standard error register (see. 2 ) be used.

An in 28 shown modification sees accesses to the read-only memory 51 only after the initial reset before. For example, the hardware reset or the blocking line switches 16 a permit flip flop 52 on, which gives access to the read-only memory 51 releases. After retrieving the identification data, the software may issue the permission flip flop 52 delete again (to free the port addresses for the normal functions), z. B. by performing a write access to a corresponding port address.

Will the interface adapter 7 according to the 29 and 30 trained so it is possible to use an interface cable next to the interface adapter 7 two drives - or any other standards compliant device - 4 and 53 to operate.

In a typical configuration, drive works 4 as master. interface adapter 7 and drive 53 Both are configured as slaves. At the interface 3 can only work with one of these facilities at a time. Therefore, the actual control signals of the interface via the In terfaceadapter 7 to the drive 53 guided. Will with the drive 53 worked, so the interface adapter 7 the control signals to the drive 53 by. Used with the interface adapter 7 worked, the control signals remain at the interface of the drive 53 inactive. It's all those control signals via the interface adapter 7 to lead by both bodies 7 . 53 be shared. In the example, these are the write and the read control signal DIOR and DIOW and - in the reverse direction - the interrupt request signal INTRQ. (That the interface adapter 7 Interrupt requests is not described here. However, interruption initiation by various types of peripheral devices has long been a prior art.)

A suitably designed adapter contains according to 30 the already described signature recognition circuit 19 with connected blocking line 16 , The control signals DIOW DRV and DIOR DRV and the interrupt request signal INTRQ DRV of the drive 53 are over barrier gates 54 or a selection circuit (multiplexer) 55 with the corresponding lines of the interface 3 connected. lock gate 54 and multiplexers 55 are to the blocking line 16 connected. With active blocking line 16 be the signals of the drive 53 to the interface lines 3 connected through. The drive 53 is active, the interface adapter 7 is inactive. To the interface adapter 7 to activate, a corresponding signature must be transferred - with write accesses. Then becomes blocking line 16 inactive. Thus, the control signals remain at the interface of the drive 53 inactive. Now the software can work with the interface adapter 7 work. To the interface adapter 7 disable it again (and thus the drive 53 re-enable), perform a special IO access which, similar to the hardware reset, resets the signature detection circuit 19 causes. For this purpose, the reset input of the signature recognition circuit 19 a disjunctive link of the hardware reset signal to the output of a disable decoder 56 upstream. In the example, the deactivation decoder is 56 is designed to become active when a write access to the address of the device and head select register 26 he follows. The wiring of the corresponding selection line 27 (DH ACCESS) results 14 ,

The arrangement according to 30 acts so that after resetting the drive first 53 is active and thus can be taken into account by the configuration software.

In the training according 31 can work together with the interface adapter 7 multiple drives or other devices connected to an interface. For this purpose, each drive two locking gates 54 provided that a drive address decoder 57 are downstream. The interrupt request lines are connected to a selection circuit (multiplexer) 58 connected to the selection circuit 55 is upstream. The address inputs of the drive address decoder 57 and the selection circuit 58 are to a device address register 59 connected, which can be designed either as a standard or as a port register.

At one time you can only work with one drive. To select a drive, the interface adapter must be selected (if necessary by means of a signature output) to register the device selection 59 to be able to load. Typical applications include the connection of so-called. Flash drives and an optical drive (CD / DVD), the latter is mainly used to new software, changes u. to install. Like. However, not only drives, but also further interface adapters according to the invention can be connected downstream of such an interface adapter.

• 1. Festwert = 0: Interfaceadapter ist Slave.
• 2. Festwert = 1: Interfaceadapter ist Master.

Sometimes it is convenient to have an interface with no drives, but more than one interface adapter 7 to join. This allows almost unlimited expansion of PCs with commercially available and cost-effective ATA controller cards. 32 shows a development of the arrangement of 15 , which makes it possible to configure the interface adapter either as a master or as a slave. Here is the permission input of the address decoder 17 precedes an antivalence association with a configuration input (MASTER / SLAVE SELECT). The configuration input is wired with a fixed value. The mode of action:

• 1. Fixed value = 0: Interface adapter is slave.
• 2. Fixed value = 1: Interface adapter is master.

For configuration control according to 32 The standard selection signal CABLE SELECT can also be used. As in 32 indicated, it is to connect inverted to said antivalence link.

33 shows how by continuing the arrangement of 20 several interface adapters can be addressed on one interface. Only part of the higher-order address bits are used for IO addressing in the interface adapter. The remaining part is controlled by a comparator 60 with a fixed adapter address 61 compared. The output of the comparator 60 is the permission input of the address decoder 17 upstream. The interface adapter is selected when the address of the fixed adapter address loaded into the address register 61 corresponds (selecting devices by address comparison is known per se and need not be described in detail).

The 34 and 35 show how the extension of access parameters (48-bit addressing) provided in newer versions of the ATA / ATAPI standards can be exploited to increase the width of the individual ports or to address additional ports.

34 illustrates the operation of the extension described in the standard. Multiple registers are implemented as two-byte depth shift register buffers (FIFOs) to accommodate longer parameter specifications. The first write access loads the higher-order byte, the second one the lower-order byte. When reading, one of the two bytes is read via the HOB bit in the device control register (cf. 3 ).

For writing in registers of I / O ports is the principle of 34 not directly applicable, since the registers are loaded successively with two different values. In a development according to the 35 to 37 Therefore, the registers of the I / O ports become a FIFO buffer 62 (typically a shift register) upstream. Each write access to a correspondingly assigned standard register address relates to the FIFO buffer 62 , Write to the device and head selector register 26 causes the acquisition of the FIFO content into the via the Portadreßdecoder 28 selected I / O registers. The depth of the FIFO may be greater than specified in the ATA / ATAPI standard. For each of the standard register addresses provided for addressing I / O ports, a FIFO buffer may be provided 62 be arranged.

• 1. eine einzige der standardgemäßen Registeradressen wählt den FIFO-Puffer 62 aus (Zugriffe auf andere Adressen werden so ausgeführt, wie bisher beschrieben),
• 2. mehrere der standardgemäßen Registeradressen wählen jeweils einen FIFO-Puffer 62 aus.

The writer permission signal FIFO in 35 may be any address select signal from one of the decoders 17 or 28 (see the 14 and 15 ) is delivered. Here, various embodiments are possible, for. B .:

• 1. One of the standard register addresses selects the FIFO buffer 62 off (accesses to other addresses are carried out as described so far),
• 2. Several of the standard register addresses each select a FIFO buffer 62 out.

After loading the FIFO buffer 62 the transfer takes place into the respective selected register.

The 36 and 37 show an example of the formation of the permission signals P_REG 1, P_REG 2, etc. The acquisition takes place by a write access to the standard device and head selection register 26 , wherein in the associated data byte, the relevant register address and possibly a permission signal (Parallel Write Enable) is supplied ( 36 ). The permission signals P_REG 1, P_REG 2, and so forth are set according to 37 from a special decoder 63 formed immediately downstream of the data bus lines, so that they at the registers (see. 35 ) are present before the low-high edge of the write pulse (DIOW-) takes effect.

These Design allows it, in an interface adapter both registers with conventional access (8 bits) as well as those with parallel access (16 bits and more) provided.

When writing bytes according to 36 the previous assignment of the device and head selection register 26 Preserve, so is the address decoder 26 (see. 15 ) with the inverted output of the decoder 63 to connect.

The 38 and 39 illustrate an alternative development that does not require FIFO buffer. The EA registers become, as indicated by 15 described via port address decoder 28 addressed. The in the standard device and head selection registers 26 held port address is but by an address counter 64 extended, with the address counter 64 the low and the device and head select registers 26 provides the higher-order bits of the port address ( 39 ).

In the example of 38 carries the address counter 64 three bits to the port address. It will be on every write access to the device and head select register 26 deleted (DH ACCESS and DIOW). For all other accesses, the respective control signal (DIOR, DIOW) acts as a counting clock (increase by one). In the device and head selection register 26 a previously unused bit position can be used to count the address counter 64 to allow or prevent (Extended Access).

In both interpretations (see 35 and 38 ) registers to be read are connected to selection circuits, e.g. B. to multiplexer. In the execution according to 35 For example, a standard register or an I / O register may be dedicated to holding the selection address. If it is only a 1-out-of-2 selection, the HOB bit can be used in the device control register in the standard sense (cf. 34 ). If several I / O registers are to be selected, for example, further (in themselves unused) bit positions can be used in the device control register to hold the selection address. In the execution according to 38 the selection inputs of the multiplexers are the address counter 64 downstream.

The 40 to 59 illustrate advanced interface adapters, which are not addressed by direct dial-up access, but via standard command protocols. This design makes it possible to exploit standardized operations that exceed the simple pro programmed input and output (PIO operation) (bus master and automatic DMA mode (ADMA)). Furthermore, it becomes possible to connect interface adapters according to the invention via a standardized high-speed bit-serial interface known as Serial ATA (SATA) (High Speed Serial ATA Attachment or AT Attachment-8 Serial Transport (ATA8-ST)).

According to 40 This interface twists two standard register sets with each other. One is in the controlling computer (host), the other is in the device. The software can only access the register set in the host (shadow register).

A data exchange between both register sets does not take place with every access, but only within the framework of standard protocols of the command execution. If the host causes the execution of a command by entering the command code in the standard command register, the entire content of the register file is transferred to the device. If the device has finished the command execution, then the - now updated - content of the register set is transmitted to the host. The data transmission is organized in the form of so-called Frame Information Structures (FIS). The 41 and 42 show the structure of FIS data blocks for register transports ( 41 from the host to the device, 42 from the device to the host). The information transfer encloses all standard provided registers including the extensions according to 34 (in the 41 and 42 marked "erw.").

to optional data transmission only the registers LBA low, LBA medium, LBA high and sector number come up in addition to their extensions (ext.) in question. These are four register positions or eight bytes. All other registers may only be used in a standard way be used.

The following explanations refer to that on the device side a standard parallel ATA interface is present (corresponding interface converter are commercially available).

One inventive interface adapter with SATA connection can So still a conventional Have interface. It is thus suitable for both types of interface.

43 shows how one of said four register positions can be exploited for universal EA purposes.

About a register position are 16 Outputs and 16 Entrances accessible. Write accesses initially concern a FIFO buffer 62 , the two output registers 64 . 65 are subordinate. The input is made via a selection circuit 66 with downstream bus coupling stage.

After the transfer of the register contents in a FIS structure according to 41 the registers are filled one after the other. REGn WR symbolizes the write control for the register address n, the z. B. with a permission signal REG n from the address decoder 17 (see. 14 ) is realized in conjunction with the write signal DIOW of the parallel interface (DIOW at the clock input, REG n at Takterlaubniseingang; 35 ). The register contents are thus transferred to the FIFO buffers 62 , Finally, the command register is loaded. This starts the command execution. This consists here of the transmitted data bytes from the FIFO buffers 62 in the output registers 64 . 65 to take over (write pulse CMD WR).

When the command execution is finished, the new device-side register contents are transferred to the host. To do this, register by register is read to obtain a FIS structure according to 42 together. Reading the extended registers requires two accesses. The HOB bit in the device control register is used for byte selection. In the example of 43 the two bytes are sent via the selector circuit addressed by the HOB bit 66 successively switched to a bidirectional data bus (DD7 ... 0) (register selection signal REGn RD).

44 gives an overview of all four register positions. This can total 64 Outputs and 64 Inputs are supported.

In a development, similar to the above-described, the Kopfauswahl- or LBA bits of the device and head selection register 26 used several arrangements according to 44 to operate. Because the field in question is in the device and head selector register 26 four bits, a maximum of 16 such blocks can be provided (ie a total of 1024 inputs and 1024 outputs). In each case, such a block is selected at a time. Therefore, up to 16 register positions can each have a FIFO buffer 62 share ( 45 ). In the example, the first (via the Device and Header Selection Register 26 adresierte) block the output registers 64 . 65 and the selection circuit 66 , The second block consists of the output registers 67 . 68 and the selection circuit 69 ,

46 shows the structure of a bit position of a universal I / O port similar 18 ,

In the example are directional registers 29 and data registers 30 each assigned to a register block. Via the device and head selection register 26 can thus on the one hand all direction registers 26 and on the other hand all data registers 30 selected who the (direction register selection via PORT_SEL 0, data register selection via PORT_SEL 1). Port selection signals PORT_SEL 0 and PORT_SEL 1 are from one of the port address decoders 28 ,

47 and 48 illustrate the device and head selection registers 26 with downstream port address decoders 28 as well as the formation of the access control signals of Kom mandoauslösung and state read. The arrangement largely corresponds to the 14 and 15 , 47 shows one of the port address decoder 28 . 48 all four. They are the address decoder 17 (see. 14 ) downstream.

CMD WR is a general write pulse which is formed during write access (DIOW to the address of the command register) Usage: among other things, for transferring the data from the FIFO buffers 62 in the output registers 64 . 65 etc.

STATUS RD is a read signal which is formed during read access (DIOR) to the address of the command register (when reading = status register). Usage: to read the status register ( 49 ).

CMD RD is a general read signal that is applied to the other registers of the command register block during read access (DIOR) (cf. 2 ) is formed. Usage: among other things for connecting the output assignments to the data bus lines ( 50 ).

49 each illustrates a bit position of the selection circuits 66 and 69 (see. 45 ). Depending on which of the port selection signals PORT_SEL 0, PORT_SEL 1 the relevant address decoder 28 has activated, when the read signal CMD RD is active, either the selection circuit 66 or the selection circuit 69 switched to the data bus.

The 50 and 51 show the occupancy of the state and device control registers. All the standard bit positions are initially set. Then follow the bit assignments that are typically supplied by the interface adapter. Due to the very simplified operation compared to drives, not all bits are important. Therefore, only these bit positions are briefly described: BSY (Busy) indicates the busy state (command in progress). DF (Device Fault) indicates a device error. Interface adapters with built-in error detection (time control, parity check on inputs or the like) can activate this bit position. HOB (High Order Byte) is used for byte selection when reading (cf. 34 ).

more sophisticated Interface adapters (for example, with built-in application circuits) may continue to work support the bits DRDY and NIEN. DRDY (Device Ready) indicates the readiness for operation. adapter the reset need a lot of time (milliseconds and more), while this bit can be activated. DRQ (Data Request) is relevant if the interface adapter a "real" data transfer (about the standard data registers) supported. NIA (Interrupt Enable) is used when the interface adapter Trigger interrupts can (n = 0: Interrupt trigger permissible NIEN = 1: Interrupt trip ) Prevented.

The device control register is controlled similarly to the device and head selection registers 26 , ie according to 14 but with different address decoding (cf. 2 ). In simple interface adapters (without data transfer), it is sufficient to know the bit position 7 (HOB).

Based on 52 to 54 Let's first briefly describe the principle of command execution. As a prerequisite for executing a command, the interface adapter must be ready (BSY = 0, DRDY = 1). First of all, the required parameters (selection information, functional characteristics, etc.) must be loaded into the corresponding registers ( 52 ). The last byte of the command code is written to the command register. Then the interface adapter is "busy" (BSY = 1), and the command execution begins ( 53 ). If the interface adapter is ready to accept data (when writing) or to supply data (when reading), it sets BUSY to 0 and DRQ to 1 (data request). Then the data transport ( 54 ; here is a reading process shown). The data transport can be initiated by polling (condition: BSY = 0, DRQ = 1), by interrupt signaling, or by providing a DMA request. The actual transport then consists of consecutive PIO or (Ultra) DMA accesses. The end of the command execution is indicated by BSY = 0 and DRQ = 0. Typically, an interrupt is triggered. The host reads the state register to see how the data transfer has expired (using bits ERR and DF). If the ERR bit is set, reading the error register gives more accurate information about the nature of the error.

55 shows switching means for command execution in a low-cost interface adapter. The command sequences are only used to transport register contents (forwarding of the register contents from the host to the outputs, conversion of the input assignments into register contents, which are transported to the host). For this purpose, command codes are used which are not connected to a data transmission (Non-Data Command Protocol). In such cases, it is sufficient to write the BSY bit with the command code (CMD WR) for a short time (a few hundred ns) to indicate to the host the acceptance and execution of the command.

The command register 70 is a command decoder 71 downstream. The status register consists of the BSY flip-flop or a time stage 72 and a bus coupling stage 73 , which, in the case of corresponding read accesses (STATUS RD), determine the status assignment (BSY + fixed assignment according to 50 ) switches to the data bus lines DD7 ... 0. In the simplest case, the time step works 72 like a monostable multivibrator. It is expediently designed such that it deactivates BSY only when the effects of the input assignments transmitted with the command are present at the inputs of the interface adapter (finished message). 56 shows the structure of a corresponding circuit.

The BSY flip-flop is a time counter 74 downstream, at whose outputs a comparator 75 is connected. The comparator 75 is still a selection circuit 76 preceded by the command decoder 71 is controlled. If the interface adapter is inactive (BSY = 0), then the time counter becomes 74 held in the reset state. By loading the command register 70 it is released (BSY = 1) and begins to count. Depending on the command, one of several time values is selected via the selection circuit 76 to the comparator 75 turned on. Corresponds to the content of the time counter 74 the said time value, is over the comparator 75 resets the BSY flip-flop and terminates the command execution.

The 57 to 59 illustrate various ways to influence the command execution time.

According to 57 is the command register 70 Downstream command decoder 71 on the time step 72 recycled. Thus, each command can be assigned a specific execution time. For this example, the selection circuit 76 wired with appropriate fixed values.

58 illustrates the program-side adjustability of the command execution time. For this purpose, at least one of the output registers is designed as a time keeping register and at the time step 72 returned (eg to one of the inputs of the selection circuit 76 ) Connected.

59 shows how the command execution time can be made dependent on the arrival of certain input assignments. BSY remains active until a certain input assignment occurs (wait state). The expected assignment can be detected with a combinatorial network (fixed decoding). In some applications, it is only necessary to wait for a single signal assignment (for example, for a strobe signal of an interface to be controlled). Then a simple selection circuit is enough. 59 shows a flexible design in which the detection circuit 77 for the expected input assignment contains a comparator, which is connected downstream of an output register. If the assignment of the inputs corresponds to the contents of the output register, the BSY flip-flop is reset.

Waiting for input assignments can be combined with a time out control. If the expected input assignment remains off, BSY is deactivated if a certain time has elapsed. To support this mode, for example, the circuit of 56 be modified so that the reset input of the BSY flip-flop, the output signals of the comparator 75 and the detection circuit 77 be preceded by a disjunctive link. The detection circuit 77 terminates the command when the corresponding condition arrives at the inputs, the comparator 75 at the expiration of the time interval.

The Influencing Command Execution Time Over Time or over operations at the E-A interfaces it, standard precautions exploit in the host to control latency and low-latency Execute reaction times. It becomes possible, for example, control procedures from the ADMA hardware in the host interface controller leave without the Processor must intervene. The software has to do this only the corresponding command sequences (Command Parameter Blocks) deploy in memory. Then the commands can be independent of Processor executed (the ADMA mode is in the relevant texts of the standardization body) in detail described; see. For example, the ATA / ATAPI Host Adapter Standard T13 / 510). In this way, you can also hard real-time requirements comply. Limited on the other hand, one is limited to a purely programmed input and output with individual application-side E-A accesses (Port I / O) under Control of a modern operating system, this is not possible. Example: it is a signal assignment for the duration of 20 μs to generate (pulse pattern). The naive programming: first OUT function (Pulse output) - wait - second OUT function (output of the original or next Occupancy). In the time between both OUT functions but can the system intervene and z. B. another application program Allocate computing time (time slicing). It can then be that one generated pulse lasts 10 ... 20 ms and longer.

The 60 to 62 illustrate developments of the interface adapter, which support not only register, but also data access. Such a design is useful if there are EA ports over which to transport larger data blocks (data transfers are less important for control processes with alternating input and output accesses). Simple adapters are designed for programmed data access. For this purpose, the Areßdecodierer 17 to the decoding of the data register address (cf. 2 ) to expand. The data register accesses are carried out with a width of 16 bits (occupancy of the data bus lines DD15... 0); otherwise they do not differ from the previously described register accesses. Interface adapters, which are addressed via standard command protocols, use the transmission processes provided for this purpose (data-in and data-out protocols). These processes are described in detail in the interface standards. Corresponding circuits are included in the control circuits of the hard disks, CD-ROM drives, etc. A detailed representation of the hardware is therefore not required.

60 shows the connection of I / O ports to the data register, here from an output register 78 and an input register 79 consists. If inputs from several I / O ports are provided, then the input register is 79 a selection circuit 80 upstream. An address register is used to select the respective I / O port 81 , This is one of the other registers from the standard register set (eg, the device and head select register 26 ).

to data transfer become suitable standard drive commands used (eg READ SECTORS and WRITE SECTORS). The data transmission is initiated with the loading of the register file and with the pickup the register file assignment completed.

Important is that the Data transfer processes exactly comply with the specifications of the standard. This is typically In addition, always transfer entire sectors of 512 bytes. Possibly. must the Interface adapter additional Append bytes (Input) or excess bytes lose weight and let go (output).

Independent I / O register sets can be provided for each command protocol (non-data and data-in / data-out) ( 61 ). Thus, in an interface adapter, both optional I / O control functions and data transfer functions can be combined. The arrangement corresponds largely 45 However, the registers and selectors do not have bit positions of the device and head select register 26 but selected via the command code. If it is a command without data transfer, will be on the registers 82 and on the selection circuit 83 accessed, the command is associated with a data transfer to the registers 84 and on the selection circuit 85 , In both cases, bit positions z. In the device and head selector registers 26 be used to each one of several arrangements of registers 82 / 84 and selection circuits 83 / 85 to address (as already based on the 43 to 49 ) Described.

If the previously available as free designated register of the standard register set in commands with data transmission still free (for general E-A purposes) can be used depends on it as the data transfer commands be designed in detail. In the simplest case, one limits to a fixed byte count for each transmission direction (eg one sector = 512 bytes each). Then you can the said register free use (but must in the host-side software on this convention consideration to take). On the other hand, should the interface adapter be much like a drive behave, the default to use registers are not more at leisure. For example, if the transfer supported by several sectors the sector number register is to be used by default. By contrast, the LBA registers (sector number, etc.) remain the same usable for E-A purposes.

The arrangement according to 60 provides direct data transport between the interface adapter and the I / O ports. However, the connected devices often can not support the data rate of the interface. The way out is to provide appropriate buffer memories ( 62 ). To the data bus lines of the interface are a program buffer 86 , an output buffer 87 and an input buffer 88 connected. The program buffer 86 is a controller 89 downstream. The buffers may be in the form of FIFOs or RAMs (sequential or random access). If it is merely a passing of the bytes, then the program buffer 86 omitted, and the buffers 87 88 can be designed as FIFOs. The controller 89 then becomes a sequencer that supports the FIFO signal plays and the respective I / O interfaces. In an alternative design, all buffers are RAMs, and the controller 89 is a program-controlled device. For this purpose, z. B. one of the commercially available microcontroller can be used. It is also possible to use several of the buffers 86 to 89 into a single RAM arrangement (data buffer + program buffer or a single universal buffer memory).

• 1. Füllen des Programmpuffers 86 mit dem jeweiligen E-A-Steuerprogramm (Ausgabekommando).
• 2. Füllen des Ausgabepuffers 87 mit den auszugebenden Daten (Ausgabekommando).
• 3. Anstoßen des E-A-Programms. Diese Funktion kann z. B. mit dem letzten Ausgabekommando kombiniert werden, das den Ausgabepuffer 87 gefüllt hat.
• 4. Abholen eingegebener Daten aus dem Eingabepuffer 88 (Eingabekommando). Diese Funktion kann beispielsweise vom Interfaceadapter durch Interruptauslösung angefordert werden (das vorhergehende Kommando bleibt solange aktiv, bis die entsprechenden Wirkungen eingetreten sind).
• 5. Ggf. wiederholter Durchlauf der Funktionen 2 bis 4. Solche Durchläufe können über entsprechende ADMA-Kommandoketten gesteuert werden so daß sie weitgehend unabhängig vom Prozessor (des Host) ablaufen.

It is possible to control the EA before largely into the controller 89 of the interface adapter. The controller 89 can take over, among other things, the addressing of the buffers and the selection of the I / O ports. For example, such an interface adapter can be used as follows:

• 1. Fill the program buffer 86 with the respective I / O control program (output command).
• 2. Fill the output buffer 87 with the data to be output (output command).
• 3. Initiate the EA program. This function can, for. B. combined with the last output command, the output buffer 87 filled.
• 4. Retrieving input data from the input buffer 88 (Input command). This function can, for example, be requested by the interface adapter through interrupt triggering (the previous command remains active until the corresponding effects have occurred).
• 5. If necessary repetitive run of functions 2 through 4. Such passes can be controlled via appropriate ADMA command strings so that they are largely independent of the processor (the host).

The autonomous control of E-A processes via microcontroller is known per se. Therefore, on the description of details be waived. The connection via a ATA interface has the advantage of significantly lower latency and Reaction times compared to usual E-A interfaces (serial, parallel, USB, network, etc.). The software overhead for response Such an interface is significantly lower than USB or Ethernet. It is also possible the support provided in the host and acceleration arrangements (bus master and ADMA operation). U. a. can triggered by the interface adapter Interrupts are served in ADMA mode without the processor must intervene.

63 illustrates the structural design of an interface adapter that can be used instead of a drive in conventional PCs.

The interface adapter 7 has the outer dimensions of a standard drive. He is here in a drive bay 90 in a mounting frame 91 is inserted. The ATA interface is via the connector 92 connected. Connectors 93 serves to connect the devices to be controlled 9 (see. 5 ). Such an arrangement makes it possible to convert any x-any PC temporarily to a microcontroller, z. B. for teaching and testing purposes.

• 1. die gesamten Ressourcen und funktionellen Eigenschaften des PCs können zur Lösung der Anwendungsaufgabe und zum Fehlersuchen (Debugging) herangezogen werden,
• 2. es kann mit der im PC-Bereich üblichen Entwicklungssoftware programmiert werden (diese ist zumeist besser ausgestattet als die typischen Etwicklungsumgebungen der Mikrocontroller, ist oft kostengünstiger und erfordert keine besondere Einarbeitung),
• 3. es entfallen die Download- und Programmierzeiten.

The advantages over the use of the known so-called starter kits (to be connected to the PC boards that contain a microcontroller) consist in the following:

• 1. the total resources and functional characteristics of the PC can be used to solve the application task and to debug
• 2. It can be programmed with the usual development software in the PC area (this is usually better equipped than the typical development environments of microcontrollers, is often less expensive and requires no special training),
• 3. It eliminates the download and programming times.

in the Unlike the simulators of popular microcontroller development environments can the PC over the built-in interface adapter at full speed (in Real time) to work on real peripheral hardware.

On so equipped PC pre-proven application solutions can - there in Real-time debugged - easily on microcontrollers or on small ones Transfer PC modules (Embedded PCs) become.

• 1. Interfaceadapter mit E-A-Ports. Die über den Steckverbinder 93 geführten Signale sind E-A-Signale.
• 2. Weitergabe der ATA-Schnittstelle. Der Interfaceadapter wird gar nicht wirksam. Das ATA-Interface wird lediglich vom Steckverbinder 93 zum Steckverbinder 93 weitergereicht. Steckverbinder 93 ist gemäß ATA-Standard belegt.

In an advantageous embodiment, the connector corresponds 93 a standard ATA connector. The interface adapter has two modes:

• 1. Interface adapter with I / O ports. The over the connector 93 Guided signals are I / O signals.
• 2. Transfer of the ATA interface. The interface adapter does not take effect at all. The ATA interface is just the connector 93 to the connector 93 passed on. Connectors 93 is assigned according to the ATA standard.

64 illustrates a simple interface adapter with four I / O ports 94 (A ... D). Each of the I / O ports 94 is according to 65 built up. The circuit largely corresponds to that of 18 , The only difference is that here the read data path from the ports via a selection circuit 95 , a synchronization register 96 and a common bus coupling stage 97 leads to the data bus of the ATA interface. The EA ports 94 be in the manner already described (see 14 to 17 ) addressed.

The in the 64 and 65 arrangement shown is extended by switching means for interface switching. 66 shows an exemplary assignment of the connector 93 using as double-row pole connector with 40 Terminals is formed. Which signals on the connector 93 present, determines the interface signal MODE SELECT.

MODE SELECT = 0: ATA operation (transmission of the ATA interface). Is connected to the connector 93 If an ATA drive is connected, MODE SELECT is connected to ground (standard assignment of this connection). The ATA operation is thus automatically set when a drive is connected.

MODE SELECT = 1: Port operation. Connected facilities to be controlled 9 Do not connect the signal, so that the correct operating mode is set automatically in this case as well.

The 67 and 68 illustrate a first embodiment. The presentation is limited to the switching between the ports A and D on the one hand and the ATA data bus (DD15 ... 0) on the other. The switching of signals having only one direction is not particularly shown, since it can be solved in an obvious manner with selection circuits (multiplexers) or tri-state coupling stages.

67 shows the changeover in output direction. For ATA operation, all ports are 94 inactive and high-impedance (the connections can thus be occupied elsewhere). This is achieved by the reset inputs of the direction registers 29 (see. 65 ) are connected to the inverted MODE select signal MODE SELECT. If the interface adapter is set to ATA mode (ATA MODE), this is done via bus coupling stages 98 the data bus is switched to ports A and D if a standard write access (ATA WRITE ACCESS) takes place.

To switch the read data path is according to 68 between synchronization registers 96 and bus coupling stage 97 a selection circuit 99 arranged. This is used to control the connections of port A to the data bus. For the forwarding of the port B is a Buskoppelstufe 100 intended. select circuit 99 and bus coupling stage 100 are activated accordingly if a standard read access (ATA READ ACCESS) takes place.

The Conditions for enabling the appropriate control signals (ATA WRITE ACCESS, ATA READ ACCESS) result directly from the interface standard. It is therefore not necessary to describe them in more detail.

The basis of the 67 and 68 Interface switching described comes with selection circuits and bus coupling stages, so z. B. in typical CPLD or FPGA circuits can be accommodated. The disadvantage is the duration of this additional switching means.

A Alternative is so-called bus switch for interface switching use. These devices have field effect transistors in the signal paths, which act as a switch. They work in both signal flow directions (bidirectional) and have only a negligible propagation delay (z. Maximum 250 ps).

69 shows a corresponding arrangement. Between interface adapter 7 and connectors 93 is a selection circuit 101 arranged, which is constructed with such bus switch components. The selection input of the selection circuit 101 is with the mode select signal (MODE SELECT) of the connector 93 wired.

• 1. Interfaceadapter allein, Steckverbinder 93 im Port-Betrieb,
• 2. Interfaceadapter und Laufwerk 53, Steckverbinder 93 im Port-Betrieb,
• 3. Steckverbinder 93 im ATA-Betrieb (bloße Durchleitung),
• 4. Laufwerk 53 und Steckverbinder 93 im ATA-Betrieb.

In 70 is a further embodiment of an interface adapter according to 63 shown. The actual interface adapter 7 and the selection circuit 101 are through an ATA drive 53 added. The drive 53 is connected in the manner already described (see 29 to 31 ). Switching of use of the connector 93 is here from the interface adapter 7 controlled, which evaluates the mode selection signal MODE SELECT and accordingly energizes the selection signal IFSEL. A simple and universal design at the same time is to connect both signals to other program-accessible I / O ports in the interface adapter so that MODE SELECT can be queried and IFDEF can be set. Among others, the following operating modes can be set:

• 1. Interface adapter alone, connectors 93 in port mode,
• 2. Interface adapter and drive 53 , Connectors 93 in port mode,
• 3. Connector 93 in ATA mode (mere transmission),
• 4th drive 53 and connectors 93 in ATA operation.

In an advantageous embodiment, the drive 53 a flash drive (flash disk). This makes it possible that a slot according to 63 its own software - up to its own operating system - can bring, so that it is not necessary to install possibly necessary "exotic" software on the particular PC specifically.

71 shows a further use of an interface adapter according to the invention. For use in the field of embedded systems there are PC modules with particularly small dimensions (examples being the form factors PC / 104, ETX, X-Board and DIMM). Such modules typically only have interfaces that meet industry standards.

This in 71 The module shown contains a PC core 102 , an inventive Inter face adapter 7 , a system connector 103 and a configuration control device 104 , The system connector 103 complies with the respective industry standard (eg ETX, X-Board or DIMM). The PC core 102 is a known per se and on such modules arrangement of processor (CPU), control circuits (CTL) and memory means (RAM, ROM). The control circuits support a typical range of common interfaces (ISA bus, PCI bus, LPC, ATA, keyboard interface, USB, RS-232, etc.). On conventional modules, these interfaces are on the system connector 103 guided. Since none of these interfaces are provided for directly connecting any devices to be controlled, corresponding adapter circuits must be arranged outside the module (eg, on a base board). By installing an interface adapter 7 gets such a module the application characteristics of a real microcontroller (above all: a multiplicity freely programmable universal I / O connections, which over the system connector 103 are accessible). The typical use cases often require a certain mix of industry standard interfaces and general purpose / application specific I / O circuits. To support such cases of use are between PC core 102 and system connectors 103 selection circuits 101 (the basis of 60 described type), which continues with the EA signals of the interface 7 are wired. The selection control inputs of the selection circuits 101 are with the configuration control device 104 connected. Thus, at the system connector 103 an appropriate mix of universal I / O ports and industry-standard interfaces are provided.

• 1. Auswahl über Anschlüsse des Systemsteckverbinders 103, die feste Signalpegel liefern, um eine bestimmte Interfaceauswahl zu veranlassen,
• 2. feste Einstellung über Steckbrücken bzw. Wahlschalter,
• 3. programmgesteuerte Einstellung, z. B. über Steuerregister, die an eines der üblichen Interfaces oder an den Interfaceadapter 7 angeschlossen sind.

There are several options, the configuration control device 104 interpreted:

• 1. Selection via connectors of the system connector 103 that provide fixed signal levels to cause a particular interface selection,
• 2. fixed setting via jumpers or selector switches,
• 3. program-controlled setting, z. Via control registers connected to one of the common interfaces or to the interface adapter 7 are connected.

These Methods of configuration control are known per se and common practice (see Plug-in cards for PC bus systems, such as ISA or PCI), so that a more detailed description is not required is.

• 1. vergleichsweise Einfachheit (etwa gegenüber dem Anschluß an einen PCI-Bus),
• 2. direkte Zugänglichkeit über E-A-Zugriffe (geringe Latenz- und Reaktionszeiten),
• 3. Nutzbarkeit vorhandener Vorkehrungen (Busmasterbetrieb, ADMA),
• 4. ATA-Standards sind – infolge ihrer eigentlichen Bestimmung (Laufwerksanschluß) – Industriestandards mit längerer Lebensdauer und Verfügbarkeit (im Gegensatz beispielsweise zu den Steuerschaltkreisen und Steckkarten-Bussystemen des PC-Marktes).

The advantages of the interface adapter connected to an ATA interface 1 exist in such applications in the following:

• 1. comparatively simple (as compared to the connection to a PCI bus),
• 2. direct accessibility via I / O accesses (low latency and reaction times),
• 3. Usability of existing arrangements (bus master operation, ADMA),
• 4. ATA standards are - due to their actual purpose (drive connection) - industry standards with longer life and availability (as opposed to, for example, the control circuits and plug-in card bus systems of the PC market).

The comparatively simple circuits of the interface adapter 7 can be accommodated in low-cost CPLD or FPGA circuits. If you look on a module according to 71 a correspondingly rich equipped circuit before, so fit there also application-specific circuits. 72 illustrates the division of such a circuit into the actual interface adapter 7 , an application-specific, freely programmable area 105 and a connector 106 , This makes it possible, many circuits that are usually built on other circuit boards with elementary logic circuits in the freely programmable area 105 of the circuit. Such-typically-not-so-difficult-design tasks can be performed with elemental (often free) development environments. As an inventively designed interface adapter 7 Conflicts with the intended use of the ATA interface avoids serious design errors in the freely programmable range 105 Do not prevent starting and operating the system. For troubleshooting and testing, the hardware and software of the PC system can thus be fully exploited. In order to support the troubleshooting, can in the connection part 106 Testing, interrogation and recording circuits (eg

Test and holding register) are arranged, in turn, in the manner already described with the interface adapter 7 are connected, z. B. as additional input and output registers. (The introduction of test aids into programmable circuits is known per se and described, for example, in the manufacturer's application notes.) It is even possible to program the circuit yourself from the PC (troubleshooting, adaptation to changing requirements). For this purpose, the programming terminals of the circuit with a suitable industry standard interface (see. 71 ) connect to. Most CPLDs and FPGAs have a programming interface that complies with the JTAG / IEEE 1149 standard. It can be easily z. B. the usual parallel interface (IEEE 1284) downstream.

Claims (33)

Adapter arrangement for connection to a drive interface, which connects the controlling computer with a standard register set in the device to be controlled, wherein the individual registers of said register set are connected to an address decoder, which is connected downstream of the interface lines , characterized in that at least one of said registers EA port is formed. Arrangement according to Claim 1, characterized in that the address decoder ( 17 ) with a blocking line ( 16 ) is connected. Arrangement according to claim 1 and 2, characterized in that the address decoder ( 17 ) upstream blocking line ( 16 ) to a time step ( 18 ) is connected, which in turn is arranged downstream of the reset circuits of the controlling computer. Arrangement according to claim 1 and 2, characterized in that the address decoder ( 17 ) upstream blocking line ( 16 ) to a signature recognition circuit ( 19 ) connected. Arrangement according to one or more of the previous ones Claims, characterized in that only those of the standard registers are designed as E-A ports which are standard for reading and and write accesses are provided. Arrangement according to one or more of the preceding claims, characterized in that at least one of the standard registers is used as address register ( 26 ) to which the I / O ports are connected via a port address decoder ( 28 ) are connected downstream. Arrangement according to claim 6, characterized in that the Portadreßdecoder 28 are designed so that they only respond to port addresses greater than or equal to one and that the address register ( 26 ) is only accessible for write access. Arrangement according to claim 1 and 6 or 7, characterized that output register of E-A ports as additional address register are formed. Arrangement according to Claims 1 and 6 to 8, characterized that at least one of the address registers as a counter is trained. Arrangement according to Claims 1, 8 and 9, characterized in that some of the I / O ports are used as data ports ( 39 ), Address ports ( 40 ) and control ports ( 41 ) and with the connectors of an I / O bus system ( 42 ) are connected. Arrangement according to Claims 1 and 3, characterized in that the address decoder ( 17 ) a selection circuit ( 44 ) which is connected, on the one hand, to the standard address lines and, on the other hand, to some of the standard data lines of the interface, that a further bit of these data lines is a bit address decoder ( 45 ) and that at least one of the I / O ports is configured such that the clock-enable inputs of the register flip-flops ( 29 . 30 ) of the output registers with the outputs of said bit address decoder ( 45 ) and that the data inputs of the register flip-flops ( 29 . 30 ) Bit selection multipliers ( 48 ) are connected upstream. Arrangement according to claim 11, characterized in that the respective standard data lines with the selection circuit ( 44 ) with the interposition of a port address holding register ( 50 ) are connected. Arrangement according to Claim 1, characterized in that a read-only memory (A) is applied to some of the I / O ports ( 51 ) connected. Arrangement according to Claims 2 and 13, characterized in that the read-only memory ( 51 ) a permission flip flop ( 52 ), whose set input with the blocking line ( 16 ) is connected. Arrangement according to Claims 1 and 4, characterized in that the interface adapter ( 7 ) another body ( 53 ), with their standard access control and interrupt lines to conjunctive links ( 54 ) and selection circuits ( 55 ) of the interface adapter ( 7 ), that said conjunctive links ( 54 ) and selection circuits ( 55 ) via the blocking line ( 16 ) with the signature recognition circuit ( 19 ) and that the reset input of the signature recognition circuit ( 19 ) a disjunctive combination of the hardware reset signal with the output of a deactivation decoder ( 56 ) is connected upstream. Arrangement according to claim 15, characterized in that the interface adapter ( 7 ) Other facilities ( 53 ), each institution ( 53 ) provided blocking gate ( 54 ) to a drive address decoder ( 56 ) are connected to the selection circuit ( 55 ) another selection circuit ( 57 ) and that the address inputs of the drive address decoder ( 56 ) and the selection circuit ( 57 ) a device address register ( 58 ) are connected downstream. Arrangement according to claim 6, characterized in that the permission input of the address decoder 17 an antivalence link to a configuration input 59 upstream. Arrangement according to claim 6 or 8, characterized in that a part of the higher-order address bits to a comparator 60 connected to the other inputs with a fixed adapter address 61 are wired and that the output of the comparator 60 the permission input of the address decoder 17 upstream. Arrangement according to one or more of the preceding claims, characterized in that at least some of the I / O ports contain a FIFO buffer ( 62 ) is connected upstream. Arrangement according to Claim 19, characterized in that the permission signals of the FIFO buffers ( 62 ) downstream I / O ports to an additional address decoder ( 63 ) whose address inputs are connected to some of the standard data lines. Arrangement according to Claims 1 and 6, characterized in that the port address decoders ( 28 ) in addition to the standard register used as an address register ( 26 ) an address counter ( 64 ), said address counter ( 64 ) the low-order and the said address register ( 26 ) returns the high order bits of the port address. Arrangement according to one or more of the preceding claims, characterized in that the accept input of the standard command register ( 70 ) over a time step ( 72 ) with the standard state register ( 73 ) connected is Arrangement according to Claim 22, characterized in that the accept inputs of the I / O ports are connected to the accept input of the standard command register ( 70 ) and that the read permission inputs of the I / O ports are connected to the read permission input of the standard state register ( 73 ) are interconnected. Arrangement according to claim 22, characterized in that the standard command register ( 70 ) downstream command decoder ( 71 ) to the time level ( 72 ) is returned. Arrangement according to claim 22, characterized in that the time stage ( 72 ) a BSY flip-flop with a downstream time counter ( 74 ) contains that the reset input of the BSY flip-flop to the output of a comparator ( 75 ) and that the inputs of the comparator ( 75 ) on the one hand to the time counter ( 74 ) and on the other hand to a selection circuit ( 76 ) whose data inputs are connected to time values and whose selection length is connected via a command decoder ( 71 ) the command register ( 70 ) are connected downstream. Arrangement according to Claim 22 or 25, characterized in that at least one of the output registers is designed as a time keeping register and is assigned to the time stage ( 72 ) is returned. Arrangement according to claim 22, characterized in that at least some of the input lines of the EA ports are connected to detection circuits for signal assignments whose outputs are connected to the time stage ( 72 ) are connected. Arrangement according to Claim 27, characterized in that the signal occupancy detection circuits comprise a comparator ( 77 ), which on the one hand is connected to the input lines and on the other hand is arranged downstream of an output register and whose output is connected to the reset input of the BSY flip-flop of the time stage ( 72 ) connected. Arrangement according to one or more of the previous ones Claims, characterized in that the Data register of the standard register set E-A ports are connected downstream. Arrangement according to one or more of the previous ones Claims, characterized in that the any standard command protocol own E-A register file assigned. Arrangement according to one or more of the preceding claims, characterized in that a program buffer ( 86 ), an output buffer ( 87 ) and an input buffer ( 88 ) are connected to the program buffer ( 86 ) a controller ( 89 ) and that the output buffer ( 87 ) and the input buffer are connected to the I / O ports. Arrangement according to one or more of the preceding claims, characterized in that the EA ports ( 8th ) of the interface adapter ( 7 ) a selection circuit ( 101 ), which on the other hand is connected to the standard interface. Arrangement according to one or more of the preceding claims, characterized in that the EA ports ( 8th ) of the interface adapter ( 7 ) Selection circuits ( 101 ), which on the other hand are connected to further interfaces of the computer system into which the interface adapter ( 7 ) is installed.