DE102006010511A1 - Vertical semiconductor arrangement e.g. semiconductor chip stack, for printed circuit board substrate, has auxiliary layer that is bounded on area of relevant main side or includes structure provided with recess, channel, wall and trench - Google Patents
Vertical semiconductor arrangement e.g. semiconductor chip stack, for printed circuit board substrate, has auxiliary layer that is bounded on area of relevant main side or includes structure provided with recess, channel, wall and trench Download PDFInfo
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- DE102006010511A1 DE102006010511A1 DE102006010511A DE102006010511A DE102006010511A1 DE 102006010511 A1 DE102006010511 A1 DE 102006010511A1 DE 102006010511 A DE102006010511 A DE 102006010511A DE 102006010511 A DE102006010511 A DE 102006010511A DE 102006010511 A1 DE102006010511 A1 DE 102006010511A1
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- additional layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 239000000758 substrate Substances 0.000 title description 3
- 239000000463 material Substances 0.000 claims abstract description 46
- 238000000034 method Methods 0.000 claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 claims abstract description 9
- 239000004020 conductor Substances 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 229920000620 organic polymer Polymers 0.000 claims description 3
- 230000001419 dependent effect Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 40
- 239000000945 filler Substances 0.000 description 17
- 150000001875 compounds Chemical class 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 239000011324 bead Substances 0.000 description 2
- 238000004382 potting Methods 0.000 description 2
- 238000009736 wetting Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002118 epoxides Chemical class 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83009—Pre-treatment of the layer connector or the bonding area
- H01L2224/83051—Forming additional members, e.g. dam structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8336—Bonding interfaces of the semiconductor or solid state body
- H01L2224/83365—Shape, e.g. interlocking features
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Die vorliegende Erfindung betrifft eine vertikale Halbleiteranordnung, insbesondere einen in Face-to-Face-Technologie hergestellten Halbleiterchipstapel oder eine Anordnung eines Chips auf einem PCB-Substrat mittels so genannter Microbumps, bei der der Zwischenraum zwischen den Komponenten mit einem als Underfill bezeichneten Füllmaterial aufgefüllt wird.The The present invention relates to a vertical semiconductor device, in particular, a semiconductor chip stack produced in face-to-face technology or an arrangement of a chip on a PCB substrate by means of such called microbumps, where the space between the components is filled with a filler called Underfill.
Bei Chipstapeln und Multichipmodulen, die durch vertikale, kubische oder dreidimensionale Integrationstechnologien, insbesondere so genannte Face-to-Face-Montage, hergestellt werden, entstehen Zwischenräume zwischen den Komponenten, die mit einem Füllmaterial aufgefüllt werden. Dieses Füllmaterial wird üblicherweise flüssig angrenzend an die Zwischenräume eingebracht, wo es verfließt und sich verteilt, sodass der Zwischenraum gefüllt wird. Nach dem Aushärten des Füllmaterials ist eine dauerhafte Füllung des Zwischenraums entstanden, die üblicherweise als Underfill bezeichnet wird. Diese Füllung dient insbesondere als Korrosionsschutz, vor allem für die in dem Zwischenraum angeordneten Leiterbahnen und Anschlusskontakte. Das Verfließen des Füllmaterials wird hierbei maßgeblich durch Kapillarkräfte und die Adhäsion an den Oberflächen der verbundenen Komponenten beeinflusst.at Stacking of chips and multichip modules by vertical, cubic or three-dimensional integration technologies, especially so called face-to-face assembly, are produced, creating spaces between the components that are filled with a filler filled become. This filling material becomes common liquid adjacent to the spaces between introduced where it flows and spread so that the space is filled. After curing the filler is a permanent filling of the interspace, usually as an underfill referred to as. This filling in particular serves as corrosion protection, especially for in the interconnect arranged conductor tracks and connection contacts. The flow of the filler is decisive here by capillary forces and the adhesion on the surfaces the connected components.
Durch die Adhäsion tritt allerdings ein ungerichtetes und nicht kontrollierbares Verfließen auf, sodass nicht verhindert werden kann, dass unerwünschte Hohlräume in dem Zwischenraum zwischen den Komponenten entstehen und gegebenenfalls Bereiche des Zwischenraum, die von dem Underfill ausgespart werden sollen, zwangsläufig aufgefüllt werden. Es ist prozesstechnisch nicht möglich, das Füllmaterial vor der Verbindung der Materialien aufzubringen; denn die nachfolgenden Prozessschritte, zum Beispiel ein Lötprozess, lassen Bedingungen entstehen, zum Beispiel hohe Temperaturen, die bewirken, dass das Füllmaterial zersetzt würde oder es seine Eigenschaften verlieren würde.By the adhesion However, an undirected and uncontrollable flow occurs, so that it can not be prevented that unwanted cavities in the Gap between the components arise and, where appropriate Areas of the gap left out by the underfill should, inevitably filled become. It is not technically possible, the filler prior to joining the materials; because the following ones Process steps, for example a soldering process, leave conditions arise, for example, high temperatures that cause the filling material would decompose or it would lose its properties.
Ein unerwünschtes Verfließen des Füllmateriales kann auch außerhalb des Zwischenraums auftreten, wenn eine der miteinander verbundenen Komponenten eine größere Oberseite besitzt, auf der eventuell noch weitere Anschlusskontakte, wie zum Beispiel Bondpads, vorhanden sind. Durch das Verfließen des Füllmaterials kann es dann vorkommen, dass auch solche externen Anschlusskontakte bedeckt werden. Möglicherweise soll die noch frei gebliebene Hauptseite der größeren Komponente mit einer Schutzschicht abgedeckt werden, für die auch das als Underfill vorgesehene Füllmaterial geeignet ist. Da das Verfließen des Füllmaterials aber nicht genau kontrolliert werden kann, ist nicht sicherzustellen, dass die Anschlusskontakte in diesem Bereich frei bleiben.One undesirable go by of the filling material can also be outside of the gap occur when one of the interconnected components a bigger top possesses, on the possibly still further connection contacts, as for example Bondpads, are available. Due to the flow of the filling material, it may happen that also such external connection contacts are covered. possibly should the still remaining main page of the larger component with a Protective layer are covered, for which also as underfill provided filling material suitable is. Because the flow of the filling material but can not be controlled precisely is not sure that the connection contacts remain free in this area.
In
der
Ein
kanalisiertes Verfließen
von Füllmaterial ist
auch von Herstellungsverfahren bekannt, mit denen eine Anordnung
eines auf einem Leadframe montierten Halbleiterchips in eine Vergussmasse
eingeschlossen oder verkapselt wird. Ein derartiges Verfahren ist
zum Beispiel in der
In
der
Aufgabe der vorliegenden Erfindung ist es, eine vertikale Halbleiteranordnung mit Underfill anzugeben, bei der der Underfill den Zwischenraum zwischen den Komponenten in vorgesehener Weise ausfüllt und Hohlräume allenfalls in dafür vorgesehenen Bereichen vorhanden sind sowie gegebenenfalls vorhandene externe Anschlusskontaktflächen von dem Material des Underfills frei gehalten sind. Außerdem soll ein Herstellungsverfahren für vertikale Halbleiteranordnungen angegeben werden, mit dem ein unerwünschtes Verfließen des Füllmaterials bei der Herstellung des Underfills vermieden wird.task It is the object of the present invention to provide a vertical semiconductor device specify with underfill where the underfill is the gap fills between the components in the intended manner and cavities at most in it provided areas and any existing ones external connection pads are kept free of the material of the underfill. In addition, should a manufacturing process for Vertical semiconductor devices are given, with an undesirable go by of the filling material avoided in the production of the underfill.
Diese Aufgabe wird mit der vertikalen Halbleiteranordnung mit den Merkmalen des Anspruches 1 bzw. mit dem Verfahren mit den Merkmalen des Anspruches 11 gelöst. Ausgestaltungen ergeben sich aus den abhängigen Ansprüchen.These Task is with the vertical semiconductor device with the features of claim 1 or with the method having the features of the claim 11 solved. Embodiments emerge from the dependent claims.
Die Halbleiteranordnung umfasst mindestens zwei Komponenten, die Halbleiterchips oder Substrate einschließlich PCBs (printed circuit board) sein können und die mit einer jeweiligen Hauptseite einander gegenüber angeordnet und dauerhaft miteinander verbunden sind. Auf den einander gegenüberliegenden Hauptseiten gegebenenfalls vorhandene elektrische Leiter oder für elektrische Verbindungen vorgesehene Kontaktflächen sind in der vorgesehenen Weise durch Kontakte miteinander verbunden. Der zwischen den Komponenten vorhandene Zwischenraum ist mit einem Underfill gefüllt. Zumindest auf einer der Hauptseiten ist eine strukturierte Zusatzschicht vorgesehen, die mit dem Underfill in Berührung ist. Die Zusatzschicht ist auf einen Bereich der betreffenden Hauptseite eingegrenzt oder weist mindestens einen Kanal, Wall und/oder Graben auf. Diese Zusatzschicht ist so strukturiert, dass bei der Herstellung des Underfills das Füllmaterial in einer vorgesehenen Weise verfließt, sodass eine vollständige Füllung des Zwischenraumes erreicht wird und gegebenenfalls nur an den vorgesehenen Stellen Hohlräume bleiben. Die Zusatzschicht kann insbesondere ein organisches Polymer, zum Beispiel Polyimid oder ein Epoxid, sein. Es ist jedoch auch möglich, die Zusatzschicht aus Metall oder aus verschiedenen Materialien auszubilden.The semiconductor device comprises at least two components, which may be semiconductor chips or substrates including PCBs (printed circuit board) and which are arranged with a respective main side facing each other and permanently connected to each other. On the opposing main sides optionally present electrical conductors or provided for electrical connections contact surfaces are connected in the intended manner by contacts. The gap between the components is filled with an underfill. At least on one of the main pages a structured additional layer is provided, which with the underfill in Touch is. The additional layer is limited to an area of the relevant main page or has at least one channel, wall and / or trench. This additional layer is structured such that in the production of the underfill, the filling material flows in a planned manner, so that a complete filling of the gap is achieved and possibly remain only at the intended locations cavities. The additional layer may in particular be an organic polymer, for example polyimide or an epoxide. However, it is also possible to form the additional layer of metal or of different materials.
Die Zusatzschicht kann Ausnehmungen oder Stege aufweisen, die Kanäle bilden, in denen die Füllmasse in vorgesehene Bereiche kanalisiert wird. Die Zusatzschicht kann zusätzlich oder statt dessen mit Wällen, insbesondere in der Form von Stegen oder Dämmen, und/oder Gräben versehen sein, die ein Verfließen der Füllmasse begrenzen. Die Strukturen der Zusatzschicht können im Zwischenraum zwischen den Komponenten vorgesehen werden oder auch außerhalb, insbesondere um externe Kontaktflächen, wie z. B. Bondpads, vor einem Benetzen mit dem Füllmaterial zu schützen.The Additional layer can have recesses or webs forming channels, in which the filling material is channeled into designated areas. The additional layer can additionally or instead with ramparts, provided in particular in the form of webs or dams, and / or trenches to be a flowing one the filling material limit. The structures of the additional layer can be in the space between be provided to the components or outside, in particular to external Contact surfaces, such as As bond pads to protect against wetting with the filler.
Das Verfahren umfasst die Schritte, die strukturierte Zusatzschicht auf einer der einander gegenüberliegend anzuordnenden Hauptseiten der Komponenten anzubringen, dann die Komponenten in der vorgesehenen Weise wie üblich miteinander zu verbinden und anschließend das als Underfill vorgesehene Füllmaterial seitlich an den Zwischenraum zwischen den Komponenten einzubringen. Die Zusatzschicht wird so strukturiert, dass sie ein Verfließen des Füllmaterials derart beeinflusst, dass das Füllmaterial an die vorgesehenen Stellen gelangt. Das kann insbesondere dadurch bewirkt werden, dass in der Zusatzschicht Kanäle ausgebildet werden und das Füllmaterial wegen der Adhäsion und/oder der auftretenden Kapillarkräfte durch die Kanäle in einen weiten Bereich des Zwischenraumes gezogen wird. Andererseits können Aussparungen oder Gräben ebenso wie Wälle oder Wülste vorhanden sein, die ein weiteres Verfließen des Füllmaterials in der betreffenden Richtung eindämmen. Auf diese Weise kann das Füllmaterial auf den Zwischenraum begrenzt werden, oder es können gezielt Hohlräume hergestellt werden, zum Beispiel um bestimmte Kontakte herum, die nicht mit dem Füllmaterial in Berührung kommen sollen.The Method includes the steps, the structured additional layer on one of the opposite to install the main components of the components to be arranged, then the Connect components in the intended manner as usual and subsequently the intended as underfill filler laterally to introduce the gap between the components. The additional layer is structured so that it flows through the filler influenced so that the filler material get to the designated places. This can be done in particular causes be formed in the additional layer channels and the filling material because of the adhesion and / or the occurring capillary forces through the channels into one wide area of the gap is drawn. On the other hand, recesses can or trenches as well as ramparts or beads be present, which is a further flow of the filling material in the relevant Damp direction. In this way, the filler material be limited to the space, or it can specifically produced cavities be, for example, around certain contacts that are not with the filling material in touch should come.
Die Zusatzschicht kann zum Beispiel ganzflächig aufgebracht und mittels einer an sich bekannten Fotolithographie strukturiert werden. Es kann mitunter genügen, die Strukturierung der Zusatzschicht darauf zu beschränken, sie nur in dem Zwischenraum oder bestimmten Bereichen des Zwischenraums auszubilden, wenn das Material der Zusatzschicht zum Beispiel so gewählt wird, dass es von dem Füllmaterial sehr gut benetzt wird, und allein hierdurch bereits erreicht wird, dass der Zwischenraum vollständig gefüllt wird und der Underfill auf den Zwischenraum begrenzt wird.The Additional layer can, for example, applied over the entire surface and by means of a known photolithography be structured. It can sometimes suffice to limit the structuring of the additional layer to it only in the gap or certain areas of the gap form if the material of the additional layer, for example so chosen that's it from the filler material is wetted very well, and this alone is already achieved, that the gap is complete filled and the underfill is limited to the gap.
Es folgt eine genauere Beschreibung von Beispielen der Halbleiteranordnung und des Verfahrens anhand der beigefügten Figuren.It follows a more detailed description of examples of the semiconductor device and the method with reference to the accompanying figures.
Die
Die
Die
Die
Die
Die
Die
Die
Die
Die
In dem nachfolgend beschriebenen Ausführungsbeispiel ist die vertikale Halbleiteranordnung ein Chipstapel, der in Face-to-Face-Technologie montiert ist. Die erste Komponente ist in diesem Beispiel ein unterer Halbleiterchip (bottom chip), der sich noch im Waferverbund befindet, wenn ein jeweiliger oberer Halbleiterchip (top chip) als zweite Komponente montiert wird.In the embodiment described below is the vertical Semiconductor assembly a chip stack mounted in face-to-face technology is. The first component is a lower semiconductor chip in this example (bottom chip), which is still in Waferverbund, if a respective upper semiconductor chip (top chip) as a second component is mounted.
In
der
Die
Die
In
der
Die
Die
Draufsicht der
In
der
Die
Die
Das
ist in der
Die
Die
Anhand
der dargestellten Ausführungsbeispiele
wird klar, wie die strukturierte Zusatzschicht
- 11
- erste Komponentefirst component
- 22
- zweite Komponentesecond component
- 33
- Underfillunderfill
- 44
- Verbindungskontaktconnection contact
- 55
- elektrischer Leiterelectrical ladder
- 66
- Zusatzschichtadditional layer
- 77
- Passivierungsschichtpassivation layer
- 88th
- Anschlusskontaktconnection contact
- 99
- Hohlraumcavity
- 1010
- Wallrampart
- 1111
- Grabendig
- 1212
- Stützesupport
Claims (20)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102006010511A DE102006010511A1 (en) | 2006-03-07 | 2006-03-07 | Vertical semiconductor arrangement e.g. semiconductor chip stack, for printed circuit board substrate, has auxiliary layer that is bounded on area of relevant main side or includes structure provided with recess, channel, wall and trench |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102006010511A DE102006010511A1 (en) | 2006-03-07 | 2006-03-07 | Vertical semiconductor arrangement e.g. semiconductor chip stack, for printed circuit board substrate, has auxiliary layer that is bounded on area of relevant main side or includes structure provided with recess, channel, wall and trench |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE102006010511A1 true DE102006010511A1 (en) | 2007-09-13 |
Family
ID=38335889
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE102006010511A Ceased DE102006010511A1 (en) | 2006-03-07 | 2006-03-07 | Vertical semiconductor arrangement e.g. semiconductor chip stack, for printed circuit board substrate, has auxiliary layer that is bounded on area of relevant main side or includes structure provided with recess, channel, wall and trench |
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| Country | Link |
|---|---|
| DE (1) | DE102006010511A1 (en) |
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| WO2011063168A1 (en) * | 2009-11-19 | 2011-05-26 | Qualcomm Incorporated | Underfilled semiconductor package using dam and trench structures and manufacturig methods thereof |
| DE102015104507A1 (en) * | 2014-12-19 | 2016-06-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated fan-out structure with openings in a buffer layer |
| US9425121B2 (en) | 2013-09-11 | 2016-08-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated fan-out structure with guiding trenches in buffer layer |
| US9455211B2 (en) | 2013-09-11 | 2016-09-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated fan-out structure with openings in buffer layer |
| DE102015218355A1 (en) | 2015-09-24 | 2017-03-30 | Robert Bosch Gmbh | Microelectronic component arrangement and production method for a microelectronic component arrangement |
| CN114068472A (en) * | 2020-08-06 | 2022-02-18 | 力成科技股份有限公司 | Package structure and method for manufacturing the same |
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| DE102015218355A1 (en) | 2015-09-24 | 2017-03-30 | Robert Bosch Gmbh | Microelectronic component arrangement and production method for a microelectronic component arrangement |
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| CN114068472B (en) * | 2020-08-06 | 2025-08-08 | 力成科技股份有限公司 | Packaging structure and manufacturing method thereof |
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