DE102009012516B4 - Multi-layer substrate for highly integrated module - Google Patents

Abstract

Multi-layer substrate (MLS) comprising
An IC chip (IC), a reference bulk layer (BML) and a balun (BU),
One or more lower layers (UL) of a dielectric material having a dielectric constant ε _u ,
One or more upper layers (OL) of a dielectric material having a dielectric constant ε _o ,
One or more middle layers (ML) of a dielectric material with dielectric constant ε _m arranged between the lower and the upper layers,
Structured metallization areas (SMF) arranged between or on the layers (UL, ML, OL),
Structured metallization lines (SML) arranged between or on the layers (UL, ML, OL),
A capacitive element (KE) formed from at least two structured metallization areas (SMF) and from at least one middle layer (ML) arranged therebetween,
An inductive element (IE) formed of patterned metallization lines (SML) arranged in direct contact with the top layer (OL) or bottom layer (UL), wherein
- ε _m > = ...

Description

The The invention relates to a multi-layer substrate for receiving circuit components a highly integrated module.

modern communications equipment include a variety of electrical and electronic components in transmitting and receiving circuits. These include on the one hand active components like low-noise amplifiers, Mixers, oscillators, switching elements and power amplifiers. These and possibly other active components are generally in one or multiple chips incorporating integrated circuits. In a so-called transceiver IC z. For example, the active components be summarized by transmitting and receiving circuit. The further in modern communication devices contained high-frequency circuit components such as bandpass filters, Baluns, ohmic resistances, Capacitors, coils or varistors are generally referred to as passive circuit components executed. circuit components like antenna switches, bandpass filters (eg with surface waves working filters), baluns and impedance matching circuits often summarized in a so-called front-end module. Become all circuit components of transmitting and receiving paths of a mobile communication device on the surface a printed circuit board, so claim these components on the printed circuit board a lot of space. The ongoing trend towards Miniaturization of mobile communication devices follows the demand for a reduced space requirement of the entirety of the components. The Miniaturization is still the most important requirement before everything from the mobile industry, to downsize terminals even further ago but all with additional To equip functions. This trend is due to an ever-increasing degree of integration Taken into account. For example, in modules based on LTCC active circuits comprising chips and passive high frequency circuit components vertically in metallization levels caused by dielectric layers are separated from each other, integrated.

From the publication US 7,167,688 B2 For example, high frequency transceiver modules are known in which active and passive high frequency circuit components are vertically integrated in a multi-layer substrate. Chips incorporating active circuit components as well as chips incorporating surface acoustic wave circuit components are disposed on a surface of a multi-layer substrate and interconnected with passive components disposed in metallization planes between the dielectric layers.

From the patent DE 10 2006 059 137 B3 Multi-layer array antennas are known for magnetic resonance applications with different dielectric constants.

From the publication US 2002/0009577 A1 Multi-layer substrates for electrical components with layers of different dielectric constants are known.

The publication DE 100 53 205 A1 describes frontend circuits for wireless transmission systems.

From the publication DE 102 28 328 A1 For example, an electronic component with a multilayer substrate and passive circuit components are known as structured metallizations.

One The problem of the prior art is that for circuit components for disposal standing volumes in mobile communication devices due to the ongoing trend for miniaturization decreases while the complexity of transmitting and receiving circuits due to additional functions to be realized continues to increase. So there is a need for electrical components, which despite a high number of circuit components a low Volume or a small footprint - d. H. a small width and a low overall height exhibit. There is still a need for electrical components and substrates which are for a Variety of different integrated circuit components provide a suitable, versatile spatial environment.

task The present invention is therefore, electrical components with reduced space requirement for the same or increased functionality with a versatile usable spatial Specify the environment.

These The object is achieved by a Multi-layer substrate solved according to claim 1. Advantageous embodiments emerge from the dependent claims.

A multilayer substrate is specified, which comprises a lower layer of a dielectric material having a dielectric constant ε _u , an upper layer of a dielectric material having a dielectric constant ε _o, and a middle layer of a dielectric material having a dielectric constant ε _m arranged between the upper and lower layers. Between or on the layers, structured metallization surfaces and structured metallization lines are arranged. A capacitive element is formed from at least two structured metallization areas and from at least one middle layer arranged therebetween. An inductive element is formed from structured metallization lines. This is arranged in direct contact with the upper layer or the lower layer. The dielectric constant ε _{m of} the middle layer is greater than or equal to 1.5 times the dielectric constant of the lower layer and greater than or equal to 1.5 times the dielectric constant of the upper layer. A multilayer substrate with mixed ceramic whose middle layers have a higher dielectric constant than upper and lower layers has the following advantages: Increasing the dielectric constant increases the capacitance of a capacitive element if the area occupancy in the multilayer substrate and the layer thickness of the dielectric layer remain constant. This is equivalent to the effect that can be achieved in such a way that the lateral area requirement is reduced while the capacity remains the same. This is particularly significant if the reproducibility of the layer thickness would be degraded by a decrease in the layer thickness, which is avoided with the multilayer substrate according to the invention, since this z. B. allows higher capacities without reducing the thickness of a layer. The lateral space requirement is thus reduced and the layer thickness does not have to be reduced. The provision of coil forming striplines / patterned metallization lines in metallization planes between low dielectric constant dielectric layers results in reduced coupling between the metallization lines of different metallization levels (parasitic capacitances), thereby increasing the Q of the corresponding inductive element and reducing losses. In general, the invention provides different circuit components with different requirements for a multi-layer substrate such a substrate available, which better - because individual - can be adapted to these requirements. Each integrated circuit element has a - with respect to the dielectric constant or the layer thickness - individually adapted spatial environment.

The between different metallization levels arranged circuit components are about Vias through the dielectric layers together connected.

Farther is an integrated circuits comprehensive chip - below Called IC chip - in or mounted on the substrate. It can be integrated with in the substrate Circuit elements be interconnected. Such a chip can be circuit components of a Transceiver circuit include. In particular, it is preferred if it comprises all the circuit components of a transceiver circuit.

The Multilayer substrate has on the one hand an IC chip on the surface the uppermost layer is disposed, and on the other hand is a balun integrated, which is an interconnection of capacitive elements, structured metallization, structured metallization lines and a reference ground layer includes, wherein the reference ground layer on the uppermost upper layer is arranged and as a mounting surface of the IC chip is used. Here are the other circuit components of the balun vertically below the reference ground layer. The Reference ground layer is preferably connected to ground.

In an advantageous embodiment, the dielectric constants of the lower and upper layers ε _u and ε _{o are} greater than _or equal to 6 and less than 10, while the dielectric constant ε _{m of} the middle layer is greater than or equal to 15 and less than or equal to 25.

The Multilayer substrate preferably comprises at least one layer LTCC (Low Temperature Cofired Ceramics, HTCC (High Temperature Cofired Ceramics) or laminate.

Farther it is preferable if the multi-layer substrate at least three dielectric Has layers that respect their dielectric constant symmetrical are arranged around the middle layer as a mirror plane.

In In a further particularly preferred embodiment, the multi-layer substrate comprises vias by at least one of the layers and metallization lines that Form parts of the signal paths. The metallization lines serve the interconnection of circuit components of the transceiver circuit with further - z. B. passive - circuit components, which are realized in the multi-layer substrate. Such circuit components can Impedance matching circuits, Baluns (so-called "balanced-unbalanced" converter; Symmetrizing matching circuits) Transmit or receive filter or other parts of a front-end circuit be.

Especially Embodiments in which a transmission filter circuit with a a Interconnection from z. B. passive reactance elements comprising transmission filter, which is connected to a transmission signal path of the transceiver circuit and a receiving filter circuit having acoustic waves operating receive filter with a received signal path of the transceiver circuit is interconnected, represent preferred embodiments.

A balun can be connected both in the transmission signal path and in the reception signal path. A balun is a circuit element that converts balanced signals into unbalanced signals, or conversely converts unbalanced signals into balanced signals. A corresponding balun preferably comprises an interconnection of capacitive and inductive elements, which are formed as structured metallization areas or structured metallization lines between or on the dielectric layers.

The High-frequency signals with which an antenna supplies a front-end circuit, are usually "unbalanced". Of the Advantage of "balanced" guided signal lines is that common-mode noise effectively suppressed be because a jamming signal, which two "balanced" guided signal lines imprinted is effectively eliminated by subtraction again. Namely then, if a fault both "balanced" guided signal lines as it were impressed is. This is the "signal-to-noise" ratio and the sensitivity increases and immunity to interference improved.

Especially the components of impedance matching elements may be in a multi-layer substrate to get integrated. So it is advantageous if the capacitive and inductive elements of the interconnection of an impedance element as structured metallization surfaces or structured metallization lines between or on the Layers are formed.

One in the transmission signal path interconnected transmission amplifier is preferably on the substrate surface arranged. Also a receive amplifier, in the receive signal path is connected, is preferably arranged on the substrate surface. The chip in which the transmission amplifier or the receiving amplifier is more integrated or more general, each chip, the integrated active Circuit components or passive circuit components such as SAW filters or BAW filter is arranged on the upper layer and connected. In particular, high frequency active circuit components Comprehensive chips are preferably above one on the top Position arranged structured metallization arranged and Z. B. with structured Metallisierungsleitungen or vias - interconnected. The interconnection can be embodied in wire-bond technology or in flip-chip technology. Possible are also embodiments in which some chips in wire-bond technology interconnected and other chips interconnected in flip-chip technology are. Also mounted in SMD (SMD = surface mounted device) technology Chips can be used.

Large area on one of the substrate surfaces arranged metallization can to HF shielding serve. For this purpose, they are preferably connected to ground. Such large-scale metallization levels serve in particular for the protection of circuit components from the disturbing electromagnetic emissions of active circuit components in a chip, d. H. against unwanted Radio frequency signals. These are z. B. on top of the arranged uppermost of the upper layers corresponding below the chip. The large-scale metallization levels can located non-conductive areas on the surface of the multi-layer substrate enclose, which comprise, for example, plated-through holes and via which the chips be interconnected with internal signal line elements can.

Thereby is a high isolation between the active high frequency components, z. In a transceiver chip and the integrated passive elements ensured in multi-layer substrate.

When Balun comes in particular a so-called Marchand balun in question, the one with each other coupled structured metallization lines and capacitive elements includes. Through the interconnection of capacitive elements in one Balun can Strip conductor of the balun - so-called. strip lines - shortened.

Corresponding the embodiments of the Invention executed Multilayer substrates are used in particular in mobile communication devices. The multi-layer substrates then comprise an antenna switch which with a transmission signal path and a reception signal path of the mobile communication device is interconnected.

Especially it is advantageous if a multilayer substrate comprises a duplexer, which is connected to the transmission and the received signal path.

in the Next, the multi-layer substrate will be described based on embodiments and associated schematic Figures closer explained. It shows:

1 a cross section through a multi-layer substrate,

2 a schematic diagram of a front-end circuit,

3 a cross section through another multi-layer substrate

1 shows a cross section through a multi-layer substrate according to the invention. Three superposed middle layers ML are arranged between upper layers OL and lower layers UL. On the upper side OO of the layer structure MLS comprising all layers or on the uppermost upper layer OL, a chip DU is arranged which comprises a duplexer circuit. Also disposed on the top surface is another chip IC comprising active circuit components. The chip comprising the duplexer circuit is in Flip-chip technology with structured metallizations (structured metallization lines SML and structured metallization surfaces SMF) on the upper surface OO interconnected, while the active circuit components comprehensive chip IC in wire-bonding technology with structured metallization elements on the upper surface is connected. Structured metallization lines SML and structured metallization surfaces SMS are arranged in metallization planes between and on the dielectric layers of the multilayer substrate. They represent passive, inductive IE or capacitive KE circuit elements. Such integrated circuit elements are interconnected via feedthroughs DK (KE, IE).

The multi-layer substrate in 1 has a mirror symmetry defined by a mirror plane SE. The mirror symmetry refers here only to the layer structure of the dielectric layers and not to the arrangement of chips on the surface or of integrated circuit elements in Metallisierungsflächen. Through-contacts DK through the lowermost of the lower layers represent contacting elements Kon on the lower substrate surface SO, via which the circuit elements of the multi-layer substrate can be connected to an external circuit environment.

2 illustrates the schematic interconnection of a front-end circuit FES. An antenna A, which usually provides an "unbalanced" guided signal is connected to an antenna switch AS. The antenna switch connects signal paths SP with the antenna A. Reception filter circuits EFS are connected in receive signal paths ESP. The reception filter circuits EFS comprise balun functionality, so that the signal lines which interconnect the reception filter circuit EFS with the transceiver circuit TCS are designed to be balanced. Between receiving filter circuit and transceiver circuit impedance matching elements IAE are each connected. The transceiver circuit TCS may include receive amplifiers EV, transmit amplifiers SV and other integrated circuits IC. However, transmit amplifier SV and receive amplifier EV need not be implemented in the same chip. They can also be implemented in different chips and even on different substrates. Furthermore, the front-end circuit comprises transmission filter circuits SFS, which are connected in transmission signal paths SSP. The transmit filter circuits are respectively connected between the antenna switch AS and the transceiver TCS. Furthermore, a transmit amplifier SV is connected between the respective transmit filter circuit and the transceiver circuit per transmit signal path SSP. Baluns BU are connected between the corresponding transmission amplifier SV and the transceiver circuit TCS.

In 2 For example, two receive signal paths in which receive filter circuits EFS are connected and two transmit signal paths in which transmit filter circuits SFS are connected are shown. This illustration is schematic. Further interconnected receive signal paths or transmit signal paths - z. B. to cover different other frequency bands - are conceivable. It is possible for a multi-layer substrate according to the invention to comprise both the circuit elements of the received signal paths and the transmission signal paths. Furthermore, it is possible for all the received signal paths in a first multi-layer substrate and all the transmit signal paths to be integrated in a further multi-layer substrate. The separation of transmit signal paths and receive signal paths onto different multi-layer substrates improves isolation between signal paths that transmit high RF power (the transmit signal paths) and signal paths that transmit low RF power (the receive signal paths). Various multi-layer substrates may be stacked and electrically and mechanically interconnected. But they can also be arranged side by side on a common PCB.

3 shows a cross section through a multi-layer substrate MLS, which is no longer symmetrical with respect to the arrangement of the dielectric layers. Above three middle layers ML arranged one above the other, an upper layer OL is arranged, the three middle layers ML being arranged above three lower layers UL arranged one above the other. Between a chip IC comprising active circuit components and the upper layer OL, a structured metallization surface is arranged as a reference mass layer BML, which is made over a large area. Vertically below the reference ground layer BML, an upper structured metallization line SML is arranged. This is separated from the reference bulk layer BML by the upper layer OL. An uppermost middle layer ML is arranged between the upper structured metallization line SML and a lower structured metallization line SML. A further middle layer ML, which is arranged below the uppermost middle layer, separates the lower structured metallization line SML from a structured metallization surface SMF. The reference ground area BMF, the structured metallization area SMF and the two structured metallization lines SML are components of a balun arranged below the chip IC, which uses two of the middle layers ML as functional layers. The reference ground layer BML on the one hand represents a ground plane of the balun and on the other hand represents an effective RF shielding of remaining circuit components in front of the emitted high-frequency power of the chip IC.

A multi-layer substrate according to the invention is not limited to one of the described embodiments. Combinations of these and variations, which z. B. further inductive or capacitive elements that may be embodied as metallizations between the dielectric layers comprise, represent embodiments of the invention as well.

LIST OF REFERENCE NUMBERS

• AS:

  antenna switch

  BML:

  Ground for the position

  BU:

  balun

  DK:

  via

  YOU:

  Duplexerchip

  EFS:

  Receive filter circuit

  ESP:

  Receive signal path

  EV:

  receiver amplifier

  FES:

  Front-end circuit

  IAE:

  impedance matching

  IC:

  IC chip

  IE:

  Inductive element

  KE:

  Capacitive element

  Kon:

  contacting

  L:

  location

  ML:

  Middle location

  MLS:

  Multilayer substrate

  OIL:

  Upper location

  OO:

  upper top

  SE:

  mirror plane

  SFS:

  Transmission filter circuit

  SMF:

  Structured metallization surface

  SML:

  Structured metallization line

  SO:

  substrate surface

  SP:

  signal path

  SSP:

  Transmission signal path

  SV:

  transmission amplifier

  TCS:

  Transceiver circuit

  UL:

  Lower position

Claims (14)

Multi-layer substrate (MLS), comprising - an IC chip (IC), a reference ground layer (BML) and a balun (BU), - one or more lower layers (UL) of a dielectric material with dielectric constant ε _u , - one or more upper layers (OL) of a dielectric material with dielectric constant ε _o , - one or more middle layers (ML) of a dielectric material with dielectric constant ε _m , arranged between the lower and the upper layers, - structured metallization surfaces (SMF), which lie between or on the layers ( UL, ML, OL) are arranged, - structured metallization lines (SML), which are arranged between or on the layers (UL, ML, OL), - one of at least two structured metallization surfaces (SMF) and at least one intermediate layer arranged therebetween (ML) formed capacitive element (KE), - one of structured metallization lines (SML) formed inductive element (IE), which in directly em contact to the upper layer (OL) or lower layer (UL) is arranged, wherein - ε _m > = 1.5 · ε _u and ε _m > = 1.5 · ε _o , - the reference ground layer (BML) on the uppermost layer (OL ), - the IC chip (IC) is arranged on the surface of the uppermost of the upper layers, - the reference ground layer (BML) serves as a mounting surface of the IC chip (IC), - the balun (BU) has an interconnection of capacitive elements (KE), structured metallization areas (SMF), structured metallization lines (SML) and the reference ground layer (BML), - the further circuit components of the balun (BU) are arranged vertically below the reference ground layer (BML). The multilayer substrate according to claim 1, wherein 6 <= ε _u <= 10, 6 <= ε _o <= 10 and 15 <= ε _m <= 25. Multi-layer substrate according to one of claims 1 or 2, wherein at least one of the layers (L) of a dielectric material, selected from lower, middle and upper layer comprises LTCC, HTCC or laminate. Multi-layer substrate according to one of claims 1 to 3, wherein a total of three or more of the layers (L) of a dielectric Materials are provided, with respect to their dielectric constant arranged symmetrically about the middle layer (ML) as a mirror plane (SE) are. Multi-layer substrate according to one of claims 1 to 4, wherein the IC chip (IC) comprises a transceiver circuit (TCS). Multi-layer substrate according to claim 5, with plated-through holes (DK) by at least one of the layers (L) of a dielectric material and with signal paths (SP) made of metallization lines (ML), the connected to the transceiver circuit (TCS). Multi-layer substrate according to one of claims 5 or 6, comprising - one Transmission filter circuit (SFS) with an interconnection of reactance elements comprehensive transmit filter, which interfaces with a transmit signal path (SSP) of the transceiver circuit (TCS) is and - one Reception filter circuit (EFS) with a working with acoustic waves Receive filter, with a received signal path (ESP) of the transceiver circuit (TCS) is interconnected. The multi-layer substrate according to claim 7, wherein the balun (BU) in the transmit signal path (SSP) or receive signal path (ESP) is interconnected. Multilayer substrate according to one of claims 6 to 8, in whose signal paths (SP) an impedance matching element (IAE) interconnected This is an interconnection of capacitive (KE) and inductive (IE) elements comprising, as structured metallization surfaces (SMF) or structured metallization lines (SML) between or are formed on the layers (L) of a dielectric material. Multi-layer substrate according to one of claims 7 to 9, in whose transmission signal path (SSP) a transmission amplifier (SV) is connected, which is arranged on the substrate surface (SO). Multi-layer substrate according to one of claims 7 to 10, in whose received signal path (ESP) a receive amplifier (EV) is connected, which is arranged on the substrate surface (SO). Multi-layer substrate according to one of claims 5 to 11, whose IC chip (IC) is wired in Wirebond technology. Multi-layer substrate for use in a mobile communication device according to one of the claims 7 to 12, which comprises an antenna switch (AS), which with a Send signal (SSP) and a received signal path (ESP) interconnected is. Multi-layer substrate for use in a mobile communication device according to one of the claims 7 to 13, which comprises a duplexer (DU) connected to the transmission signal (SSP) and the received signal path (ESP) is interconnected.

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