DE102014003655B4 - Apparatus comprising an RC-dominated oscillator with trimmable passive components, and method for operating an RC-dominated oscillator to achieve a predetermined target frequency - Google Patents

Abstract

Device comprising:
an RC-dominated oscillator (100) including a resistor (200, 300) and/or a capacitor (500) or a plurality of resistors (200, 300) and/or a plurality of capacitors (500) with programmable resistance and programmable capacitance configured to be adjusted until the RC-dominated oscillator (100) produces a predetermined target frequency;
a lookup table for storing configuration values of trimmable resistors (200, 300) and/or trimmable capacitors (500); and
a circuit with trimmable resistors (200, 300) and/or trimmable capacitors (500) which are arranged to be adjusted based on the configuration values.

Description

background

To manufacture high volumes of complex analog structures such as voltage regulators (VRs), consistent performance is expected to be delivered in the presence of silicon process variations in devices and passive components. Passive components include inductors, resistors, and capacitors. These passive components vary in chip characteristics on the same wafer. For example, a resistance value of a passive resistor may vary four times between different chips. Such variation affects performance of these complex analog circuits.

In US 2006 / 0 181 359 A1 discloses an oscillator circuit that is configured to adjust the frequency of a signal FOUT by changing the number of resistors and capacitors in the circuit. In particular, capacitances of capacitors are adjusted.

In US 2006 / 0 220 724 A1 Adaptation of two resistors is disclosed. As a result of the adaptation, the resistors exhibit the same switching behavior.

In US 2012 / 0 093 268 A1 discloses an RC oscillator whose capacitors and resistors can be adjusted to produce a target frequency. This adjustment serves to center the frequency and is performed in response to erroneous data transmissions that are affected by the oscillator.

In US 2007 / 0 165 446 A1 Programmable resistors are disclosed that are connected between two inverters and can be programmed to low or high states.

In US 2003 / 0 071 653 A1 discloses a switch that connects interconnect segments based on configuration data stored in memory cells.

The present invention is based on the object of adapting circuits with resistors and/or capacitors in order to generate a predetermined target frequency. This object is achieved by the independent claims.

Short description of the drawings

• 1A zeigt einen RC (resistor-capacitor)-dominierten Oszillator gemäß einer Ausführungsform der Offenbarung, der zum Bestimmen von Trimmcode für trimmbare passive Geräte verwendet wird.
• 1B zeigt einen Plot mit Wellenformen, die von dem RC-dominierten Oszillator gemäß einer Ausführungsform der Offenbarung erzeugt werden, der verwendet wird, um Trimmcode für trimmbare passive Geräte zu bestimmen.
• 1C zeigt, wie ein fein justierbarer binärer Kondensator gemäß einer Ausführungsform der Offenbarung verwendet wird, um trotz Prozessveränderungen eine erwünschte Kapazität auszuwählen.
• 2 zeigt einen Widerstand mit trimmbarer Widerstandseinheitszelle gemäß einer Ausführungsform der Offenbarung.
• 3 zeigt einen trimmbaren Widerstand gemäß einer weiteren Ausführungsform der Offenbarung.
• 4 zeigt einen trimmbaren Widerstand mit programmierbarem Widerstand gemäß einer Ausführungsform der Offenbarung.
• 5 zeigt einen trimmbaren Kondensator mit programmierbarer Kapazität gemäß einer Ausführungsform der Offenbarung.
• 6 zeigt ein Flussdiagramm zum Trimmen passiver Geräte gemäß einer Ausführungsform der Offenbarung.
• 7 zeigt einen RC-Konfigurationsfluss unter Verwendung einer Nachschlagetabelle (lookup table (LUT)) und/oder Formel zum Trimmen von Kondensator und Widerstand einer Schaltung (beispielsweise Kompensator für einen Spannungsregler) unter Verwendung von Code von dem RC-dominierten Oszillator aus 1A gemäß einer Ausführungsform.
• 8 zeigt einen Kompensator mit trimmbaren passiven Geräten gemäß einer Ausführungsform, die unter Verwendung des RC-Konfigurationsflusses aus 7 getrimmt werden.
• 9 zeigt ein intelligentes Gerät oder ein Computersystem oder ein SoC (system-on-chip) mit trimmbaren passiven Geräten und Vorrichtung/Verfahren zum Trimmen der passiven Elemente gemäß einer Ausführungsform der Offenbarung.

The embodiments of the disclosure will be more fully understood from the detailed description below and the accompanying drawings of various embodiments of the disclosure.

• 1A shows a RC (resistor-capacitor) dominated oscillator according to an embodiment of the disclosure used to determine trim code for trimmable passive devices.
• 1B shows a plot of waveforms generated by the RC dominated oscillator used to determine trim code for trimmable passive devices according to an embodiment of the disclosure.
• 1C shows how a finely adjustable binary capacitor is used to select a desired capacitance despite process variations, according to an embodiment of the disclosure.
• 2 shows a resistor with trimmable resistance unit cell according to an embodiment of the disclosure.
• 3 shows a trimmable resistor according to another embodiment of the disclosure.
• 4 shows a trimmable resistor with programmable resistance according to an embodiment of the disclosure.
• 5 shows a trimmable capacitor with programmable capacitance according to an embodiment of the disclosure.
• 6 shows a flowchart for trimming passive devices according to an embodiment of the disclosure.
• 7 shows an RC configuration flow using a lookup table (LUT) and/or formula for trimming capacitor and resistor of a circuit (e.g. compensator for a voltage regulator) using code from the RC dominated oscillator 1A according to one embodiment.
• 8 shows a compensator with trimmable passive devices according to an embodiment using the RC configuration flow of 7 be trimmed.
• 9 shows an intelligent device or a computer system or a SoC (system-on-chip) with trimmable passive devices and apparatus/method for trimming the passive elements according to an embodiment of the disclosure.

Detailed description

To maintain circuits dynamically programmable at known power levels in the presence of silicon process variation, a method and apparatus for normalizing passive component power is described. Embodiments describe a method and apparatus for implementing passive elements with normalized chip power using a novel RC passive trimming scheme, where "R" is resistance and "C" is capacitance.

To provide constant performance in the presence of silicon process variation, where both R and C can vary by up to +/-40%, the passive elements used in analog circuits (e.g., voltage regulators) are built using trimmable passive devices according to one embodiment. In one embodiment, the values for R and C can be trimmed to a normalized RC product. In cases where circuits must additionally retain the ability to be programmed with variable, but normalized, time constants, for these circuits, in one embodiment, the passive values can be selected in an independent manner to trim a setting that normalizes the value of the passive elements across chips.

For example, a nominally desired 10KΩ resistor could end up exhibiting a 6KΩ or a 14KΩ resistor from die to die in the same or different wafers. In one embodiment, a resistor is implemented with segments that may be added to or derived from the nominal value. In one embodiment, the resistor trim settings configure the number of segments added to or derived from the resistor depending on whether the final resistance value needs to be increased or decreased. In one embodiment, the resistance value may vary from 0.6x to 1.4x the typical process value.

In one embodiment, capacitors are built with a value that can be trimmed. The number of bits allocated to trim the resistors and capacitors depends on the precision of the correction required. In one embodiment, a total of 4 bits are used to trim the passive elements. In other embodiments, a different number of bits may be used to trim the passive elements.

To find the trim settings needed to correct for process changes, in one embodiment an RC dominated oscillator is used. The oscillation frequency of this oscillator is known by design due to the typical process size of the passive elements used. In one embodiment, the trim settings are determined by comparing the oscillation frequency of this oscillator to an external frequency reference. In one embodiment, the oscillator switching frequency is set by the absolute RC product value and will increase and/or decrease as the trim settings are changed. In one embodiment, a trimming FSM (Finite State Machine) steps through the passive elements' trim input settings until its frequency matches the reference frequency source (e.g., 100 MHz).

In the following description, numerous details are discussed to provide a more detailed explanation of embodiments of the present disclosure. However, it will be apparent to one of ordinary skill in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form and not in detail to avoid obscuring embodiments of the present disclosure.

It should be understood that in the respective drawings of the embodiments, signals are shown by lines. Some lines may be thicker to highlight individual signal paths and/or may have arrows at one or more ends to highlight a primary information flow direction. Rather, the lines are used with one or more example embodiments to facilitate easier understanding of a circuit or logic unit. Each signal shown may actually include one or more signals that can travel in any direction, as dictated by design requirements or constraints, and may be implemented with any suitable type of signaling scheme.

Throughout the specification and claims, the term "connected" means a direct electrical connection between the items connected without any devices therebetween. The term "coupled" means either a direct electrical connection between the connected items or an indirect connection through one or more passive or active devices therebetween. The term "circuit" means one or more passive and/or active components arranged to cooperate with each other to perform a desired function. The term "signal" means at least one current signal nal, voltage signal or data/clock signal. The meaning of "a" and "the" includes plural references. The meaning of "in" includes "in" and "on".

The term "scaling" generally refers to converting a design (schematic and layout) from one process technology to another process technology. The term "scaling" also generally refers to reducing the size of the layout and devices within the same technology node. The term "scaling" can also refer to adjusting (e.g., slowing down) a signal frequency with respect to another parameter, such as power supply level. The terms "substantially," "almost," "approximately," "near," and "about" generally refer to being within +/-20% of a target value.

Unless otherwise indicated, the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object indicates that reference is made to different examples of the same objects, and is not intended to imply that the objects so described must occur in any particular sequence, either temporally, spatially, in order, or in any other way.

For purposes of the embodiments, the transistors are metal oxide semiconductor (MOS) transistors that include drain, source, gate, and ground terminals. The transistors also include tri-gate and FinFet transistors, gate-all-around cylindrical transistors, or other devices that implement transistor functionality, such as carbon nanotubes or spintronic devices. Source and drain terminals may be identical terminals and are used interchangeably herein. Those of ordinary skill in the art will appreciate that other transistors, such as bipolar junction transistors - BJT PNP/NPN, BiCMOS, CMOS, eFET, etc., may be used without departing from the scope of the disclosure. The term "MN" indicates an n-type transistor (e.g., NMOS, NPN BJT, etc.), and the term "MP" indicates a p-type transistor (e.g., PMOS, PNP BJT, etc.).

1A shows an RC-dominated oscillator 100 used to determine trim code for trimmable passive devices according to an embodiment of the disclosure. In one embodiment, the RC-dominated oscillator 100 is independent of transistor speed and process variation, i.e., the oscillator frequency is essentially determined by the passive devices R and C. For example, the transistors used in the RC-dominated oscillator 100 contribute zero or substantially zero first order dependence on transistor speed. The RC-dominated oscillator 100 is one such example of an oscillator. Other oscillators with zero or substantially zero first order dependence on transistor speed can be used by coupling passive devices (Rs and Cs) to the transistors.

In one embodiment, RC-dominated oscillator 100 includes variable capacitor C1, variable resistors R1, R2 and R3, inverters invl, inv2, in3, inv4, inv5 and inv6. In one embodiment, a voltage at node Vx reaches the trigger point of inverter inv1 so that RC-dominated oscillator 100 oscillates. In one embodiment, R1=Rt.k, R2=Rt.(1-k) and R3=Rs. In one embodiment, at an oscillation frequency of 100MHz, Cl=3.12pF, k=0.778, Rs=2277Ω, Rt=16025Ω. In other embodiments, other values may be used to achieve a target oscillator frequency.

In one embodiment, any or some of the passive devices in the RC-dominated oscillator 100 are trimmable. In this example, 7 bits are used to trim capacitor C1. In one embodiment, a node Vo provides the output of the RC-dominated oscillator 100. In one embodiment, an RC time constant of the RC-dominated oscillator 100 determines the oscillator frequency, where the RC time constant is directly related to the resistance and capacitances of R1, R2, R3, and C1. In one embodiment, for a desired target oscillation frequency of the RC-dominated oscillator 100, the resistors and capacitor(s) are trimmed (due to process variations). In one embodiment, the trim bits are used to determine program code for trimming other passive devices in the chip.

1B shows a plot 120 of waveforms generated by the RC-dominated oscillator 100 used to determine trim code for trimmable passive devices according to an embodiment of the disclosure. It is understood that those elements of 1B , which have the same reference numbers (or names) as the elements of any other figure, can operate or function in a manner similar to that described, but are not limited to that.

$$X=\frac{R_T}{R_T+R_S}$$

$$R_O=R_S\Vert R_T$$

$$\tau =R_{O}C$$

$$t_{o1}=-\tau \cdot \text{ln}\left[1-\frac{\left(k-1\right)\cdot V_{CC}+V_{INV}}{k\cdot X\cdot V_{CC}}\right]$$

$$t_{o2}=-\tau \cdot \text{ln}\left[1-\left(\frac{1}{X}-\frac{V_{INV}}{k\cdot X\cdot V_{CC}}\right)\right]$$

$$t_{ƒ2}=-\tau \cdot \text{ln}\left[1-\frac{k\cdot V_{CC}-\left[\left(k-1\right)\cdot V_{CC}+V_{INV}\right]}{K\cdot X\cdot V_{CC}}\right]$$

$$T_{osc}=\left(t_{ƒ1}-t_{o1}\right)+\left(t_{ƒ2}-t_{o2}\right)$$

The X-axis represents time and the Y-axis represents voltage. Plot 120 shows two waveforms, voltages at nodes Vx and Vo. A portion of the RC-dominated oscillator 100 is shown on the right side of plot 120. V _INV represents the output trip point of the inverter inv1. As described with reference to 1 discussed, R1=Rt.k, R2=Rt.(1-k) and R3=Rs, where: $$0<k<1$$

$$X=\frac{R_T}{R_T+R_S}$$

$$R_O=R_S\Vert R_T$$

$$\tau =R_{O}C$$

$${\mathrm{<figure-callout\; id="1"\; label="t\; O"\; filenames="DE102014003655B4\_0025.png,DE102014003655B4\_0026.png"\; state="\{\{state\}\}">t</figure-callout>}}_O=-\tau \cdot \text{ln}\left[1-\frac{\left(k-1\right)\cdot V_{CC}+V_{INV}}{k\cdot X\cdot V_{CC}}\right]$$

$${\mathrm{<figure-callout\; id="2"\; label="t\; O"\; filenames="DE102014003655B4\_0026.png,DE102014003655B4\_0033.png"\; state="\{\{state\}\}">t</figure-callout>}}_O=-\tau \cdot \text{ln}\left[1-\left(\frac{1}{X}-\frac{V_{INV}}{k\cdot X\cdot V_{CC}}\right)\right]$$

$${\mathrm{<figure-callout\; id="2"\; label="t\; ƒ"\; filenames="DE102014003655B4\_0026.png,DE102014003655B4\_0033.png"\; state="\{\{state\}\}">t</figure-callout>}}_{ƒ}=-\tau \cdot \text{ln}\left[1-\frac{k\cdot V_{CC}-\left[\left(k-1\right)\cdot V_{CC}+V_{INV}\right]}{K\cdot X\cdot V_{CC}}\right]$$

$$T_{Osc}=\left({\mathrm{<figure-callout\; id="1"\; label="t\; ƒ"\; filenames="DE102014003655B4\_0025.png,DE102014003655B4\_0026.png"\; state="\{\{state\}\}">t</figure-callout>}}_{ƒ}-t_{O1}\right)+\left({\mathrm{<figure-callout\; id="2"\; label="t\; ƒ"\; filenames="DE102014003655B4\_0026.png,DE102014003655B4\_0033.png"\; state="\{\{state\}\}">t</figure-callout>}}_{ƒ}-t_{O2}\right)$$

$$t_{ƒ1}=t_{ƒ2}$$

wobei 1-T_OSC die Oszillierfrequenz des RC-dominierten Oszillators 100 ist.In one embodiment, if V _INV = 0.5 * V _CC , then: $${\mathrm{<figure-callout\; id="1"\; label="t\; O"\; filenames="DE102014003655B4\_0025.png,DE102014003655B4\_0026.png"\; state="\{\{state\}\}">t</figure-callout>}}_O={\mathrm{<figure-callout\; id="2"\; label="t\; O"\; filenames="DE102014003655B4\_0026.png,DE102014003655B4\_0033.png"\; state="\{\{state\}\}">t</figure-callout>}}_O$$

$${\mathrm{<figure-callout\; id="1"\; label="t\; ƒ"\; filenames="DE102014003655B4\_0025.png,DE102014003655B4\_0026.png"\; state="\{\{state\}\}">t</figure-callout>}}_{ƒ}={\mathrm{<figure-callout\; id="2"\; label="t\; ƒ"\; filenames="DE102014003655B4\_0026.png,DE102014003655B4\_0033.png"\; state="\{\{state\}\}">t</figure-callout>}}_{ƒ}$$

where 1-T _OSC is the oscillation frequency of the RC-dominated oscillator 100.

1C shows an example of code 130 for capacitor C1 from 1A according to an embodiment of the disclosure. It is understood that those elements of 1C , which have the same reference numbers (or names) as the elements of any other figure, can operate or function in a manner similar to that described, but are not limited to that.

In this example, 7 binary bits are used to calculate the actual capacitance of capacitor C1 from 1A As the capacitance of C1 increases, the frequency of the oscillation decreases until it exceeds a reference frequency. In one embodiment, a change in the binary code required to hit this target frequency is a direct indication of an RC product deviation from the expected value.

2 shows a resistor 200 with trimmable resistance unit cell 201 according to an embodiment of the disclosure. It is understood that those elements of 2 , which have the same reference numbers (or names) as the elements of any other figure, can operate or function in a manner similar to that described, but are not limited to that.

In one embodiment, resistor 200 includes a first pass gate PG1. In one embodiment, PG1 may be operated (via control signals Cr21 and C21_b, where Cr21_b is the inverse of Cr21) to short nodes n21 and n23 or leave them open. In one embodiment, unit cell 201 includes a first resistor Rtl, second resistor Rt2, and second pass gate PG2. In one embodiment, second pass gate PG2 may be operated (via control signals Cr22 and C22_b, where Cr22_b is the inverse of Cr22) to short nodes n22 and n23 or leave them open. In one embodiment, PG2 is used to trim the resistance magnitude of resistor 200, while PG1 is used to program a nominal value of the resistor.

In this example, when PG1 is on, the nominal value of resistor 200 is zero ohms, and when PG1 is off, the nominal value of resistor 200 is either Rt1+Rt2 or Rt1 (depending on whether PG2 is on or off). In this embodiment, resistor 200 is trimmable by one bit (due to a pass gate in PG2) and programmable by one bit to a nominal value (due to a pass gate in PG1). In one embodiment, resistors R1, R2, and R3 of RC-dominated oscillator 100 include the same resistance as resistor 200. In one embodiment, trim code is used to trim R1, R2, and R3 (directly or indirectly, for example, by using a lookup table and/or formula) to trim resistor 200 across PG2.

3 shows a trimmable resistor 300 according to another embodiment of the disclosure. In this embodiment, the trimmable resistor 300 includes a first terminal n31 and a second terminal n36. The exemplary embodiment of the trimmable resistor 300 is a 2-bit trimmable resistor (with 4-to-1 decoder), where the two bits are used to control pass gates. For example, pass gate PG31 is controllable by trim signal Cr31 (and its inverse bit Cr31_b), pass gate PG32 is controllable by trim signal Cr32 (and its inverse bit Cr32_b), pass gate PG33 is controllable by trim signal Cr33 (and its inverse bit Cr33), and pass gate PG34 is controllable by trim signal Cr34 (and its inverse bit Cr34_b). In other In other embodiments, a different number of trimmable bits may be used. In one embodiment, the trim signals are decoded trim bits using either a decoder or a lookup table.

In one embodiment, a unit cell of trimmable resistor 300 includes a resistor coupled to a pass gate. For example, a resistor R31 coupled to pass gate PG31 forms a first unit cell, R32 coupled to pass gate PG32 forms a second unit cell, R33 coupled to pass gate PG33 forms a third unit cell, and R34 coupled to pass gate PG34 forms a fourth pass cell. In this embodiment, PG31 is coupled to nodes n36 and n32, PG32 is coupled to nodes n36 and n33, PG33 is coupled to n36 and n34, and PG34 is coupled to n36 and n35. In one embodiment, resistors R1, R2, and R3 of RC-dominated oscillator 100 use the same trimmable resistor 300. In other embodiments, trimming code(s) used for R1, R2, and R3 of the RC-dominated oscillator is also applied to pass gates PG31, PG32, PG33, and PG34.

4 shows a trimmable resistor 400 with programmable resistance according to an embodiment of the disclosure. In this embodiment, a first terminal of the trimmable resistor 400 is node n41 and a second terminal of the trimmable resistor is node n455. In one embodiment, the trimmable resistor 400 includes unit cells 401, 402, 403, 404 and 40N, where 'N' is an integer greater than 4. In one embodiment, each unit cell is similar to the unit cell 201 of 2 .

Referring again to 4 In one embodiment, resistors R1, R2, and R3 of RC-dominated oscillator 100 use the same trimmable resistor unit cell 401. In one embodiment, trimming code(s) used for R1, R2, and R3 of RC-dominated oscillator 100 is/are also applied (directly or indirectly, e.g., by using a lookup table and/or formula) to pass gates of unit cells 401, 402, 403, 404, and 40N, i.e., PG42, PG44, PG46, PG48, and PG4N2. In such an embodiment, control signals to the pass gates are the same, i.e. Cr42 (and Cr42_b which is inverse of Cr42), Cr44 (and Cr44_b which is inverse of Cr44), Cr46 (and Cr46_b which is inverse of Cr46), Cr48 (and Cr48_b which is inverse of Cr48) and Cr4N2 (and Cr4N2_b which is inverse of CrN2) are controlled by the same signal.

In one embodiment, pass gates PG41 (coupled between nodes n41 and n43), PG43 (coupled between nodes n43 and n44), PG45 (coupled between nodes n43 and n45), PG47 (coupled between nodes n43 and n46), and PG4N1 (coupled between node n43 and node n4N) are used to program a nominal value for resistor 400, where 'N' is a number greater than 6. In one embodiment, control signals to the pass gates are different and are used to adjust a nominal value for resistor 400, i.e. Cr41 (Cr41_b which is inverse of Cr41), Cr43 (and Cr43_b which is inverse of Cr43), Cr45 (and Cr45_b which is inverse of Cr45), Cr47 (and Cr47_b which is inverse of Cr47) and Cr4N1 (and Cr4N1_b which is inverse of Cr4N1) are controlled by different signals.

5 shows a trimmable capacitor 500 with programmable capacitance according to an embodiment of the disclosure. The first terminal of the trimmable capacitor 500 is n41 and the second terminal is n52. In one embodiment, the trimmable capacitor 500 comprises unit cells 501-504. In other embodiments, a different number of unit cells may be used. In order not to obscure the embodiments, a unit cell 501 will be described. The same description applies to other unit cells, i.e., 502-504.

In one embodiment, unit cell 501 includes capacitor C50 to provide base capacitance, capacitor 51 is coupled to pass gate PG51, capacitor 52 is coupled to pass gate PG52, and capacitor 53 is coupled to pass gate PG53. In one embodiment, unit cell 501 is a 3-bit trimmable unit cell using the three pass gates. In other embodiments, a different number of trimmable bits may be used. In one embodiment, capacitor C50 is coupled to nodes n51 and n53.

In one embodiment, pass gate PG51 is controllable by signals Cr51 and Cr51_b (where Cr51_b is the inverse of Cr51) and operable to couple capacitor C51 to node n53 such that capacitor C51 is in parallel with capacitor C50. In one embodiment, pass gate PG52 is controllable by signals Cr52 and Cr52_b (where Cr52_b is the inverse of Cr52) and operable to couple capacitor C52 to node n53 such that capacitor C52 is in parallel with capacitor C50. is in parallel. In one embodiment, pass gate PG53 is controllable by signals Cr53 and Cr53_b (where Cr53_b is the inverse of Cr53) and is operable to couple capacitor C53 to node n53 such that capacitor C53 is in parallel with capacitor C50. In one embodiment, other unit cells (i.e., unit cells 50, 503, and 504) have their pass gates controlled by the same signals as the pass gates of unit cell 501. In this embodiment, the signals used to control pass gates PG51, PG52, and PG53 trim the trimmable capacitor due to process changes. In one embodiment, these signals are associated with the program code (also called trim code) acquired from RC-dominated oscillator 100.

In one embodiment, capacitors C51, C52, and C53 are binary weighted. In another embodiment, capacitors C51, C52, and C53 are thermometer weighted. In one embodiment, pass gates PG51, PG52, and PG53 are sized proportional to the size of the capacitors to which they are coupled. For example, if capacitors C51, C52, and C53 are binary weighted, the size of pass gates PG51, PG52, and PG53 is also binary weighted.

In one embodiment, trimmable capacitor 500 includes pass gate PG54 coupled between nodes n53 and n52, pass gate PG55 coupled between nodes n54 and n52, pass gate PG56 coupled between nodes n55 and n52, and pass gate PG57 coupled between nodes n56 and n52. In this embodiment, pass gates PG54, PG55, PG56, and PG57 are used to program a nominal value of trimmable capacitor 500.

In one embodiment, pass gate PG54 is controlled by signals Cr54 and Cr54_b (where Cr54_b is the inverse of Cr54) to couple unit cell 501 to node n52. In one embodiment, pass gate PG55 is controlled by signals Cr55 and Cr55_b (where Cr55_b is the inverse of Cr55) to couple or decouple unit cell 502 to node n52. In one embodiment, pass gate PG56 is controlled by signals Cr56 and Cr56_b (where Cr56_b is the inverse of Cr56) to couple or decouple unit cell 503 to node n52. In one embodiment, pass gate PG57 is controlled by signals Cr57 and Cr57_b (where Cr57_b is the inverse of Cr57) to couple or decouple unit cell 502 from node n52.

6 shows a flow chart 600 for trimming passive devices according to an embodiment of the disclosure. It is understood that those elements of 6 , which have the same reference numbers (or names) as the elements of any other figure, can operate or function in a manner similar to that described, but are not limited to that.

Although the blocks in the flowcharts are 6 are shown in a particular order, the order of the steps may be modified. Thus, the embodiments shown may be performed in a different order, and some steps/blocks may be performed in parallel. Some of the blocks and/or operations shown in 6 are optional according to certain embodiments. The numbering of the illustrated blocks is for clarity and is not intended to dictate an order of operations in which the various blocks must occur. Furthermore, operations of the various flows may be used in a variety of combinations.

In one embodiment, at block 601, a target oscillation frequency is determined for the RC-dominated oscillator 100. In one embodiment, different chips include the same RC-dominated oscillator 100. At block 602, trim code associated with the Rs and Cs of the RC-dominated oscillator 100 is determined to achieve the target oscillation frequency. In one embodiment, trim code is determined for other RC-dominated oscillators 100 in other chips to achieve the same target frequency. As discussed in the Background section, because resistances and capacitances of resistors and capacitors differ between chips (e.g., by up to 4x), trim codes for the RC-dominated oscillators 100 for different chips also vary in achieving the same target oscillation frequency. In one embodiment, the trim code for the RC-dominated oscillator is determined by a tester as described with reference to 7 described.

Referring again to 6 at block 603, the trim code (associated with the RC-dominated oscillator 100) and the desired nominal value for Rs and Cs are entered into a formula or lookup table (LUT) to determine a program code for trimming Rs and Cs of the trimmable resistor (e.g., trimmable resistor 200, 300, 400) and/or capacitor (e.g., trimmable capacitor 500). Such a LUT and/or formula is described with reference to 7 described.

Referring again to 6 program code is applied to trim Rs and Cs of the trimmable resistor (e.g., trimmable resistor 200, 300, 400) and/or capacitor (e.g., trimmable capacitor 500) at block 604 to compensate for process variations.

In one embodiment, the method 600 operates in a loop, where in each pass the oscillator frequency is compared to a reference frequency and, depending on whether the oscillator is faster or slower, the trim code is incremented or decremented to reduce or increase the oscillator frequency to bring it closer to the reference (much like an analog-to-digital converter).

Program software code/instructions associated with flowchart 600 that are executed to implement embodiments of the disclosed subject matter may be implemented as part of an operating system or a particular application, component, program, object, module, routine, or other sequence of instructions or organization of sequences of instructions, referred to as "program software code/instructions," "operating system program software code/instructions," "application program software code/instructions," or simply "software."

The program software code/instructions associated with flowchart 600 typically include one or more instructions stored at various times in various tangible storage and archiving devices in the computing device or on the periphery thereof that, when retrieved/read by the computing device and executed by the computing device as described herein, cause a computing device to perform functions, functionality, and operations necessary to perform a method, such as to perform elements that include various aspects of the function, functionality, and operations of the method(s) that represent an aspect of the disclosed subject matter.

For purposes of this disclosure, a module is a software, hardware, or firmware (or combinations thereof) system, process, or functionality or component thereof that performs or enables the processes, structures, and/or functions, functionality, and/or operations described herein (with or without human interaction or intervention) as if they were performed by the designated module. A module may include submodules. Software components of a module may be stored on a tangible machine-readable medium. Modules may be integral with, or loaded and executed by, one or more servers. One or more modules may be encapsulated in a machine or an application.

A tangible machine-readable medium may be used to store program software code/instructions and data that, when executed by a computing device, cause the computing device to perform(s) a method as may be defined in one or more of the appended claims directed to the disclosed subject matter. The tangible machine-readable medium may include storing the executable software program code/instructions and data in various tangible locations, including, for example, but not limited to, ROM, volatile RAM, non-volatile memory and/or cache and/or other tangible storage as mentioned in the present application. Portions of this program software code/instructions and/or data may be stored in any of these storage and/or archiving devices. Furthermore, the program software code/instructions may be retrieved from other storage, including, for example, through centralized servers or point-to-point networks and the like, including the Internet. Different pieces of software program code/instructions and data may be obtained at different times and in different communication sessions or in the same communication session.

The software program code/instructions and data may be obtained in full prior to execution of a particular software program or application by the computing device. Alternatively, portions of the software program code/instructions and data may be obtained dynamically, for example, just in time when they are needed for execution. Alternatively, any combination of these ways of obtaining the software program code/instructions and data may occur, for example, for different applications, components, programs, objects, modules, routines, or other sequences of instructions or organization of sequences of instructions. Thus, it is not necessary that the data and instructions be present in full on a tangible machine-readable medium at any particular time.

Examples of tangible computer-readable media include, but are not limited to, recordable and non-recordable media types such as, among others, volatile and non-volatile storage devices, read only memory (ROM), random access memory (RAM), flash memory devices, floppy and other removable disks, magnetic disk storage media, optical storage media (e.g., compact disk read-only memory (CD ROMs), digital versatile disks (DVDs), etc. The software program code(s) may be temporarily stored in digital tangible communication links while electrical, optical, acoustic or other forms of traveling signals are implemented through such tangible communication links, such as carrier waves, infrared signals, digital signals, etc.

Generally, a tangible machine-readable medium includes any tangible mechanism that provides information in a form accessible to a machine (e.g., a computing device) (i.e., stores and/or transmits information in digital form, e.g., data packets), embodied in, for example, a communications device, a computing device, a network device, a personal digital assistant, a manufacturing tool, a mobile communications device, whether or not downloadable and capable of executing applications and sub-applications from the communications network, such as the Internet, e.g., an ^iPhone® , ^Blackberry® Droid® or the like, or any other device including a computing device. In one embodiment, the processor-based system (e.g., as described in 8 shown) in the form of, or is included in, a PDA, a cellular phone, a notebook computer, a tablet, a game console, a set-top box, an embedded system, a television, a personal desktop computer, etc. Alternatively, the conventional communications applications and sub-application(s) may be used in some embodiments of the disclosed subject matter.

7 shows an RC configuration flow 700 using a lookup table (LUT) and/or formula for trimming capacitor and resistor of a circuit (e.g., compensator of a voltage regulator) using code from the RC dominated oscillator 100 1A according to an embodiment of the disclosure. It is understood that those elements of 7 , which have the same reference numbers (or names) as the elements of any other figure, can operate or function in a manner similar to that described, but are not limited to that.

In one embodiment, a tester 701 generates a trim code 'x' for the resistors of the RC-dominated oscillator 100 using an RC trim FSM (Finite State Machine). For example, the RC trim FSM increments using control bits to determine a resistance value of the resistors R1, R2 and/or R3 from 1A to achieve a target oscillation frequency at Vo. In one embodiment, trim code 'x' is compared to trim code 'y' to set a value for a variable 'rtrim'. Trim code 'y' is a trim code (also called a default trim code) that the RC trim FSM would generate if the RC product (which determines the target oscillation frequency of the RC dominated oscillator 100) was at the target value. In one embodiment, if the RC product is already on target (e.g., by chance), the FSM ends up at the default trim code, i.e., the RC does not need to be adjusted.

In one embodiment, trim code 'x' and variable 'rtrim' are received from a LUT or formula for generating trim code for resistors and/or capacitors in the chip. In one embodiment, the LUT and/or formula are managed and stored by a power control unit (PCU). In other embodiments, the LUT and/or formula are managed and stored by another logic unit. In one embodiment, PCU 702 receives configuration inputs C1config[3:0], C2config[2:0], C3config[4:0], where C1config, C2config, and C3config are the target values (or nominal values) for some of the passive elements of the compensator.

$${\text{C}}_{\text{1b}}=\mathrm{230,7}/47=\mathrm{4,909}$$

$${\text{C}}_{\text{1c}}=257/47=\mathrm{5,4681}$$

Referring to capacitor C1 from 1A and 1C In one embodiment, the following constants are stored in the LUT of the PCU 702. $${\text{C}}_{\text{1a}}=356.4/47=\mathrm{7,584}$$

$${\text{C}}_{\text{1b}}=230.7/47=\mathrm{4,909}$$

$${\text{C}}_{\text{1c}}=257/47=\mathrm{5,4681}$$

• a=ConfigBase/LSB,
• b=ConfigLSB/LSB,
• c=Base/LSB.

Where:

• a=ConfigBase/LSB,
• b=ConfigLSB/LSB,
• c=Base/LSB.

Where Base and LSB are the nominal schematic values of the always connected base capacitor and the LSB of the binary selectable capacitor; ConfigBase and ConfigLSB are capacitance values that a designer can determine using the circuit that includes base and LSB capacitors. capacitors. In one embodiment, any capacitance value can be achieved with Base and LSB despite process variation because the design knows what the process variation is from the result of the RC trim FSM. In one embodiment, ConfigBase and ConfigLSB are larger (ie coarser) than Base and LSB, respectively.

$$N=\frac{1}{\frac{C_{\mathrm{1,}BASE}}{C_{\mathrm{1,}LSB}}+y}$$

$$\begin{array}{l}\mathrm{\Delta }R\left[i\right],i\in \left\{\mathrm{0,1}\right\}\\ \frac{1}{\mathrm{\Delta }R\left[i\right]},i\in \left\{\mathrm{0,1}\right\}\end{array}$$

In one embodiment, to calculate a selection code (i.e., trimmable bits for a passive device), the following trim constants are stored by PCU 702 in a storage medium (e.g., ROM): $$M=\frac{\frac{{\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="DE102014003655B4\_0025.png,DE102014003655B4\_0026.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{1,}BA\mathrm{<figure-callout\; id="1"\; label="S\; E\; C"\; filenames="DE102014003655B4\_0025.png,DE102014003655B4\_0026.png"\; state="\{\{state\}\}">S</figure-callout>}E}}{C_{}}}{\frac{C_{}}{}}$$

$$N=\frac{1}{\frac{{\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="DE102014003655B4\_0025.png,DE102014003655B4\_0026.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{1,}BA\mathrm{<figure-callout\; id="1"\; label="S\; E\; C"\; filenames="DE102014003655B4\_0025.png,DE102014003655B4\_0026.png"\; state="\{\{state\}\}">S</figure-callout>}E}}{C_{}}+y}$$

$$\begin{array}{l}\mathrm{\Delta }R\left[i\right],i\in \left\{0.1\right\}\\ \frac{1}{\mathrm{\Delta }R\left[i\right]},i\in \left\{0.1\right\}\end{array}$$

Where ΔR is the factor by which the nominal resistance value is modified after the RC trim result is known. For example, ΔR[0]=sqrt(2) and Δr[1]=1/sqrt(2). In this example, R[0] is always equal to 2x R[1]. In one embodiment, index 'i' is selected based on whether the RC trim result is greater or less than the target code.

$$N=\frac{1}{\frac{257}{47}+55}=0.01654$$

Continuing the example, assume that an ideal trim code is 'y'=55 and actual trim code is 'x'. 'M' and 'N' are then determined as: $$M=\frac{\frac{257}{47}}{\frac{257}{47}+55}=0.09043$$

$$N=\frac{1}{\frac{257}{47}+55}=0.01654$$

Where ‘M’ and ‘N’ are constants that are determined by a structure of the capacitor C1 1A and nominal trim code.

$$\text{N}=\mathrm{0,01654,}$$

$$\mathrm{\Delta }\text{R}\left[0\right]=\mathrm{0,7071,}$$

$$\mathrm{\Delta }\text{R}\left[1\right]=\mathrm{1,414.}$$

PCU 702 then stores: $$M=\mathrm{0.09043,}$$

$$\text{N}=\mathrm{0.01654,}$$

$$\mathrm{\Delta }\text{R}\left[0\right]=\mathrm{0.7071,}$$

$$\mathrm{\Delta }\text{R}\left[1\right]=\mathrm{1,414.}$$

In one embodiment, the following rtrim values are stored or merged: If 'x' is less than or equal to 'y', then rtrim=0, if 'x' is greater than 'y', then rtrim=1. Continuing the example, the following ΔRs are calculated by PCU 702: If rtrim=0, then ΔR=ΔR[0], and if rtrim=1, then ΔR=ΔR[1]. In one embodiment, the formula for calculating C _select is given as: $$C_{select}=\left(C_a+C_b\cdot COneiG\right)\cdot \frac{1}{\mathrm{\Delta }R}\cdot \left(M+N\cdot x\right)-C_c$$

Continuing the RC configuration flow 700, the rtrim value, Cselect values (for trimming capacitors), and R configuration values (for trimming capacitors) are used to trim the capacitors and resistors of a circuit that includes resistors and capacitors. In this exemplary embodiment, the circuit is a compensator 703 used in a voltage regulator.

8 shows an exemplary embodiment of the compensator circuit 800 (the same as 703, and also referred to as a differential type 3 compensator) that includes trimmable passive devices that are also trimmed according to the embodiments discussed.

In one embodiment, differential type-3 compensator 800 includes a differential amplifier (AMP), passive resistors with values R1a, R1b, dual passive resistors R2 and R3, dual passive capacitors C1, C2 and C3, and unity gate buffers (UGB). In one embodiment, UGB is optional. In one embodiment, R1b=R1/2 and R1a=R1.

In one embodiment, differential inputs (signal and ground) for Vout and Vref are received by the passive devices and eventually as inputs to the differential amplifier. The term "dacgrndsense" refers to the ground node near a digital-to-analog converter using a voltage regulator. The term "loadvoltagesense" refers to node Vout near the load of the voltage regulator. The term "loadgndsense" refers to a ground node near the load. The term "dacvidvoltage" refers to reference voltage Vref.

In one embodiment, the resistance network comprises passive resistors with values ten R1a and R1b such that Vout=Vref x R1a/R1b. In one embodiment, (R1a/R1b)=2 shall support conditions when Vout is greater than Vccags, where Vccags is an analog power supply. In other embodiments, other ratios for R1a/R1b may be used.

In one embodiment, dual passive devices (ie, R2, R3, C1, C2, and C3) are coupled together as in 8 In one embodiment, the coupling of the dual passive devices is such that the frequency response (ie, of Vout/Vfb) is preserved. In one embodiment, the coupling of the dual passive devices is such that any common mode noise at voltage_sense/ground_sense or reference_voltage/reference_ground nodes is removed.

In one embodiment, the coupling of the dual passive devices is such that any substrate or supply noise coupled through the parasitic passive elements into the positive and negative inputs of the amplifier (AMP) is approximately identical, such that it has no net (or substantially net zero) effect on Vfb. In one embodiment, the passive devices are trimmed to ensure that any RC time constant remains approximately on target despite process variation, e.g., systematic process variation.

In one embodiment, UGB is used to reduce the capacitive load of the amplifier output. In such an embodiment, a single stage amplifier design may be used so that the differential amplifier maintains phase margin. In one embodiment, a design with multiple instances of the amplifier with gated output stage is used so that the compensator bandwidth can be configured to reduce power consumption.

Referring again to 7 Cselect includes C1sel[6:0], C2sel[4:0] and C3sel[7:0] provided by PCU 702 to compensator 703. R configuration values include R1config[1:0], R2config[3:0] and R3config[2:0]. The Rsel value depends on rtrim. If rtrim=0, Rsel=Rconfig, and if rtrim=1, Rsel=2 x Rconfig, where Rsel is “ΔR[i]” as described with reference to 7 discussed.

9 shows an intelligent device or a computer system or a SoC (system-on-chip) with trimmable passive devices and apparatus and methods for trimming these passive devices according to an embodiment of the disclosure. It is understood that those elements from 9 , which have the same reference numbers (or names) as the elements of any other figure, can operate or function in a manner similar to that described, but are not limited to that.

9 16 shows a block diagram of one embodiment of a mobile device in which flat surface interface connectors could be used. In one embodiment, computing device 1600 represents a mobile computing device, such as a computer tablet, a cell phone or smartphone, a wireless e-reader, or other wireless mobile device. It should be understood that certain components are shown generically and not all components of such a device are shown in computing device 1600.

In one embodiment, computing device 1600 includes a first processor 1610 with trimmable passive devices according to the embodiments discussed. Other blocks of computing device 1600 may also include the trimmable passive devices of the embodiments. The various embodiments of the present disclosure may also include a network interface within 1670, such as a wireless interface, so that a system embodiment may be included in a wireless device, such as a cellular phone or personal digital assistant.

In one embodiment, processor 1610 (and processor 1690) may include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 1610 include executing an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting computing device 1600 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

In one embodiment, computing device 1600 includes an audio subsystem 1620 that represents hardware (e.g., audio hardware and audio circuitry) and software (e.g., drivers, codecs) components associated with providing audio functions for the computing device. Audio functions may include speaker and/or headphone output, as well as microphone input. Devices for such Functions may be integrated into the computing device 1600 or coupled to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by the processor 1610.

The display subsystem 1630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600. The display subsystem 1630 includes a display interface 1632 that includes the respective screen or hardware device to provide a display to the user. In one embodiment, the display interface 1632 includes logic separate from the processor 1610 to perform at least some processing related to the display. In one embodiment, the display subsystem 1630 includes a touchscreen (or touchpad) device that provides both output and input to the user.

I/O controller 1640 provides hardware devices and software components related to interaction with a user. I/O controller 1640 may be operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 630. Furthermore, I/O controller 1640 provides a connection point for other devices that connect to computing device 1600 through which a user may interact with the system. For example, devices that may connect to computing device 1600 could include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with particular applications, such as card readers or other devices.

As mentioned above, the I/O controller 1640 may interact with the audio subsystem 1620 and/or display subsystem 1630. For example, input from a microphone or other audio device may provide input or commands for one or more applications and functions of the computing device 1600. Furthermore, audio output may be provided instead of or in addition to display output. In another example, if the display subsystem 1630 includes a touchscreen, the display device may also serve as an input device that may be at least partially managed by the I/O controller 1640. There may also be other touchpads or switches on the computing device 1600 to provide I/O functions managed by the I/O controller 1640.

In one embodiment, the I/O controller 1640 manages devices such as accelerometers, cameras, light sensors, or other environmental sensors or other hardware that may be included in the computing device 1600. The input may be part of direct user interaction, as well as providing environmental inputs to the system to affect its operations (such as filtering for noise, adjusting indicators for brightness detection, applying a flash to a camera, or other features).

In one embodiment, computing device 1600 includes power management 1650 that manages battery power consumption, battery charging, and features related to power saving operation. Storage subsystem 1660 includes storage devices for storing information in computing device 1600. Storage may include non-volatile (state that does not change when power to the storage device is interrupted) and/or volatile (state is indeterminate when power to the storage device is interrupted) storage devices. Storage subsystem 1660 may store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of computing device 1600.

Elements of embodiments are also provided as a machine-readable medium (e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions for implementing any processes discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD-ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) that may be transmitted from a remote computer (e.g., a server) to a requesting computer (e.g., a client) using data signals over a communications link (e.g., a modem or network connection).

Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable computing device 1600 to communicate with external devices. Computing device 1600 could include separate devices such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

Connectivity 1670 may include several different types of connectivity. To generalize, computing device 1600 is shown with cellular connectivity 1672 and wireless connectivity 1674. Mobile connectivity 1672 generally refers to mobile network connectivity provided by wireless transmission devices, such as via GSM (global system for mobile communications) or variants or derivatives, CDMA (code division multiple access) or variants or derivatives, TDM (time division multiplexing) or variants or derivatives, or other mobile service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not mobile and may include personal networks (such as Bluetooth, near field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communications.

Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) for establishing peripheral connections. It is understood that computing device 1600 may be a peripheral device (“to” 1682) to other computing devices, as well as have peripheral devices (“from” 1684) connected to it. Computing device 1600 typically includes a “docking” port for connecting to other computing devices for purposes such as managing (e.g., downloading and/or uploading, modifying, synchronizing) content on computing device 1600. Furthermore, a docking port may enable computing device 1600 to connect to certain peripherals that enable computing device 1600 to control content output to, for example, audiovisual or other systems.

In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1600 may establish peripheral connections 1680 through common or standards-based connectors. Common types may include a Universal Serial Bus (USB) connector (which may include any number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

References in the specification to "an embodiment," "one (1) embodiment," "some embodiments," or "other embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various manifestations of "an embodiment," "one (1) embodiment," or "some embodiments" do not necessarily all refer to the same embodiments. If the specification states that a component, feature, structure, or characteristic "may" or "could" be included, that particular component, feature, structure, or characteristic may not be included. If the specification or claim refers to "an" element, that does not mean that only one of the elements is present. If the specification or claims refer to "another" element, that does not preclude more than one of the other elements from being present.

Moreover, the specific features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment wherever the specific features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

While the disclosure has been described in connection with specific embodiments thereof, many alternatives, modifications, and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures, such as Dynamic RAM (DRAM), may utilize the embodiments discussed. The embodiments of the disclosure are intended to include all such alternatives, modifications, and variations as being within the broad scope of the appended claims.

Furthermore, well-known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the illustrated figures for simplicity of illustration and discussion and in order not to obscure the disclosure. Furthermore, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure and also in view of the fact that that details regarding implementation of such block diagram arrangements will depend heavily on the platform within which the present disclosure is to be implemented (i.e., such details should be well within the knowledge of one of ordinary skill in the art). Where specific details (e.g., circuits) are set forth to describe example embodiments of the disclosure, it will be apparent to one of ordinary skill in the art that the disclosure may be practiced without or with modification of those specific details. The description should therefore be considered illustrative and not restrictive.

The following examples are of further embodiments. Statements in the examples may be used anywhere in one or more embodiments. Any optional features of the apparatus described herein may also be implemented with respect to a method or process.

For example, in one embodiment, a device comprises: a resistor-capacitor (RC) dominated oscillator that is independent of first order transistor speed dependence, wherein the RC dominated oscillator includes one or more resistors and capacitors having programmable resistance and programmable capacitance, and wherein the RC dominated oscillator is to generate an output signal having a frequency that depends substantially on values of the programmable resistance and programmable capacitance; and a trimmable resistor or capacitor operable to be trimmed to compensate for process variations according to program code associated with the programmable resistance and programmed capacitance of the RC dominated oscillator.

In one embodiment, each resistor of the RC dominated oscillator comprises: a first resistor coupled in series with the first resistor; a first pass gate operable to short the first and second resistors; and a second pass gate operable to short the second resistor. In one embodiment, the first pass gate is controllable by one or more signals associated with the program code. In one embodiment, the trimmable resistor comprises a unit cell, the unit cell including: a first resistor; a second resistor coupled in series with the first resistor; and a pass gate operable to short the second resistor.

In one embodiment, the pass gate is controllable by one or more signals associated with the program code. In one embodiment, the trimmable resistor comprises a unit cell, the unit cell including: a resistor; and a pass gate operable to couple the resistor to another component. In one embodiment, the pass gate is controllable by one or more signals associated with the program code. In one embodiment, each capacitor of the RC dominated oscillator comprises: a first capacitor; and a plurality of capacitors operable to couple in parallel with the first capacitor via a corresponding plurality of pass gates, and wherein the plurality of pass gates is controllable by one or more signals associated with the program code.

In one embodiment, the trimmable capacitor comprises a unit cell, the unit cell including: a first capacitor; and a plurality of capacitors operable to be coupled in parallel with the first capacitor via a corresponding plurality of pass gates, and wherein the plurality of pass gates are controllable by one or more signals associated with the program code. In one embodiment, the apparatus further comprises a lookup table (LUT) to translate the program code into code for trimming the trimmable resistor or capacitor. An embodiment further comprises a storage medium having instructions stored thereon that, when executed, cause logic to translate the program code into code for trimming the trimmable resistor or capacitor. In one embodiment, the trimmable resistor or capacitor are part of a voltage regulator.

In another example, in one embodiment, a method comprises: determining a target frequency; operating a resistor-capacitor (RC) dominated oscillator that is independent of a first order speed dependence of a transistor to achieve a target frequency, wherein the RC dominated oscillator includes one or more resistors and capacitors having programmable resistance and programmable capacitance, and wherein the RC dominated oscillator is to generate an output signal having the target frequency dependent substantially on values of the programmable resistance and programmable capacitance; and trimming a trimmable resistor or capacitor to compensate for process variations. according to a program code corresponding to the target frequency, the program code being associated with the programmable resistance and the programmable capacitance of the RC-dominated oscillator.

In one embodiment, the trimmable capacitor comprises: a first resistor; a second resistor coupled in series with the first resistor; and a pass gate operable to short the second resistor. In one embodiment, the method further comprises controlling the pass gate through one or more signals associated with the program code. In one embodiment, the method comprises translating the program code to trim the trimmable resistor or capacitor using a lookup table (LUT).

In another example, in one embodiment, a system comprises: a memory unit; a processor coupled to the memory unit, the processor including: a resistor-capacitor (RC) dominated oscillator that is independent of first order transistor speed dependence, the RC dominated oscillator including one or more resistors and capacitors with programmable resistance and programmable capacitance, and the RC dominated oscillator to generate an output signal having a frequency that depends substantially on values of the programmable resistance and programmable capacitance; and a trimmable resistor or capacitor operable to be trimmed according to program code associated with the programmable resistance and programmable capacitance of the RC dominated oscillator to compensate for process variations; and a wireless interface to enable the processor to communicate with another device. In one embodiment, the trimmable resistor comprises a unit cell, the unit cell including: a first resistor, a second resistor coupled in series with the first resistor; and a pass gate operable to short the second resistor, the pass gate being controllable by one or more signals associated with the program code.

In one embodiment, the trimmable capacitor comprises: a unit cell, the unit cell including: a first capacitor; and a plurality of capacitors operable to be coupled in parallel with the first capacitor via a corresponding plurality of pass gates, and wherein the plurality of pass gates are controllable by one or more signals associated with the program code. In one embodiment, the system further comprises a display unit to display content processed by the processor.

Claims (14)

Apparatus comprising: an RC-dominated oscillator (100) including a resistor (200, 300) and/or a capacitor (500) or a plurality of resistors (200, 300) and/or a plurality of capacitors (500) with programmable resistance and programmable capacitance that are configured to be adjusted until the RC-dominated oscillator (100) produces a predetermined target frequency; a lookup table for storing configuration values of trimmable resistors (200, 300) and/or trimmable capacitors (500); and a circuit with trimmable resistors (200, 300) and/or trimmable capacitors (500) configured to be adjusted based on the configuration values. Device according to Claim 1 , characterized in that each resistor (200, 300) of the RC-dominated oscillator (100) comprises: a first resistor (200, 300); a second resistor (200, 300) coupled in series with the first resistor (200, 300); a first pass gate operable to short-circuit the first resistor (200, 300) and the second resistor (200, 300); and a second pass gate operable to short-circuit the second resistor (200, 300). Device according to Claim 2 , characterized in that the first pass gate is controllable by one or more signals associated with a program code specifying the configuration values. A device according to any preceding claim, characterized in that one of the trimmable resistors (200, 300) comprises a unit cell (201), the unit cell (201) including: a first resistor (200, 300); a second resistor (200, 300) coupled in series with the first resistor (200, 300); and a pass gate operable to short-circuit the second resistor (200, 300). Device according to Claim 4 , characterized in that the passage gate can be controlled by one or more signals connected to the program code. A device according to any preceding claim, characterized in that one of the trimmable resistors (200, 300) comprises a unit cell (201), the unit cell (201) including: a resistor (200, 300); and a pass gate operable to couple the resistor (200, 300) to another component. Device according to Claim 6 , characterized in that the pass gate is controllable by one or more signals which are associated with a program code. Apparatus according to any preceding claim, characterized in that each capacitor (500) of the RC-dominated oscillator (100) comprises: a first capacitor (500); and a plurality of capacitors (500) operable to be coupled in parallel with the first capacitor (500) via a corresponding plurality of pass gates, and in that the plurality of pass gates are controllable by one or more signals associated with program code. Apparatus according to any preceding claim, characterized in that one of the trimmable capacitors (500) comprises a unit cell (501), the unit cell (501) including: a first capacitor (500); and a plurality of capacitors (500) operable to be coupled in parallel with the first capacitor (500) via a corresponding plurality of pass gates, and in that the plurality of pass gates are controllable by one or more signals associated with the program code. Apparatus according to any preceding claim, wherein the lookup table is for translating program code for trimming one of the trimmable resistors (200, 300) or the trimmable capacitors (500). The apparatus of any preceding claim, further comprising a storage medium containing instructions that, when executed, cause logic to translate program code into code for trimming one of the trimmable resistors (200, 300) or the trimmable capacitors (500). Device according to one of the preceding claims, characterized in that one of the trimmable resistors (200, 300) or the trimmable capacitors (500) is part of a voltage regulator. A method comprising: operating an RC-dominated oscillator (100) to achieve a predetermined target frequency, the RC-dominated oscillator (100) including a resistor (200, 300) and/or a capacitor (500) or a plurality of resistors (200, 300) and/or a plurality of capacitors (500) with programmable resistance and programmable capacitance; adjusting trimmable resistors (200, 300) and/or trimmable capacitors (500) until the RC-dominated oscillator (100) produces the target frequency; storing configuration values of the trimmable resistors (200, 300) and/or the trimmable capacitors (500) in a lookup table. Procedure according to Claim 13 , characterized in that one of the trimmable resistors (200, 300) comprises: a first resistor (200, 300); a second resistor (200, 300) coupled in series with the first resistor (200, 300); and a pass gate operable to short the second resistor (200, 300), the method further comprising: controlling the pass gate by one or more signals associated with program code; translating the program code into code for trimming one of the trimmable resistors (200, 300) and/or one of the trimmable capacitors (500) using the lookup table based on the configuration values.

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