DE102015219266A1 - Method for testing a memory unit of a microcontroller - Google Patents

Abstract

The invention relates to a method for testing a memory unit (101) of a microcontroller (100), wherein the memory unit (101) has one or more memory banks (130, 131, 132), an additional memory bank (140) and a test unit (120) for the Performing tests on one of the one or more memory banks (130, 131, 132), wherein the memory unit (101) has at least two simultaneously usable communication channels (131a, 132a) for random access to one of the one or more memory banks (130, 131 , 132) and the auxiliary memory bank (140), wherein a memory content of a memory bank (131) of the one or more memory banks (130, 131, 132) to be tested is written into the additional memory bank (210), wherein passing an access request of the test unit (120) to the memory bank (131) to be tested, and wherein a test of the memory bank (131) to be tested is performed by the test unit (120), wherein if, during the Tes t, an access request to the memory contents of the memory bank (131) to be tested is registered, the access request is redirected to the additional memory bank (140) and the memory contents in the additional memory bank (140) are accessed, an access request to a Memory contents of one of the remaining memory banks (132) of the one or more memory banks (130, 131, 132) is registered, the access request is directed to the respective memory bank (132) and the memory contents of the respective memory bank (132) of the remaining memory banks (130, 131, 132) is accessed.

Description

The present invention relates to a method for testing a memory unit of a microcontroller, a memory controller for a memory unit of a microcontroller, a microcontroller and a computer program for carrying out the method.

State of the art

To ensure functional safety of storage devices in microcontrollers, such as RAM memories, these storage devices can be checked for errors. For this purpose, for example, a so-called "memory built-in self-test" (MBIST) can be performed. This may be, for example, hardware elements integrated in the microcontroller, which execute defined memory test sequences.

The WO 2013/102230 A1 describes, for example, the testing of a main memory of an integrated circuit. A built-in self-test module (BBISTM) selects a portion of main memory, writes that portion to temporary memory, and tests the portion of main memory. Also in the US 2014/0289575 A1 and the US 8 020 053 B2 In each case an MBIST method is described.

Disclosure of the invention

According to the invention, a method for testing a memory unit of a microcontroller, a memory controller for a memory unit of a microcontroller, a microcontroller and a computer program for carrying out the method with the features of the independent patent claims are proposed. Advantageous embodiments are the subject of the dependent claims and the following description.

The memory unit has one or more memory banks and an additional memory bank. In particular, the memory unit is designed as a RAM memory of the microcontroller, the memory banks and the additional memory bank each in particular as a RAM bank.

The memory unit has at least two simultaneously usable communication channels, each of which can be used for random access to one of the one or more memory banks and the additional memory bank. In particular, at least two different memory banks (arbitrary memory banks or additional memory bank) can thus be accessed simultaneously.

The memory unit further comprises a test unit for performing tests of the one or more memory banks and optionally the auxiliary memory bank. In particular, the tests are carried out as part of a so-called "memory built-in self-test" (MBIST). The term "memory-built-in self-test" should in particular be understood to mean hardware elements integrated in the microcontroller, which are set up to carry out defined memory test sequences in an automated manner. Different test sequences can be used. The test unit is designed in particular as a so-called "online memory built-in self-test controller" (MBIST controller).

In particular, the memory unit has a preferred embodiment of a memory controller according to the invention. The memory controller communicates in particular via the at least two simultaneously usable communication channels with the one or more memory banks and the additional memory bank in communication connection. Thus, in particular, at least two different memory banks of the one or more memory banks and the additional memory bank can be accessed at the same time. The memory controller is, in particular programmatically, configured to perform a preferred embodiment of the method according to the invention. For this purpose, the memory controller registers in particular access requests, i.a. also the test unit, on the one or more memory banks and the additional memory bank and forwards them accordingly.

In the course of the method, a memory content of a memory bank to be tested of the one or more memory banks is written to the additional memory bank. In particular, the test unit determines one of the one or more memory banks to be tested and transmits a corresponding access request to the memory controller. The memory controller and / or the test unit then cause the writing of the memory contents in the additional memory bank. The access request of the test unit is passed from the memory controller to the memory bank to be tested and a test of the memory bank to be tested is performed by the test unit.

The test of the memory unit is carried out in particular during the ongoing regular operation of the microcontroller. Due to the at least two communication channels, it is possible for external sources (eg processors in the microcontroller, other microcontrollers, bus masters) to access memory contents of the one or more memory banks independently of the test in the course of regular operation. An appropriate access request, in particular via a suitable Communication system (eg bus) is transmitted, registered by the memory controller.

If, during the test, an access request to the memory contents of the memory bank to be tested is registered by the memory controller, it forwards the access request to the additional memory bank. In this case, while the test is being performed, the memory contents in the auxiliary memory bank (and not in the memory bank under test) are accessed, advantageously simultaneously with and independent of the test being performed.

If, during the test, an access request to a memory content of one of the remaining memory banks (if present), which are not currently being tested, is registered by the memory controller, the access request is directed to the respective memory bank. During the test that has been carried out, in this case the memory contents of the respective memory bank are accessed via one of the at least two communication channels, advantageously simultaneously with and independently of the test carried out, which uses another of the at least two communication channels.

By outsourcing the memory contents of the memory bank to be tested in the additional memory bank in particular no access conflicts between external sources and the test unit occur. Accesses from external sources to the memory contents of the memory bank to be tested are, in particular, redirected without exception to the additional memory bank. The test accesses to the memory bank to be tested generated by the test unit are passed to the memory bank to be tested.

The at least two communication channels which can be used simultaneously and at random make it possible to carry out tests of individual memory banks during operation of the microcontroller, and yet nevertheless to access all memory contents of the memory unit simultaneously and without a time delay. In particular, it is made possible to carry out the test of the memory bank to be tested, and advantageously to simultaneously access the paged memory contents of this tested memory bank and / or the memory contents of the remaining untested memory banks. The test performed does not affect the regular operation of the microcontroller.

In particular, it is not necessary to access requests of the test unit to the memory bank to be tested, which are registered in the course of the test performed, and access requests from external sources to the memory bank to be tested or the remaining memory banks, which are carried out in the course of the regular operation of the microcontroller prioritize and process staggered. In particular, it is ensured that there is no temporal influence and no delay of the other necessary for regular operation memory accesses from external sources. It can be ensured that both the test and accesses to the memory contents of the individual memory banks are each performed with a deterministic (i.e., previously known) duration.

The test unit can be implemented together with the memory controller for performing the method in the memory unit or it is also conceivable to upgrade conventional test units or conventional memory controllers. In particular, memory controller and test unit together form a test module for performing the method. Tests can be performed by this test module independently and without the involvement of processors of the microcontroller. For example, the test module may be configured to boot from a processor or other external source and then perform the appropriate tests autonomously without further processor / external source intervention.

By performing the test by a test unit implemented in the memory unit and not by a software executed, for example, in the processor of the microcontroller, the computing capacity of the microcontroller can be used for regular operation and does not have to be used for the memory tests.

The storage unit test can be performed in an energy-efficient, low-effort manner, and memory test throughput can be increased. The method is in particular fully multicore-capable and in particular allows the simple use of virtualization solutions. In particular, the method is intrinsically safe, i. Malfunctions caused by the test unit or the test module are detected automatically. Furthermore, in particular memory error images can be detected, which can not be recognized, for example by means of software-based memory tests, or only to a limited extent (for example, Address Decoder Activation, Deactivation Delay Fault).

In particular, the method ensures that the memory content of the memory bank to be tested is preserved and is available for access both during and after the test. Preferably, further memory banks are tested after the test carried out, in particular all the memory banks in succession. The additional memory bank can in particular in the course of the regular operation if it is not used for caching during a test run.

According to a first preferred embodiment, after the test has been performed, the memory contents from the additional memory bank are copied back into the tested memory bank. The additional memory bank is preferably used as a permanent shadow memory bank and used as a buffer for the memory contents of each memory bank to be tested. Advantageously, after the test has been performed and the memory contents have been copied back from the additional memory bank to the tested memory bank, a memory content of a memory bank to be tested next is copied into the additional memory bank. After the test of this memory bank to be tested next has been performed, the corresponding memory content is preferably copied back into the tested memory bank. This process is repeated in particular for all memory banks. This embodiment enables a particularly simple implementation since the memory controller can always forward access requests to the currently tested memory bank, in particular always to the additional memory bank.

According to a second preferred embodiment, the memory contents remain in the additional memory bank after the test has been carried out and are not copied back into the tested memory bank. The role of a shadow memory bank is preferably assigned to other memory banks for subsequent tests. After the test has been carried out, the additional memory bank is used as a regular memory bank for the regular operation of the microcontroller. Preferably, the last tested memory bank is used as a shadow memory bank for further tests to be carried out. A memory content of a memory bank to be tested next is advantageously copied into the previously tested memory bank and a test of the memory bank to be tested next is performed. If, during the test of the memory bank to be tested next, an access request to its memory contents occurs, this access request is diverted to the previously tested memory bank and the memory contents in this previously tested memory bank are accessed. This design allows tests to be carried out, in particular with high flexibility and higher throughput, since there is no duplication.

Advantageously, the individual memory banks of the one or more memory banks and the additional memory bank have the same or substantially the same memory capacity. In particular, the memory banks and the additional memory bank are in each case the same or the same design. With different storage capacities of the individual memory banks, the storage capacity of the additional memory bank is in particular at least as large as the largest of the memory banks. Thus, it is ensured, in particular, that the memory contents of each of the memory banks can each be stored completely in the additional memory bank and that the entire memory content of the tested memory bank can be accessed even when one of the memory banks is tested.

Due to the configuration of the additional memory bank of this type, the memory controller can be constructed in a simple manner, since with a redirection of an access request to the additional memory bank, only that portion of the memory address is adapted by the memory controller which identifies the corresponding memory bank. The portion which identifies the memory contents within the memory bank can, in particular, remain unchanged.

Advantageously, in the course of the test carried out on the memory bank to be tested, an error detection of the test unit is carried out. If, for example, memory test sequences are carried out in the course of the test which contain write accesses, there is a risk that in the event of a fault of the test unit user data will be falsified. Due to the error detection, the test unit can be secured and errors in the test unit can be detected and remedied early. In particular, the error detection is performed by means of checksums and / or by means of an "Error Correcting Code" (ECC, error correction method).

For this purpose, the test unit may in particular comprise checksum registers, e.g. Multiple Input Signature Register (MISR). Furthermore, the test unit has in particular further registers, e.g. Control register, address register, data register in which particular command sequence and / or test data for the memory test are stored.

Before the test of the memory bank is performed, a reference signature can be calculated. In particular, individual commands and addresses as well as the data to be written or the data expected for a read access are fed into the respective register. In the case of a save command, the address to be saved is additionally fed into one of the checksum registers. During the execution of the test, memory accesses are processed by the test unit in sequence and additionally the instructions and addresses as well as the written or the read data are fed into the checksum registers. In the case of a save command, in addition, the data read from the memory is added to the checksum registers fed. When executing a final restore command, the contents of the checksum registers are each compared before recovering the data. A deviation of special checksums in particular indicates a fault of the test unit or in the tested memory bank. Afterwards, the checksum registers are reset in particular.

In particular, if the memory contents from the additional memory bank are written back into the tested memory bank, a new checksum comparison can be carried out. In particular, the address and the restored data are fed into the checksum registers for each access. After all data has been restored, in particular, a new checksum comparison of the checksum registers takes place. A deviation of the respective checksums indicates an error in the test unit or in the restored memory contents data.

If the specific memory test sequence of the test performed, the address sequence and the test data used are known in advance, the reference checksums can already be calculated offline. In this case, the calculation process of the reference checksums before the actual memory test can be omitted. In this case, the contents of the checksum registers are compared with the off-line checksums before the Restore command is executed. Alternatively, the detection of errors in the test unit itself can be done by using the hardware lockstep principle.

The method is suitable for microcontrollers in a large number of different areas, in particular for microcontrollers, which are implemented in control units for controlling technical installations, such as, for example, machine tools, printing presses, nuclear power plants, railways, aircraft or, preferably, motor vehicles. In motor vehicles, the method is particularly suitable for control units for engine control and / or hybrid control, and for controlling airbag, ABS, ESP, steering control devices, etc.

Also, the implementation of the method in the form of a computer program is advantageous because this causes very low costs, especially if an executive controller is still used for other tasks and therefore already exists.

Further advantages and embodiments of the invention will become apparent from the description and the accompanying drawings.

The invention is illustrated schematically by means of embodiments in the drawing and will be described below with reference to the drawing.

Brief description of the drawings

1 schematically shows a preferred embodiment of a microcontroller according to the invention, which is adapted to perform a preferred embodiment of a method according to the invention.

2 schematically shows a preferred embodiment of a method according to the invention as a block diagram.

3 schematically shows a part of a preferred embodiment of a microcontroller according to the invention, which is adapted to carry out a preferred embodiment of a method according to the invention.

4 schematically shows a part of a preferred embodiment of a microcontroller according to the invention, which is adapted to carry out a preferred embodiment of a method according to the invention.

Embodiment (s) of the invention

In 1 a preferred embodiment of a microcontroller according to the invention is shown schematically and with 100 designated. The microcontroller 100 may preferably be implemented in a control unit of a motor vehicle, for example in an engine control unit. The microcontroller 100 has a storage unit 101 in the form of a RAM memory and a processor unit 102 , For example, a multi-core processor.

The microcontroller 100 includes a communication system 103 eg in the form of an on-chip bus system or a crossbar. The processor unit is for example via an interface 102b to the communication system 103 tethered.

The storage unit 101 has one or more memory banks 130 in the form of RAM banks. In this example, the memory unit has two memory banks or RAM banks 131 and 132 on. It is understood that the storage unit 101 may be a convenient number (may be only one) of memory banks. Furthermore, an additional memory bank 140 or additional RAM bank provided. The RAM banks 130 and the additional RAM bank 140 are identical in construction in this example and each have the same storage capacity. The individual RAM banks 131 and 132 however, they can be different in size. In this case, the additional RAM bank 140 suitably at least as large as the largest of the RAM banks 131 and 132 ,

A memory controller 110 (so-called "RAM Bank Decoder") registers access requests to memory contents in the RAM banks 130 and 140 and forwards them to the respective RAM banks. The memory controller is in each case via separate communication channels 131 . 132a . 140a with every single RAM bank 131 . 132 . 140 in communication connection, whereby of the communication channels 131 . 132a . 140a at least any two can be used simultaneously. Thus, at a time, at least two different RAM banks can be accessed at random simultaneously.

A bus interface 150 is to the communication system 103 connected (see reference numeral 150b ). Access requests made by external sources (eg processor unit 102 , DMA controller, ...) via the communication system 103 are transmitted by the bus interface 150 received and over a communication channel 150a to the memory controller 110 transmitted.

A test unit 120 in the form of a so-called "online memory built-in self-test controller" is for performing tests of the RAM banks 130 respectively. 140 intended. The tests are carried out as part of a so-called "Memory Built In Self Test" (MBIST). The test unit 120 is via an interface or a communication channel 120a with the memory controller 110 in communication connection. The test unit 120 can be implemented in different forms depending on the required flexibility with regard to the memory test sequences to be performed, for example as a sequencer, state machine, CPU, etc.

If a fault in one of the RAM banks is detected during a test, a corresponding message can be sent via a channel 122a to a fault management 122 (so-called "Error Management Unit"). The error management 122 For example, as software in the processor unit 102 be run or as a separate hardware unit in the microcontroller 100 be integrated.

Furthermore, there are configuration registers 121 (Online MBIST register) provided, which via an interface or a communication channel 121 with the test unit 120 is in communication connection. In particular, the control of the test unit takes place 120 (eg selection of memory test sequence, configuration of the address range to be tested, etc.) via the configuration registers 121 ,

The configuration registers 121 are still via an interface 121b to the communication system 103 tethered. Thus, the configuration registers 121 over the communication system 103 Receive configuration data according to which the tests of the RAM banks are to be performed. This configuration data can be accessed via the interface 121 to the test unit 120 be transmitted. Furthermore, the test unit via the interface 121 Status messages regarding the tests performed on the configuration registers 121 transmit these status messages via the communication system 103 provides.

To perform the tests of the RAM banks according to the received configuration data, the test unit transmits 120 over the interface 120a corresponding test access requests to the memory controller 110 ,

To test individual RAM banks 130 respectively. 140 and at the same time to all memory contents of the memory unit 101 to be able to access is the microcontroller 100 arranged to perform a preferred embodiment of a method according to the invention, which in 2 is shown schematically as a block diagram.

In 3 is part of the microcontroller 100 out 1 shown in more detail schematically. The 2 and 3 are explained together below.

In one step 200 becomes the test unit 120 activated. For example, an external source may be for this purpose via the communication system 103 Configuration data to the configuration registers 121 to transfer.

In one step 201 is first from the test unit 120 a test of the auxiliary RAM bank 140 carried out. For this purpose, the test unit transmits 120 a corresponding test access request to the memory controller 110 which assigns these accesses to the address of the additional RAM bank 140 directs and whereupon the test unit 120 Test sequences in the course of the "Memory Built-In Self Test" (MBIST) performs.

In step 202 will check if the additional RAM bank 140 has an error. If so, the procedure in step 203 aborted and a corresponding message is sent to the error management 122 transmitted. If the additional RAM bank 140 has no error, is in accordance with step 204 from the test unit, a RAM bank of the RAM banks to be tested first 130 determines, for example, the RAM bank 131 ,

In step 210 is through the memory controller 110 carried out an evacuation or Umkopiervorgang, in the course of which the memory contents of the RAM bank 131 in the additional RAM bank 140 is written.

In particular, this swapping out of the memory contents occurs continuously with ascending addresses within the RAM bank 131 , In step 211 becomes an Evacuation Pointer to the smallest address within the RAM bank 131 set. For this purpose, in the memory controller 110 a corresponding evacuation pointer unit 310 (so-called "Evacuation Pointer Management Unit"). The evacuation pointer particularly identifies the progress of the paging of the memory contents or the corresponding internal address of the paging progress.

A date (eg a word) at the corresponding address will be in step 212 read in and in step 213 to a corresponding internal address of the additional RAM bank 140 written. In step 214 is from the memory controller 110 checks whether during this Umkopiervorgags the corresponding date (in particular between reading the data according to step 212 and before reconfiguring the evacuation pointer according to step 216 ) an access request, for example from an external source, is made on this date. If this is the case, the steps become 212 and 213 performed again and the date is again in the additional RAM bank 140 copied (so-called "re-evacuation").

For this purpose, a corresponding observation unit can be provided in the memory controller 320 (so-called Re-Evacuation Requirement Detection Unit, 3 ) be provided. In particular, it is checked for this purpose whether a date at the original address is overwritten by an external source. If this is the case, the observation unit will 320 a corresponding signal ("Re-Evacuation Required Signal") is set and sent to the test unit 120 transmitted, whereupon the Umkopiervorgang is repeated.

Alternatively, the steps 212 . 213 and 215 Atomic, ie without interruption by external access, done. In this case, no repetition ("re-evacuation") is necessary.

After the date succeeds in the additional RAM bank 140 has been copied and no external access has been made to this date during the copy process, in step 215 from the memory controller 110 checks whether an access request for example from an external source to the memory contents of the RAM bank 131 he follows. For this purpose, in step 214 the addressed by the external source in the course of the access request address in particular compared to the evacuation pointer, for example, from an addressing unit 330 ("Bank Address Remapping Unit", 3 ) of the memory controller 110 ,

If the addressed address is smaller than the evacuation pointer, the corresponding memory content is already in the additional RAM bank 140 has been written and the access request is to the add-on RAM bank 140 passed on. Otherwise, the memory contents have not yet been copied and the access is made to the memory contents within the RAM bank 131 ,

The evacuation pointer will then be in step 216 to the next higher address within the RAM bank 131 elevated. In step 217 It checks if all the words and thus the complete memory contents of the RAM bank 131 in the additional RAM bank 140 were written. If not, the steps become 212 to 216 repeated for the next word.

Once the full memory contents of the RAM bank 131 in the additional RAM bank 140 is evacuated, is in step 220 the test of the RAM bank 131 carried out. The test unit 120 sends appropriate test access requests to the memory controller 110 , in particular to an authorization unit 340 (so-called "Access Arbitration Unit", 3 ). A task of the authorization unit 340 consists in particular of detecting access collisions (ie concurrent access attempts) on the same RAM bank and serializing them. This happens during the evacuation as well as during the test phase. Test access requests are made by the authorization unit 340 in particular to a switching unit 350 (so-called "routing unit", 3 ) and from there to the RAM bank to be tested 131 passed and the test sequences are in the RAM bank 131 carried out.

In step 230 Checks whether requests for access to the memory contents of the RAM banks during the test 130 respectively. The authorization unit 340 receives corresponding access requests and checks them. If the access requests are allowed, they will be sent to the exchange unit 350 transmitted.

In step 231 At the same time as the test being performed, the access requests are forwarded to the corresponding RAM bank and the corresponding memory contents are accessed. When doing so, the memory contents of the currently tested RAM bank 131 is to be accessed, this access is to the additional RAM bank 140 forwarded. When a memory content of a currently untested RAM bank is to be accessed, for example, the RAM bank 132 , will access this RAM bank 132 directed.

When the test is finished, it is checked if there is an error in the tested RAM bank 131 is present. If so, the procedure in step 203 aborted and a corresponding message is sent to the error management 122 transmitted.

The units 310 to 350 of the storage controller 110 are preferably designed as separate digital hardware units and work in particular simultaneously. Thus, the steps 211 to 217 in particular at the same time and the corresponding tasks can be done in parallel.

The steps can also be analogous 220 and 230 be carried out in particular simultaneously. During step 220 is performed is checked in particular for each access (test access and external access), whether this can be done immediately or not. step 220 and step 230 can be done in parallel.

For example, for each individual external access by the addressing unit 330 If necessary, the bank address can be adjusted, regardless of whether by the test unit 120 currently evacuation operations or test accesses are performed. The same applies to the authorization unit 340 ,

If the RAM bank 131 has no error, according to a first preferred embodiment in step 251 the memory contents from the additional RAM bank 140 back to the tested RAM bank 131 be written, analogous to step 210 , In step 260 Checks whether all RAM banks have been checked. If this is not the case, the step will be 204 to 251 performed again and the memory contents of the next RAM bank, such as the RAM bank 132 , is tested, indicated by reference numerals 281 , For this purpose, the memory contents of the RAM bank 132 in step 210 also in the additional RAM bank 140 written.

According to an alternative preferred embodiment, in step 252 the memory contents from the additional RAM bank 140 not back in the tested RAM bank 131 written. When in step 260 not all RAM banks have been tested yet, the steps become 204 to 252 carried out again. In this case, the memory contents of the next RAM bank (for example, RAM bank 132 ) in step 210 preferably in the previously tested RAM bank (for example RAM bank 131 ), indicated by reference numerals 282 , If according to step 230 an access request to this next RAM bank 132 is registered, this access request is in step 231 to the previously tested RAM bank 131 is redirected and it is accessed on the memory contents in this.

The process is carried out until in step 260 it is found that all RAM banks 130 were tested and no errors of RAM banks 130 is present. In this case, the test unit will be in step 270 disabled.

Alternatively, the test unit in step 270 again with the testing of all RAM banks 130 and the additional RAM bank 140 kick off. For this purpose, follow all steps beginning with step 201 repeated again, indicated by reference numerals 271 to memory errors during the operation of the microcontroller 100 occur as quickly as possible.

If from the test unit 120 Memory test sequences are used that contain write access, there is a risk that in case of failure of the test unit 120 User data are corrupted. The operation of the test unit can therefore be secured with error detection mechanisms. In 4 is such a test unit 120 shown schematically.

In this embodiment, the test unit comprises 120 a defined number of Control & Address registers 410 and data registers 420 which comprise the command sequence of a memory test or the test data used thereby. In particular, such an instruction set comprises at least the commands "Save <address>", "Write <address><data>","Read<address><data>" and "Restore".

The command "Save <address>" reads in the current contents of a memory cell with the address "<address>" and in the additional RAM bank 140 saved.

By means of the command "Write <address> <data>", the data "<data>" contained in the corresponding data register is written to the address "<address>" in the RAM bank to be tested.

The command "Read <address> <data>" reads the current content of the address "<address>" and compares it with the data "<data>" contained in the corresponding data register. In particular, these data "<data>" of the data register represent an expected value for the comparison.

The test run is completed with the "Restore" command. All data previously evacuated using "save" commands is copied back to the original addresses.

Next to these registers 410 and 420 includes the test unit 120 preferably still three pairs of checksum registers 430 , These can eg be implemented as a Multiple Input Signature Register (MISR).

For example, a first pair includes the checksum registers "Address (Ref)". 431 and "Data (Ref)" 432 , These checksum registers 431 and 432 are used in particular to calculate a reference signature before the actual memory test. For this purpose, the individual commands including the addresses as well as the data to be written or the data expected for a read access are fed into the respective register. In the case of a "Save" command, the address to be saved is additionally included in the checksum register "Address (Rest)" 435 fed.

During the execution of the memory test, the memory accesses are processed one after the other and, in addition, the commands including the addresses as well as the written or the read data are written to the check sum registers "Address (Exe)". 433 or "Data (Exe)" 434 fed. In the case of a "Save" command, the data read from the memory are also written to the "Data (Save)" checksum register. 436 fed.

When executing the final "Restore" command, before restoring the data, the contents of the checksum registers "Address (Ref)" 431 and "Address (Exe)" 433 as well as "Data (Ref)" 431 and "Data (Exe)" 434 each compared with each other. A deviation of the respective checksums indicates an error in the test unit 120 or in the tested RAM bank.

Afterwards the checksum registers "Address (Exe)" 433 and "Data (Exe)" 434 reset and the restoration of data performed. For each access, the address and the restored data are written to the check sum register "Address (Exe)". 433 or "Data (Exe)" 434 fed.

After all data has been restored, a new checksum comparison between "Address (Exe)" 433 and "Address (Remainder)" 435 and "Data (Exe)" 434 and "Data (Save)" 436 , A deviation of the respective checksums indicates an error in the test unit 120 or in the recovered data.

If the memory test sequence, the address sequence and the test data used are already known in advance, the reference checksums can already be calculated offline. In this case, the calculation process of the reference checksums before the actual memory test can be omitted. The contents of the checksum registers "Address (Exe)" 343 and "Data (Exe)" 434 In this case, it will be compared to the off-line checksums before running the "Restore" command.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• WO 2013/102230 A1 [0003]
• US 2014/0289575 A1 [0003]
• US8020053 B2 [0003]

Claims (14)

Method for testing a storage unit ( 101 ) of a microcontroller ( 100 ), wherein the memory unit ( 101 ) one or more memory banks ( 130 . 131 . 132 ), an additional memory bank ( 140 ) and a test unit ( 120 ) for performing tests of one of the one or more memory banks ( 130 . 131 . 132 ), wherein the memory unit ( 101 ) via at least two simultaneously usable communication channels ( 131 . 132a ) for random access to one of the one or more memory banks ( 130 . 131 . 132 ) and the additional memory bank ( 140 ), wherein a memory content of a memory bank to be tested ( 131 ) of the one or more memory banks ( 130 . 131 . 132 ) in the additional memory bank ( 140 ) is written ( 210 ), - where an access request of the test unit ( 120 ) to the memory bank to be tested ( 131 ) and whereby a test of the memory bank to be tested ( 131 ) through the test unit ( 120 ) is carried out ( 220 ), Wherein - when, while the test is being performed, - an access request to the memory contents of the memory bank to be tested ( 131 ), the access request to the additional memory bank ( 140 ) is redirected ( 231 ) and the memory contents in the additional memory bank ( 140 ), an access request to a memory content of one of the remaining memory banks ( 132 ) of the one or more memory banks ( 130 . 131 . 132 ), the access request to the respective memory bank ( 132 ) ( 231 ) and the memory contents of the respective memory bank ( 132 ) of the remaining memory banks ( 130 . 131 . 132 ) is accessed. Method according to claim 1, wherein the test of the memory bank to be tested ( 131 ) is carried out ( 220 ) and at the same time to the memory contents in the additional memory bank ( 140 ) is accessed ( 231 ) and / or wherein the test of the memory bank to be tested ( 131 ) is carried out ( 220 ) and at the same time on the memory contents of the respective remaining memory bank ( 132 ) of the one or more memory banks ( 130 . 131 . 132 ) is accessed ( 231 ). The method of claim 1 or 2, wherein after the test has been performed, the memory contents from the additional memory bank ( 140 ) back into the tested memory bank ( 131 ) is copied ( 151 ). Method according to claim 3, wherein, after the memory contents have been read from the additional memory bank ( 140 ) back into the tested memory bank ( 131 ), a memory content of a memory bank to be tested next ( 132 ) of the one or more memory banks ( 130 . 131 . 132 ) in the additional memory bank ( 140 ), the test of the next memory bank to be tested ( 132 ) and, after the test has been carried out, the corresponding memory content is returned to the tested memory bank ( 132 ) is copied. The method of claim 1 or 2, wherein after the test has been performed, the memory contents from the additional memory bank ( 140 ) not back to the tested memory bank ( 131 ) is copied ( 252 ). The method of claim 5, wherein after the test has been performed, a memory content of a memory bank to be next tested ( 132 ) of the one or more memory banks ( 130 . 131 . 132 ) into the previously tested memory bank ( 131 ) and a test of the memory bank to be tested next ( 132 ) is carried out. The method of claim 6, wherein, when testing the next memory bank to be tested ( 132 ), an access request to a memory content of this memory bank to be tested next ( 132 ), the access request to the previously tested memory bank ( 131 ) and the memory contents in the previously tested memory bank ( 131 ) is accessed. Method according to one of the preceding claims, wherein the individual memory banks of the one or more memory banks ( 130 . 131 . 132 ) and the additional memory bank ( 140 ) have the same or substantially the same storage capacity. Method according to one of the preceding claims, wherein in the course of the test carried out the memory bank to be tested ( 131 ) an error detection of the test unit ( 120 ) is performed, in particular by an error detection using checksums, by checksum register ( 430 ), by checksum comparison of checksum registers ( 430 ) and / or by calculating a reference signature. Memory controller ( 110 ) for a storage unit ( 101 ) of a microcontroller ( 100 ), which storage unit ( 101 ) one or more memory banks ( 130 . 131 . 132 ) and an additional memory bank ( 140 ), wherein the memory controller ( 110 ) via at least two simultaneously usable communication channels ( 131 . 132a ) for random access to one of the one or more memory banks ( 130 . 131 . 132 ) and the additional memory bank ( 140 ), and via a test unit ( 120 ) for performing tests of one of the one or more memory banks ( 130 . 131 . 132 ). Memory controller ( 110 ) according to claim 10, which is adapted to perform a method according to any one of claims 1 to 9. Microcontroller ( 100 ), comprising: A storage unit ( 101 ) with one or more memory banks ( 130 . 131 . 132 ) and an additional memory bank ( 140 ), - a test unit ( 120 ) for performing tests on one of the one or more memory banks ( 130 . 131 . 132 ), and - a memory controller ( 110 ) according to claim 10 or 11. Computer program that has a memory controller ( 110 ) to perform a method according to one of claims 1 to 9, when it is stored on the memory controller ( 110 ) is performed. Machine-readable storage medium with a computer program stored thereon according to claim 13.

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