DE102016117166A1 - SEMICONDUCTOR DEVICE AND METHOD FOR THE PRODUCTION THEREOF - Google Patents

Abstract

A semiconductor device includes a first field effect transistor (FET) including a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first lower metal layer and a first upper metal layer. The first bottom metal layer includes a first underlying metal layer in contact with the first gate dielectric layer and a first volume metal layer. A lower surface of the first upper metal layer is in contact with an upper surface of the first underlying metal layer and an upper surface of the first bulk metal layer.

Description

CROSS-REFERENCE TO THE RELATED APPLICATIONS

This application claims the benefit of US Provisional Patent Application 62 / 272,031, filed on Dec. 28, 2015, the entire disclosure of which is hereby incorporated by reference herein.

TECHNICAL AREA

The disclosure relates to a method for manufacturing a semiconductor device, and more particularly relates to a structure and a manufacturing method for a metal gate structure.

BACKGROUND

As the semiconductor industry has advanced into the field of nanometer technology process nodes in an effort to provide higher device density, higher performance, and lower cost, the challenges associated with manufacturing and design problems for developing three-dimensional designs, such as a finite state of the art, have increased. Field effect transistor (Fin-FET), and led to the use of a metal gate structure with a material of high k (high dielectric constant). The metal gate structure is often fabricated using gate replacement technologies.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with current industry practice, various structural elements are not drawn to scale and are used for illustrative purposes only. The dimensions of the various structural elements may be increased or decreased as needed for the sake of clarity of the meeting.

1A - 12 10 illustrates an exemplary sequential manufacturing process of a semiconductor device according to an embodiment of the present disclosure. 1B - 12 are cross-sectional views, the line X1-X1 of 1A correspond.

DETAILED DESCRIPTION

It should be understood that the following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are just examples that should not be construed as limiting. For example, the dimensions of elements are not limited to the disclosed range or values, but may depend on the process conditions and / or the desired characteristics of the device. In addition, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which further features between the first and second features may be formed so that the first and second features may not be in direct contact. Various features may be arbitrarily drawn at different scales for the sake of simplicity and clarity

Furthermore, spatially relative terms such as "below," "below," "lower," "above," "upper," and the like, may be used herein to simplify the description to describe the relationship of an element Structure element to describe one or more other elements or structural elements, as illustrated in the figures. The spatially relative terms are intended to include, in addition to the orientation shown in the figures, further orientations of the device during use or operation. The device may also be otherwise oriented (90 degrees rotated or otherwise oriented), and the spatially relative descriptors used herein may equally be interpreted accordingly. In addition, the term "made from" may mean either "comprises" or "consists of".

1A - 12 10 illustrates an exemplary sequential manufacturing process of a semiconductor device according to an embodiment of the present disclosure. 1B - 12 are cross-sectional views taken on line X1-X1 of FIG 1A correspond. It is understood that additional operations before, during and after by the 1A - 12 and that some of the operations described below may be replaced or omitted to obtain further embodiments of the method. The order of operations or processes may be interchangeable.

1A FIG. 12 is a plan view (plan view) of a structure of a semiconductor device after dummy gate structures have been formed over a substrate. FIG. In the 1A and 1B become dummy gate structure 40 . 41 and 42 formed over a channel layer, for example a part of a rib structure 20 , Each of the dummy gate structures 40 . 41 and 42 corresponds to an n-channel FET, a p-channel FET and an n-type long channel FET.

The rib structure 20 is over a substrate 10 formed and extends from an insulating layer 30 , For the purpose of explanation, the dummy gate structures will be described 40 . 41 and 42 over the same rib structure 20 but in some embodiments, the dummy gate structures 40 . 41 and 42 each formed over other rib structures. Although there are two rib structures 20 in 1A however, the number of rib structures per gate structure is not limited to two and may be one or three or more.

The substrate 10 For example, a p-type silicon substrate having a impurity concentration in a range of about 1 × 10 ¹⁵ cm ^-3 to about 1 × 10 ¹⁸ cm ^-3 . In other embodiments, the substrate is an n-type silicon substrate having a spurious atom concentration in a range of about 1 × 10 ¹⁵ cm ^-3 to about 1 × 10 ¹⁸ cm ^-3 . Alternatively, the substrate may comprise another elemental semiconductor, such as germanium; a compound semiconductor, including Group IV-IV compound semiconductors, such as SiC and SiGe, Group III-V compound semiconductors, such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. In one embodiment, the substrate is a silicon layer of an SOI (silicon on insulator) substrate.

The rib structures 20 can be formed by trench etching the substrate. After forming the rib structures 20 becomes the insulating layer 30 over the rib structures 20 educated. The insulating layer 30 contains one or more layers of insulating materials, such as silicon oxide, silicon oxynitride or silicon nitride, which are formed by LPCVD (Low Pressure Chemical Vapor Deposition), plasma CVD or flowable CVD. The insulating layer can be formed by one or more layers of spin-on-glass (SOG), SiO, SiON, SiOCN and / or fluorine-doped silicate glass (FSG).

After forming the insulating layer 30 over the rib structures 20 a planarization operation is performed to form part of the insulating layer 30 to remove. The planarization operation may include a chemical mechanical polishing (CMP) and / or an etch back process. Then the insulating layer 30 further removed (indented) that the upper regions of the rib structures 20 lie free.

Then the dummy gate structures become 40 . 41 and 42 over the exposed rib structures 20 educated. The dummy gate structure includes a dummy gate electrode layer 44 polysilicon and a dummy gate dielectric layer 43 , Sidewall spacers 48 which include one or more layers of insulating materials are also formed on the sidewalls of the dummy gate electrode layer. The sidewall spacers 48 contain one or more layers of insulating material, such as silicon nitride-based material including SiN, SiON, SiCN and SiOCN. The film thickness of the sidewall spacers 48 at the bottom of the sidewall spacers, in some ranges from about 3 nm to about 15 nm embodiments, and in another embodiment ranges from about 4 nm to about 8 nm.

The dummy gate structures further include a mask insulating layer 46 , which is used to pattern a polysilicon layer to the dummy gate electrode layers. The thickness of the mask insulating layer 46 in some embodiments ranges from about 10 nm to about 30 nm, and in other embodiments ranges from about 15 nm to about 20 nm.

As in 2 As shown, after the dummy gate structures have been formed, source / drain regions are formed 60 educated. In the present disclosure, a source and a drain are used interchangeably, and the term source / drain refers to either a source or a drain. In some embodiments, the rib structure becomes 20 which is not covered by the dummy gate structures, under the top of the insulating layer 30 indented. Then the source / drain regions become 60 formed over the indented rib structure using an epitaxial growth method. The source / drain regions 60 may include a strain material to apply a stress to the channel region.

Then, as in 3 shown, a first etch stop layer (ESL) 70 and a first inter-layer dielectrics (ILD) layer 75 formed over the dummy gate structures and the source / drain regions. The first ESL 70 contains one or more layers of insulating material, such as silicon nitride-based material, including SiN, SiCN and SiOCN. The thickness of the first ESL 70 is in a range of about 3 nm to about 10 nm in some embodiments. The first ILD layer 75 contains one or more layers insulating material such as silicon oxide-based material such as silicon dioxide (SiO ₂ ) and SiON.

After a planarization operation on the first ILD layer 75 and the ESL 70 The dummy gate structures are removed to gate spaces 81 . 82 and 83 to form, as in 4 shown. As in 4 shown, the gate sidewall spacers remain 48 in the gate rooms.

Then, as in 5 shown a gate dielectric layer 85 educated. The gate dielectric layer 85 contains one or more layers of dielectric material, such as a high-k metal oxide. Examples of the metal oxides used for high-k dielectrics include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, Ia, Ce, Pr, Nd, Sm, Eu , Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and / or mixtures thereof. In some embodiments, prior to forming the gate dielectric layer 85 an interface layer (not shown) of, for example, silicon oxide is formed over the fin structure (channel region).

Furthermore, a first Workfunction Adjustment (WFA) layer is created 90 for a p-channel FET in the gate space 82 educated. A cover layer of a suitable conductive material is deposited over the gate spaces and the first ILD layer 75 and a patterning operation including lithography and etching is performed to form the first WFA layer 90 for a p-channel FET in the gate space 82 (and the surrounding area). The first WFA layer 90 contains one or more layers of conductive material. Examples of the first WFA layer 90 For a p-channel FET, Ti, TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC and Co. are included. In one embodiment, Ti is used. The thickness of the first WFA layer 90 is in a range of about 3 nm to about 10 nm in some embodiments. The first WFA layer 90 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) including sputtering, atomic layer deposition (ALD) or other suitable methods. As in 5 shown, becomes the first WFA layer 90 conformal in the gate space 82 educated.

Then a second WFA layer 95 for n-channel FETs in the gate spaces 81 and 83 educated. A cover layer of a suitable conductive material is deposited over the gate spaces and the first WFA layer 90 and a patterning operation including lithography and etching is performed to form the second WFA 95 for n-channel FETs in the gate spaces 81 and 83 (and the surrounding area). The second WFA layer 95 contains one or more layers of conductive material. Examples of the second WFA layer 95 for an n-channel FET include TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC. In one embodiment, TiN is used. The thickness of the second WFA layer 95 is in a range of about 3 nm to about 10 nm in some embodiments. The second WFA layer 95 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) including sputtering, atomic layer deposition (ALD) or other suitable methods. As in 5 shown, becomes the second WFA layer 95 conformal in the gate spaces 81 and 83 educated. It should be noted that the order of forming the first WFA layer 90 and the second WFA layer 95 can be changed. The second WFA layer 95 is made of a different material than the first WFA layer 90 ,

Then, as in 6 shown a first metal material 101 for a first metal layer 100 over the structure of 5 educated. The first metal material includes one or more layers of metal material, such as Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlC, TiAlN, TaN, NiSi, CoSi, or other conductive materials. In one embodiment, TiN is used. The first metal material is formed by CVD, PVD, ALD, electroplating or other suitable methods. The first metal layer 100 is made of a different material than at least one of the first WFA layer and the second WFA layer.

Then, as in 7 shown performing a planarization operation to the upper portion of the deposited first metal material 101 to remove. After the planarization operation, the first metal layer becomes 100 formed in each of the gate spaces. The planarization operation may include a chemical mechanical polishing (CMP) and / or an etch back process.

After each of the gate spaces with the first metal layer 100 filled in, the first metal layers become 100 indented (etched back) to gate indentations 87 . 88 and 89 to form, as in 8th shown. The upper sections of the first metal layers 100 are etched by dry etching and / or wet etching. The amount (depth) D1 of the indented portion, in some embodiments, ranges from about 20 nm to about 50 nm, and the height H1 of the remaining first metal layer from the top of the fin structure 20 in some embodiments ranges from about 30 nm to about 60 nm.

During the indentation etch, the first WFA layer becomes 90 and the second WFA layer 95 also etched.

Then, as in 9 shown a second metal material 111 for a second metal layer 110 over the structure of 8th educated. The second metal material includes one or more layers of metal material such as Al, Cu, Co, W, Ti, Ta, TiN, TiAl, TiAlC, TiAlN, TaN, NiSi, CoSi, or other conductive materials. In one embodiment, W or Co is used. The second metal material is formed by CVD, PVD, ALD, electroplating or other suitable methods. The second metal material 111 is made of a different material than the first metal material (and the first and second WFA layers) and has a higher resistance to a gas containing Cl and / or F than the first metal material 101 (and the first and second WFA layers).

Subsequently, a planarization operation is performed to form the upper portion of the deposited second metal material 111 to remove. After the planarization operation, the second metal layer becomes 110 formed in each of the gate spaces. The planarization operation may include a chemical mechanical polishing (CMP) and / or an etch back process.

The planarized second metal layers 110 are further indented into the gate spaces by a re-etching operation, as in FIG 10 shown. The amount (depth) D2 of the indented portion is in a range of about 10 nm to about 40 nm in some embodiments, and the thickness T1 of the remaining second metal layer 110 from the top of the first metal layer 100 is in a range of about 10 nm to about 30 nm in some embodiments 10 Shown is an underside of the second metal layer 110 in contact with an upper surface of the first metal layer 100 and an upper side of the first and / or the second WFA layer 90 . 95 ,

Then, as in 11 shown, insulating Kappschichten 120 over the second metal layers 110 educated. The insulating capping layer 120 contains one or more layers of insulating material, such as silicon nitride-based material, including SiN, SiCN and SiOCN.

To the insulating Kappschichten 120 to form a cover layer of an insulating material having a relatively large thickness over the structure of 10 and a planarization operation such as a CMP is performed.

Then a second ILD 130 over the structure of 11 and a patterning operation is performed to form via holes. The via holes are filled with one or more conductive materials to make via plugs 140 . 142 . 144 . 146 and 148 to form, as in 12 shown. Further, one or more metal wirings (not shown) are respectively formed over the via plugs. A dual damascene process can be used to form the via plugs and the metal wirings.

In the above-mentioned embodiment, the second metal layers are formed by a cap layer deposition, a planarization operation, and a back etching operation. In another embodiment, the second metal layers are formed directly over the first metal layers. For example, after the structure of 8th was formed, a selective deposition of W or Co used to form the second metal layer over the first metal layers only in the gate spaces to the in 10 To obtain structure shown. For example, Co and W can selectively on the metal layers by an ALD method 90 . 95 and 100 while Co or W are not grown on SiO ₂ , SiN or other dielectric materials.

It is understood that in 12 In the embodiment mentioned above, the fabrication operations for a Fin-FET are described. However, the above-mentioned manufacturing process may be applied to other types of FETs, such as planar-type FETs.

The various embodiments or examples described herein have several advantages over the prior art. For example, in the present disclosure, as in 12 shown the feedthrough plug 140 . 144 and 148 in contact with the second metal layers 110 , If through holes for the feedthrough plug 140 . 144 and 148 dry etching by means of a gas containing Cl and / or F is used. If the second metal layers 110 not having a higher resistance to Cl or F, the Ti or TiN layer exposed in the bottoms of the via holes would be damaged by the Cl or F component in the etching gas (e.g. Cause erosion). In contrast, in the present embodiment, damage to the Ti or TiN layers can be avoided since the second metal layers 110 that have higher resistance to Cl or F than Ti and TiN.

It will be appreciated that it is not necessarily that all advantages have been discussed herein, that no single benefit must be apparent to all embodiments, and that other embodiments may provide other benefits.

According to one aspect of the present disclosure, in a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A source / drain region is formed. A first insulating layer is formed over the dummy gate structure and the source / drain region. The dummy gate structure is removed to form a gate space. The gate space is filled with a first metal layer. The filled first metal layer is indented to form a gate indentation. A second metal layer is formed over the first metal layer in the gate indentation. A second insulating layer is formed over the second metal layer in the gate indentation.

According to another aspect of the present disclosure, in a method of manufacturing a semiconductor device, a first dummy gate structure and a second dummy gate structure are formed over a substrate. Source / drain regions are formed. A first insulating layer is formed over the first and second dummy gate structures and the source / drain regions. The first and second dummy gate structures are removed to form a first gate space and a second gate space. A first metal layer is formed in the first gate space, and a second metal layer is formed in the first and second gate spaces. After forming the first and second metal layers, the first and second gate spaces are filled with a third metal layer. The first, second, and third metal layers formed in the first gate space are indented to form a first gate indentation, and the first and third metal layers formed in the second gate space are indented, to form a second gate indentation. Fourth metal layers are formed in the first and second gate indentations to form a first gate electrode and a second gate electrode. Second insulating layers are formed over the fourth metal layers in the first and second gate indents.

According to another aspect of the present disclosure, a semiconductor device includes a first field effect transistor (FET) including a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first lower metal layer and a first upper metal layer. The first bottom metal layer includes a first underlying metal layer in contact with the first gate dielectric layer and a first volume metal layer. A lower surface of the first upper metal layer is in contact with an upper surface of the first underlying metal layer and an upper surface of the first bulk metal layer.

The above outlines features of various embodiments so that those skilled in the art can better understand the aspects of the present disclosure. It will be appreciated by those skilled in the art that the present disclosure may be readily utilized as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments presented herein. It should also be understood by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made to the present invention without departing from the spirit and scope of the present disclosure.

Claims (20)

A method of manufacturing a semiconductor device, the method comprising: Forming a dummy gate structure over a substrate; Forming a source / drain region; Forming a first insulating layer over the dummy gate structure and the source / drain region; Removing the dummy gate structures to form a gate space; Filling the gate space with a first metal layer; Indenting the filled first metal layer to form a gate indentation; Forming a second metal layer over the first metal layer in the gate indentation; and Forming a second insulating layer over the second metal layer in the gate indentation. The method of claim 1, wherein a material of the first metal layer is other than a material of the second metal layer. The method of claim 1 or 2, wherein the material of the first metal layer contains TiN. A method according to any one of the preceding claims, wherein the material of the second metal layer contains at least one of Co, W, Ti, Al and Cu. The method of claim 1, further comprising forming a third metal layer in the gate space prior to forming the first metal layer, wherein a bottom surface of the second metal layer is in contact with an upper surface of the first metal layer and an upper surface of the third metal layer. The method of claim 5, further comprising forming a gate dielectric layer in the gate space prior to forming the third metal layer. The method of claim 5 or 6, wherein a material of the third metal layer contains Ti. The method of any one of the preceding claims, wherein forming the second metal layer over the first metal layer includes: Forming a cap layer of a metal material for the second metal layer in the gate indentation and over the first insulating layer; and Removing upper portions of the metal material such that an upper surface of the second metal layer is below an upper surface of the first insulating layer. The method of any one of the preceding claims, wherein forming the second metal layer over the first metal layer includes: Forming a metal material for the second metal layer in the gate indentation such that the metal material partially fills the gate indentation and an upper surface of the second metal layer is below an upper surface of the first insulating layer. The method of any one of the preceding claims, further comprising forming a gate sidewall spacer on a sidewall of the dummy gate structure, wherein an upper surface of the second metal layer is below an upper surface of the gate sidewall spacer. A method of manufacturing a semiconductor device, the method comprising: Forming a first dummy gate structure and a second dummy gate structure over a substrate; Forming source / drain regions; Forming a first insulating layer over the first and second dummy gate structures and the source / drain regions; Removing the first and second dummy gate structures to form a first gate space and a second gate space; Forming a first metal layer in the first gate space; Forming a second metal layer in the first and second gate spaces; after forming the first and second metal layers, filling the first and second gate spaces with a third metal layer; Indenting the first, second and third metal layers formed in the first gate space to form a first gate indent, and indenting the first and third metal layers formed in the second gate space to form a second gate space. To make indentation; Forming fourth metal layers in the first and second gate indentations to form a first gate electrode and a second gate electrode; and Forming second insulating layers over the fourth metal layers in the first and second gate indentations. The method of claim 11, wherein: contains the first metal layer TiN, the second metal layer contains Ti, the third metal layer TiN contains, and the fourth metal layer contains at least one of Co, W, Ti, Al and Cu. The method of claim 12, wherein: in the first gate electrode, a bottom of the fourth metal layer is in contact with tops of the first, second and third metal layers, and in the second gate electrode, a lower surface of the fourth metal layer is in contact with upper surfaces of the first and third metal layers. The method of any one of claims 11 to 13, wherein forming fourth metal layers includes: Forming a cap layer of a metal material for the fourth metal layers in the first and second gate indents and over the first insulating layer; and Removing upper portions of the metal material such that upper surfaces of the fourth metal layers are below a top surface of the first insulating layer. The method of claim 11, wherein forming the fourth metal layers includes forming a metal material for the fourth metal layers in the first and second gate indentations such that the metal material partially fills the first second gate indentations. The method of claim 11, further comprising forming a gate sidewall spacer on a sidewall of the dummy gate structure, wherein an upper surface of the second metal layer is below an upper surface of the gate sidewall spacer. A semiconductor device, comprising: a first field effect transistor (FET) including a first gate dielectric layer and a first gate electrode, wherein: the first gate electrode includes a first lower metal layer and a first upper metal layer, the first lower metal layer includes a first a first underlying metal layer in contact with the first gate dielectric layer and a first volume metal layer, and a bottom surface of the first top metal layer is in contact with an upper surface of the first underlying metal layer and an upper surface of the first volume metal layer. A semiconductor device according to claim 17, wherein: contains the first underlying metal layer Ti, the first volume metal layer TiN contains, and the first upper metal layer contains at least one of Co, W, Ti, Al and Cu. The semiconductor device according to claim 17 or 18, further comprising: a second FET including a second gate dielectric layer and a second gate electrode, wherein: the second gate electrode includes a second lower metal layer and a second upper metal layer, the second bottom metal layers include a second underlying metal layer in contact with the second gate dielectric layer, a third underlying metal layer, and a second volume metal layer, and a bottom of the second top metal layer is in contact with an upper surface of the second underlying metal layer, an upper surface of the third underlying metal layer, and an upper surface of the second bulk metal layer. A semiconductor device according to claim 19, wherein: contains the second underlying metal layer TiN, contains the third underlying metal layer Ti, the second volume metal layer TiN contains, and the second upper metal layer contains at least one of Co, W, Ti, Al and Cu.

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