DE102017210165A1 - Multi-transistor arrangement, bridge rectifier and method for producing a multiple transistor arrangement - Google Patents

Abstract

The invention provides a multiple transistor arrangement, in particular a multiple transistor arrangement for a bridge rectifier. For this purpose, an arrangement of parallel electrodes is provided on a common semiconductor substrate, which enables efficient implementation of a plurality of transistors for an active bridge rectifier circuit.

Description

The present invention relates to a multiple-transistor arrangement, a bridge rectifier and a method for producing a multi-transistor arrangement

State of the art

Rectifier circuits are used in many electronic circuits. For example, rectifier circuits are an essential element in DC-DC converters or even in power factor adjustment circuits. In this case, the rectifier circuits may be formed, for example, as a bridge rectifier. In particular, the rectifier circuits can be designed as active rectifiers with synchronously clocked transistors.

For this purpose, it is also possible, for example, to use lateral power transistors, in particular lateral gallium-nitride-based power transistors. A typical design for such power transistors is, for example, a so-called High Electron Mobility Transistor (HEMT). For this purpose, a two-dimensional electron gas is generated by means of a layer stack of gallium nitride (GaN) and aluminum gallium nitride (AIGaN) or other suitable material combinations, which is formed by Ankontaktierungen and a gate terminal to a controllable transistor.

The publication EP 2 267 784 A2 discloses, for example, an AlGaN / GaN HEMT. The HEMT knows here a thin AlGaN layer. Additional layers are provided to minimize gate leakage and increase current carrying capacity.

Disclosure of the invention

The present invention discloses a multiple transistor arrangement with the features of patent claim 1, a bridge rectifier with the features of claim 8 and a method for producing a multiple transistor arrangement with the features of claim 10.

Accordingly, it is provided:

A multiple transistor arrangement having a semiconductor substrate; a plurality of drain-source electrodes and a plurality of control electrodes. The drain-source electrodes are each arranged parallel to one another on the semiconductor substrate. The plurality of control electrodes are each arranged between two adjacent drain-source electrodes.

Furthermore, it is provided:

A bridge rectifier with a multiple transistor arrangement according to the invention.

It is also provided:

Method for producing a multiple transistor arrangement. The method comprises the steps of providing a semiconductor substrate; arranging a plurality of drain-source electrodes on the semiconductor substrate such that the drain-source electrodes are arranged parallel to each other; and arranging a plurality of control electrodes such that a respective control electrode is arranged between two adjacent drain-source electrodes.

Advantages of the invention

The present invention is based on the finding that a structure of a rectifier, in particular a bridge rectifier with discrete transistors, requires a relatively large area requirement. Among other things, this is associated with relatively large parasitic capacitances and inductances.

It is therefore an idea of the present invention to take this knowledge into account and to provide a transistor arrangement for a rectifier, which requires a reduced area requirement. In addition, parasitic capacitances and inductances can be significantly minimized by the multiple transistor arrangement according to the invention.

In addition, by an optimized arrangement of a plurality of transistors on a common substrate no individual isolation between the individual transistors is required. As a result, the area utilization can be increased

According to one embodiment, the semiconductor substrate comprises a plurality of semiconductor layers. In this case, these multiple semiconductor layers form a heterostructure. Heterostructures or semiconductor heterostructures are monocrystalline layers of semiconductors of different composition. Such layer structures provide an important basis for the production of novel microelectronic components. A combination of materials for the production of semiconductor heterostructures is, for example, the system gallium arsenide (GaAs) / aluminum gallium arsenide (AlGaAs).

According to one embodiment, the semiconductor substrate comprises gallium nitride, aluminum gallium nitride and / or aluminum indium nitride. Furthermore It is also possible to use any other materials or material combinations which are suitable for the realization of corresponding transistors.

According to one embodiment, a plurality of drain-source electrodes are each assigned to a common external terminal, wherein all the drain-source electrodes, which are assigned to a common external terminal, are electrically connected to one another. Furthermore, a plurality of control electrodes can each be assigned to a common control connection, wherein all control electrodes which are assigned to a common control connection are electrically connected to one another. In this way, it is possible to realize transistor structures which correspond to a plurality of individual transistors connected in parallel.

According to one embodiment, each fourth of the drain-source electrodes arranged parallel to one another is assigned to a common external connection and in each case every fourth control electrode is assigned to a common control connection. In this way, a particularly efficient structure of a bridge rectifier with four transistors can be realized.

According to one embodiment, a dielectric layer is arranged between the semiconductor substrate and at least between a part of the control electrodes. As a result, the control properties of the respective transistor structures can be influenced. In particular, it is possible in this way to distinguish between transistors which are switched on in the non-activated state and transistors which are switched off in the non-activated state.

In one embodiment, the dielectric layer is disposed between the semiconductor substrate and each second control electrode. This corresponds to a structure of a bridge rectifier, in which respective opposite transistors have the same switching characteristics.

According to one embodiment, a field plate is arranged in each case on the drain-source electrodes and / or the control electrodes. As a result, a shielding of electrical fields and associated interference properties can be achieved.

According to one embodiment of the bridge rectifier, the bridge rectifier comprises a logic circuit. The logic circuit is designed to predetermine a predetermined switching behavior for driving the multiple transistor arrangement, the logic circuit being arranged on the semiconductor substrate of the multiple transistor arrangement. In this way, the corresponding drive logic can be implemented efficiently and space-saving on the substrate with the transistor arrangement.

The above embodiments and developments can, as far as appropriate, combine arbitrarily. Further refinements, further developments and implementations of the invention also include combinations of feature of the invention which have not been explicitly mentioned above or described below with regard to the exemplary embodiments. In particular, the person skilled in the art will also add individual aspects as improvements or additions to the respective basic form of the present invention.

list of figures

The present invention will be explained in more detail with reference to the exemplary embodiments indicated in the schematic figures of the drawings.

• 1: eine schematische Darstellung einer BrückengleichrichterSchaltung, wie Sie einer Ausführungsform der vorliegenden Erfindung zugrunde liegt;
• 2: eine schematische Darstellung eines Querschnitts durch eine Mehrfach-Transistor-Anordnung gemäß einer Ausführungsform;
• 3: eine schematische Darstellung einer Draufsicht auf eine Mehrfach-Transistor-Anordnung gemäß einer Ausführungsform;
• 4: eine schematische Darstellung einer Draufsicht auf eine Mehrfach-Transistor-Anordnung gemäß einer weiteren Ausführungsform; und
• 5: eine schematische Darstellung eines Ablaufdiagramms, wie es einem Verfahren zur Herstellung einer Mehrfach-Transistor, Anordnung gemäß einer Ausführungsform zugrunde liegt.

Showing:

• 1 a schematic representation of a bridge rectifier circuit, as it is based on an embodiment of the present invention;
• 2 FIG. 2 is a schematic representation of a cross section through a multiple transistor arrangement according to an embodiment; FIG.
• 3 FIG. 2 is a schematic representation of a top view of a multiple transistor arrangement according to an embodiment; FIG.
• 4 FIG. 2 is a schematic representation of a top view of a multiple transistor arrangement according to a further embodiment; FIG. and
• 5 3 is a schematic representation of a flowchart underlying a method of fabricating a multiple transistor array according to one embodiment.

Embodiments of the invention

In all figures, the same or functionally identical elements and devices - unless otherwise stated - provided with the same reference numerals.

1 shows a schematic representation of a bridge rectifier 1 , as it is based on an embodiment of the present invention. In this example, the bridge rectifier includes 1 four transistors T1 to T4 , In each case, a source terminal of a transistor T1 to T4 with a drain terminal of an adjacent transistor T1 to T4 connected. At a first junction K1 is the source terminal of the first transistor T1 to the drain terminal of the fourth transistor T4 connected. At a second node K2 is the source terminal of the second transistor T2 with the drain terminal of the first transistor T1 connected. At a third node K3 is the source terminal of the third transistor T3 to the drain terminal of the second transistor T2 connected. At a fourth node K4 is the source terminal of the fourth transistor T4 to the drain terminal of the third transistor T3 connected. The gate terminals of the transistors T1 to T4 are here with G1 to G4 designated.

For the conventional bridge rectifier, the individual transistors are T1 to T4 executed as a single, discrete components.

Such a rectifier arrangement can be realized on a common semiconductor substrate according to an embodiment of the present invention.

2 shows a schematic representation of a cross section through a multiple transistor arrangement 2 according to one embodiment. The multiple transistor arrangement 2 comprises at least one semiconductor substrate 20 , on which a plurality of mutually parallel drain-source electrodes 21 - 1 to 21 - 4 are arranged. Between two drain-source electrodes 21 - 1 to 21 - 4 is each a control electrode 22 - 1 to 22 - 4 arranged. In this way, two adjacent drain-source electrodes form in each case 21 - 1 to 21 - 4 and a control electrode interposed therebetween 22 - 1 to 22 - 4 a transistor. Such a transistor corresponds to a transistor T1 to T4 according to 1 , Each drain-source electrode corresponds to this 21 - 1 to 21 - 4 simultaneously a source terminal of a transistor T1 to T4 and a drain terminal of an adjacent transistor T1 to T4 , The control electrodes 22 - 1 to 22 - 4 correspond to the gate terminals G1 to G4 according to 1 ,

As in 2 can already be seen, it can be the arrangement of drain-source electrodes 21 - 1 to 21 - 4 and intermediate control electrodes 22 - 1 to 22 - 4 be continued periodically in the X direction.

In the semiconductor substrate 20 the multiple transistor arrangement 2 it may be any suitable semiconductor substrate. In particular, for example, a substrate is possible which comprises gallium nitride (GaN), aluminum gallium nitride (AlGaN) and / or aluminum indium nitride (AlInN). In particular, the semiconductor substrate 20 Also include a layer stack of several suitable semiconductor materials. The corresponding semiconductor substrate 20 For example, it can be deposited on a suitable support (not shown here). In particular, for example, a support of silicon (Si), silicon carbide (SiC), sapphire (Al ₂ O ₃ ) or gallium arsenide (GaAs) material combinations is possible.

For the drain-source electrodes 21 - 1 to 21 - 4 and the control electrodes 22 - 1 to 22 - 4 they may be electrodes made of a suitable material, in particular of a suitable semiconductor material. In particular, any suitable acquaintances or novel materials are possible here. For example, on a semiconductor substrate 20 be provided with gallium nitride electrode structures with aluminum indium nitride. To improve the contact between the drain-source electrodes 21 - 1 to 21 -4 and the semiconductor substrate 20 For example, additional intermediate layers of aluminum, titanium, nickel and / or gold may be used.

Between the semiconductor substrate 20 and the control electrodes 22 - 1 to 22 - 4 In addition, optionally a further dielectric layer 23 be provided. By such an additional dielectric layer 23 For example, the control behavior of a transistor of two adjacent drain-source electrodes 21 - 1 to 21 - 4 and an interposed control electrode second 22-1 to 22-4 are set. For example, can be set in this way, whether a corresponding transistor in the non-driven state is conductive (normally on) or non-conductive (normally off).

In particular, in this way, for example, a configuration can be set in which two are in 1 opposite transistors (eg T1 and T3 ) are conductive by default and the other two are in 1 opposite transistors (eg T2 and T4 ) are not conductive by default. In this case, for example, in each case between the semiconductor substrate 20 and every second control electrodes 22 - 1 to 22 - 4 a dielectric layer 23 be provided. In addition, any other configurations are possible.

For shielding the electric field can above the control electrodes 22 - 1 to 22 - 4 and / or above the drain-source electrodes 21 - 1 to 21 - 4 optionally a so-called field plate may be provided. In particular, critical field peaks at the edge of a conductive channel can be reduced in this way. The field plates can, for example, from the same material as the corresponding electrodes 21 - 1 to 21 - 4 respectively. 22 - 1 to 22 - 4 will be realized.

3 shows a schematic representation of a plan view of a multi-transistor arrangement 2 according to an embodiment of the present invention. As can be seen here, the drain-source electrodes extend 21 - 1 to 21 - 4 each parallel to each other, with the individual drain-source electrodes 21 - 1 to 21 - 4 are arranged spaced from each other. Between every two adjacent drain-source electrodes 21 - 1 to a 21-4 is in each case a control electrode 22 - 1 to 22 - 4 arranged. Also these control electrodes 22 - 1 to 22 - 4 are parallel to each other and parallel to the drain-source electrodes 21 - 1 to 21 - 4 , The arrangement of the parallel drain-source electrodes 21 - 1 to 21 - 4 and the control electrodes interposed therebetween 22 - 1 to 22 - 4 can be continued arbitrarily in the X direction.

A first drain-source electrode 21 - 1 forms with an adjacent second drain-source electrode 21 - 2 and the first control electrode disposed therebetween 22 - 1 a first transistor connected to the transistor T1 out 1 equivalent. A second drain-source electrode 21 - 2 forms with an adjacent third drain-source electrode 21 - 3 and the second control electrode disposed therebetween 22 - 2 a second transistor connected to the transistor T2 out 1 equivalent. A third drain-source electrode 21 - 3 forms with an adjacent fourth drain-source electrode 21 - 4 and the third control electrode disposed therebetween 22 - 2 a third transistor connected to the transistor T3 out 1 equivalent. A fourth drain-source electrode 21 - 4 forms with an adjacent first drain-source electrode 21 - 1 and the fourth control electrode interposed therebetween 22 - 4 a fourth transistor connected to the transistor T4 out 1 equivalent.

In a continuation of the electrode structure in the X direction, all equivalent electrodes can each be electrically connected to each other, as for example in the embodiment of FIG 4 is shown. For example, all first, second, third and fourth drain-source electrodes can be used 21 - 1 to 21 - 4 each electrically connected to each other. Accordingly, in each case all the first, second, third and fourth control electrodes 22 - 1 to 22 - 4 each electrically connected to each other. For example, this can be electrically conductive fasteners 24 - 1 to 24 - 4 such as 25 - 1 to 25 - 4 , For example, in the form of metallization, be provided over the electrodes, which electrically connect the respective electrodes each other.

The drain-source electrodes 21 - 1 to 21 - 4 as well as the control electrodes 22 - 1 to 22 - 4 can be led out via suitable electrical connections to suitable external connections. For this purpose, any suitable compounds, for example by means of bonds or by flip-chip technology, connect the electrodes to the external terminals. In particular, this can be the external connections with the connecting elements 24 - 1 to 24 - 4 such as 25 - 1 to 25 - 4 be contacted.

In addition, in the control terminals of the transistors thus formed, that is, the control electrodes 22 - 1 to 22 - 4 be controlled via a suitable logic circuit. In such a logic circuit, for example, logic may be implemented which controls the driving of the transistors on the multi-transistor arrangement 2 limited to predetermined switching states. In this way, unauthorized, especially dangerous switching states can be prevented. In this case, the logic circuit for controlling the control electrodes 22 - 1 to 22 - 4 also together with the multiple transistor arrangement 2 be implemented on a common substrate.

5 shows a schematic representation of a flowchart, as a method for producing a multi-transistor arrangement 2 according to one embodiment is based. In step S1 becomes a semiconductor substrate 20 provided. In step S2 be on the semiconductor substrate 20 several drain-source electrodes 21 - 1 to 21 - 4 arranged. In step S3 be on the semiconductor substrate 20 several control electrodes 22 - 1 to 22 - 4 arranged. The drain-source electrodes 21 - 1 to 21 - 4 run on the semiconductor substrate 20 each parallel to each other. The control electrodes 22 - 1 to 22 - 4 also run parallel to each other and parallel to the drain-source electrodes 21 - 1 to 21 - 4 , In particular, in each case between two adjacent drain-source electrodes 21 - 1 to 21 - 4 one control electrode each 22 - 1 to 22 - 4 arranged.

In summary, the present invention relates to a multi-transistor arrangement, in particular a multi-transistor arrangement for a bridge rectifier. For this purpose, an arrangement of parallel electrodes is provided on a common semiconductor substrate, which enables efficient implementation of a plurality of transistors for an active bridge rectifier circuit.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• EP 2267784 A2 [0004]

Claims (11)

Multiple transistor arrangement (2), with: a semiconductor substrate (20); a plurality of drain-source electrodes (21-1, 21-4) each disposed in parallel with each other on the semiconductor substrate (20); and a plurality of control electrodes (22-1..22-4), wherein in each case between two adjacent drain-source electrodes (21-1..21-4) a control electrode (22-1..22-4) is arranged. Multiple transistor arrangement (2) according to Claim 1 wherein the semiconductor substrate (20) comprises a plurality of semiconductor layers forming a heterostructure. Multiple transistor arrangement (2) according to Claim 1 or 2 wherein the semiconductor substrate (20) comprises gallium nitride, aluminum gallium nitride and / or aluminum indium nitride. Multiple transistor arrangement (2) according to one of Claims 1 to 3 , wherein a plurality of drain-source electrodes (21-1..21-4) are each assigned to a common external terminal and a plurality of control electrodes (22-1..22-4) are each assigned to a common control terminal, and wherein all the drain-source -Electrodes (21-1..21-4), which are assigned to a common external terminal are electrically connected to each other and all the control electrodes (22-1..22-4), which are assigned to a common control terminal are electrically connected .. Multiple transistor arrangement (2) according to Claim 4 wherein each fourth of the mutually parallel drain-source electrodes (21-1..21-4) is assigned to a common external terminal, and wherein each fourth control electrode (22-1..22-4) assigned to a common control terminal is. Multiple transistor arrangement (2) according to one of Claims 1 to 5 wherein between the semiconductor substrate (20) and at least one subgroup of the plurality of control electrodes (22-1..22-4), a dielectric layer (23) is arranged. Multiple transistor arrangement (2) according to Claim 6 wherein the dielectric layer (23) is disposed between the semiconductor substrate (20) and each second control electrode (22-1, 22-2). Multiple transistor arrangement (2) according to one of Claims 1 to 7 , wherein on the drain-source electrodes (21-1..21-4) and / or the control electrodes (22-1..22-4) in each case a field plate is arranged. Bridge rectifier with a multi-transistor arrangement (2) according to one of Claims 1 to 8th , Bridge rectifier after Claim 9 , comprising a logic circuit which is designed to predetermine a predetermined switching behavior for driving the multi-transistor arrangement (2), the logic circuit being arranged on the semiconductor substrate of the multiple transistor arrangement (2). Method for producing a multiple transistor arrangement with the steps: Providing (S1) a semiconductor substrate (20); Arranging (S2) a plurality of drain-source electrodes (21-1, 21-4) on the semiconductor substrate (20) such that the drain-source electrodes (21-1, 21-4) are each arranged parallel to each other ; and Arranging (S3) a plurality of control electrodes (22-1..22-4), such that in each case a control electrode (22-1..22-4) between two adjacent drain-source electrodes (21-1..21-4) is arranged.

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