DE102020200421B4 - Integrated circuit arrangement and method for producing an integrated circuit arrangement - Google Patents

Abstract

The present invention relates to an integrated circuit arrangement and to a method for producing an integrated circuit arrangement. The integrated circuit arrangement (100) comprises at least one active electronic component (102), at least one passive electrical element (120), an electrically conductive housing (130) in which the active electronic component (102) is at least partially accommodated, the passive electrical element (120) has at least a first electrode (114) and a second electrode (132), wherein the first electrode (114) is connected inside the housing (130) to the active electronic component (102), and wherein the second Electrode (132) is formed by at least part of the housing (130).

Description

The present invention relates to an integrated circuit arrangement and to a method for producing an integrated circuit arrangement.

Modern application-specific integrated circuits (ASICs) are mostly implemented in CMOS (complementary metal-oxide-semiconductor) technology, which enables a high circuit and functional density. These commercially available processes are continuously being optimized towards smaller gate sizes, which in turn lead to ever smaller semiconductor chips with the same functionality. However, this miniaturization reaches its limits when the capacities are required, which can hardly be solved with the existing processes or materials and which often take up a disproportionate part of the chip area. However, this restriction does not conform to the striving for a decreasing CMOS “die” (isolated monolithic silicon cube). High capacities can therefore only be achieved with external components or new technologies.

Very small ASICs (with areas of less than 200x200 μm ² ) are very advantageous, especially in biomedical engineering for implantable systems, since small volumes of implanted components lead to higher biocompatibility and compatibility, as described in the article, for example Y. Pyungwoo et al, "Toward a distributed free-floating wireless implantable neural recording system," (eng), pp. 4495-4498, 2016 , is known.

• J. Jeong et al., „Conformal Hermetic Sealing of Wireless Microelectronic Implantable Chiplets by Multilayered Atomic Layer Deposition (ALD),“ Adv. Fund Mater., vol. 2, p. 1806440, 2018 ;
• J. M. Maloney, S. A. Lipka, and S. P. Baldwin, „In Vivo Biostability of CVD Silicon Oxide and Silicon Nitride Films,“ Micro- and nanosystems - materials and devices, 2005 ;
• G. Kotzar et al, „Evaluation of MEMS materials of construction for implantable medical devices,“ (eng), Biomaterials, vol. 23, no. 13, pp. 2737-2750, 2002 ; und
• K. Qian, M. o. d. Beeck, G. Bryce, K. Malachowski, and C. van Hoof, „Novel miniaturized packaging for implantable electronic devices,“ pp. 1-3, 2012.

In this special application, it would also be very advantageous to encapsulate these ASICs conformally, in particular to apply a protective layer of water- and gas-impermeable materials directly to the chip. Metals, for example, are ideal here, as discussed in the following articles:

• J. Jeong et al., "Conformal Hermetic Sealing of Wireless Microelectronic Implantable Chiplets by Multilayered Atomic Layer Deposition (ALD)," Adv. Fund Mater., Vol. 2, p. 1806440, 2018 ;
• JM Maloney, SA Lipka, and SP Baldwin, "In Vivo Biostability of CVD Silicon Oxide and Silicon Nitride Films," Micro- and nanosystems - materials and devices, 2005 ;
• G. Kotzar et al, "Evaluation of MEMS materials of construction for implantable medical devices," (eng), Biomaterials, vol. 23, no.13, pp. 2737-2750, 2002 ; and
• K. Qian, M. od Beeck, G. Bryce, K. Malachowski, and C. van Hoof, "Novel miniaturized packaging for implantable electronic devices," pp. 1-3, 2012.

Furthermore, control and contacting of the chips with DC voltage-free signals is desirable, since galvanic corrosion of the conductive contacts that are led out of the hermetic capsule can thus be reduced or even avoided (see Fig JW Osenbach, "Water-Induced Corrosion of Materials Used for Semiconductor Passivation," J. Electrochem. Soc., Vol. 140, no. 12, pp. 3667-3675, 1993 ). For the voltage supply of the chips in particular, rectification of the external alternating supply voltage is necessary, which requires large capacities. Filters for the input signals to be measured, which also require capacities, are also desirable.

A further example of active implantable ASICs are block capacitors that do not allow any leakage currents at the outputs for electrodes that stimulate biological tissue (required by the relevant standard, BS EN 45502-1: 2015-06-30, "Implants for surgery. Active implantable medical devices. General requirements for safety, marking and for information to be provided by the manufacturer ‟, issue date: 2015-06-30 ).

• Die mit den bekannten Anordnungen zu erreichenden Kapazitäten sind zu gering oder nur mit der kostenaufwendigen Nutzung großer Flächen des Chips zu realisieren. Standardkapazitäten im CMOS Prozess sind MIM (Metal-Insulator-Metal)-Strukturen mit etwa 1fF/µm², MOS (Poly-Oxid- Diffusion/Well) mit maximal 1-50 pF Kapazität oder MOM (Metal-Oxide-Metal) Strukturen mit etwa 0,2fF/µm². Weiterhin gibt es die Gateoxide der Transistoren, die mit <10fF/µm² groß sind, aber die maximalen nutzbaren Flächen sind zu klein. CPOD Kapazitäten (poly on diffusion) können bis zu 8 fF/µm² erreichen.

Known integrated circuit arrangements have the following disadvantages:

• The capacities that can be achieved with the known arrangements are too low or can only be achieved with the costly use of large areas of the chip. Standard capacities in the CMOS process are MIM (Metal-Insulator-Metal) structures with about 1fF / µm ² , MOS (Poly-Oxide-Diffusion / Well) with a maximum of 1-50 pF capacity or MOM (Metal-Oxide-Metal) structures with about 0.2fF / µm ² . There are also the gate oxides of the transistors, which are <10fF / µm ^{2 in} size, but the maximum usable areas are too small. CPOD capacities (poly on diffusion) can reach up to 8 fF / µm ² .

The capacities (e.g. support capacities) must therefore be built up externally with discrete components that have to be connected. The connection and these external components must be encapsulated together in a biomedical application, which represents a higher process engineering effort, as is the case, for example, in the article X. Liu et al, "Advances in Scalable Implantable Systems for Neurostimulation Using Networked ASICs," IEEE Des. Test, vol. 33, no. 4, pp. 8-23, 2016 is shown.

The hermetic encapsulation and isolation of the chips has to be done for biomedical applications in order to guarantee the longevity.

the US 2003/0122250 A1 refers to a thin high-frequency module with an integrated circuit chip with low susceptibility to breakage. The high frequency module of reference (1) includes an insulating substrate having a plurality of thin ceramic plates stacked in layers and an insulating layer formed on the top surface of the insulating substrate. In the high-frequency module, a thin-film circuit is formed on the upper side of the insulating layer, which circuit comprises a wiring pattern and an electrical part with a resistor and / or a capacitor. The wiring pattern is made of a thin film. The electrical part is connected to the wiring pattern and is made of a thin film. Therefore, the electrical part of the high-frequency module according to the invention can be shaped more precisely than an electrical part of a related high-frequency module. As a result, it is possible to provide a high-frequency module with high performance.

the U.S. 4,654,694 A discloses a case for an electronic component provided with a capacitor. The electronic housing has a capacitor in the form of a carrier plate which carries a component and is covered with a cap. In addition, the housing contains a capacitor which is placed on the carrier plate in such a way that it is located between the component and the cap.

There is therefore a need for integrated circuit arrangements which overcome the disadvantages of the prior art and which can be produced inexpensively, are robust and reliable.

This object is achieved by the subject matter of the independent claims. Advantageous embodiments of the present invention are the subject of the dependent claims.

The present invention is based on the idea of combining the hermetically compliant encapsulation of the ASICs and the required capacities in a post process using standard MEMS technology, which can be carried out on entire wafers at the same time. This enables integrated circuit arrangements and in particular ASICs with very much smaller ASIC volumes, while the requirements of standards, longevity and functionality remain met. The more general approach to the miniaturization of the ASICs is the relocation of the large required areas out of the ASIC into the encapsulation, which thus has an additional function. The side walls and the back of the ASICs are particularly suitable for this. At least two metal surfaces are applied in a MEMS process to e.g. a CMOS ASIC, which are separated by at least one insulating layer and thus form a capacitor.

For example, so-called high-k oxides can serve as insulation layers in the ALD (atomic layer deposition) process and form a capacitor on the unused outer surfaces of the ASICs between two built-up metal surfaces. The ALD layers form very large capacitances (metal-insulator-metal capacitors) because of their small thickness and large area.

The ALD process is a multi-stage deposition process that is essentially similar to deposition using chemical vapor deposition (CVD). CVD is based on a reaction of two reactive chemical precursors in the gas phase, which are deposited as a product on a substrate. In the case of ALD, the process is divided into separate stages. In the first step, the substrate is exposed to the gas phase of a reactive molecular precursor, with up to a monolayer of the precursor being chemisorbed on the substrate surface. Using the specific example of a deposition of aluminum oxide, trimethylaluminum (TMA), for example, can be used, which is highly reactive in the presence of water. In the second step, the excess of precursor molecules is removed by pumping in order to prevent an unwanted reaction in the gas phase. This results in the substrate being wetted with (ideally) a monolayer of TMA. Incidentally, this step is the main difference between ALD and CVD. In the next step, this substrate is exposed to the gas phase of the second molecular precursor, which immediately reacts with the monolayer of the first precursor to form the product. Using the example of the deposition of aluminum oxide, water vapor is usually used as a counter component to TMA. The excess water and the reaction products (here methane) are again removed by pumps and a separation cycle is thus completed. This procedure can be repeated according to the desired film thicknesses, the deposited film growing layer by layer. Depending on the nature of the substrate and the film, layers between 0.2 and 1.5 Angstroms thick can be deposited per cycle, which are usually also compliant on substrates with very complex structures. In contrast to other deposition methods, this results in the possibility of structures with high aspect ratios (lithographically produced structures and small pores) evenly over their length and with precise control of the layer thickness (in the sub- Angstrom range) and thereby change the material characteristics.

Furthermore, the outwardly directed metal surface can enclose the chip (except for the contacts) and at the same time serve as conformal hermetic encapsulation. In order to prevent galvanic corrosion, this metal surface must be connected as a ground contact for the capacitors. All deposits (insulator and metals) must be compatible with the ASIC (e.g. CMOS technology) (see e.g. S. Sedky, A. Witvrouw, H. Bender, and K. Baert, "Experimental determination of the maximum post-process annealing temperature for standard CMOS wafers," IEEE Trans. Electron Devices, vol. 48, no. 2, pp. 377-385, 2001 ). Therefore, low-temperature processes (temperatures below 500 ° C) are usually desirable, such as the ALD process or PECVD processes for insulators and sputtering and vapor deposition of metals.

In particular, an integrated circuit arrangement according to the present invention comprises at least one active electronic component, at least one passive electrical element and an electrically conductive housing in which the active electronic component is at least partially accommodated. The passive electrical element has at least a first electrode and a second electrode, which are separated by an insulating or semiconducting layer. The first electrode inside the housing is connected to the active electronic component, and the second electrode is formed by at least a part of the housing. In this way, further required passive components such as capacitors, inductors and / or diodes can be added in a housing process downstream of the production of the electronic component. These passive components do not require any installation space on the active surface of the electronic component, so that the circuit arrangement according to the invention is particularly compact. The embedding of the post-processed passive components, in particular capacitors, leads to considerable space and cost savings in the case of commercially available CMOS ASICs as active components. No external components (independent of the chip) are required. The chips are encapsulated and thus long-term stability is ensured. Furthermore, critical elements such as filters, rectifiers and block capacitors can be integrated directly into the chip, which guarantee a DC voltage-free supply, which also enables long-term stability in aqueous environments. Finally, block capacitances can be integrated for safety in the event of electrical stimulation with electrodes and a greater variety of signal filters can be used, which may require large capacities.

According to an advantageous development of the present invention, the at least one electronic component has a base body with opposing base and top surfaces and side surfaces running transversely thereto, the at least one first electrode being arranged along at least one of the side surfaces. In this way, the otherwise unused side surfaces are used to accommodate the passive components and the structure of the integrated circuit arrangement becomes particularly compact and space-saving.

According to the invention, the active electronic component has at least one electrical connection that is led to the outside through the housing. In particular, it can be provided that the active electronic component is connected to at least one electrical connection arranged on an outside of the integrated circuit arrangement and the at least one electrical connection is electrically insulated from the rest of the housing by an electrically insulating material. This ensures maximum safety and stability for use in an aqueous environment.

The advantages of the present invention come into play in particular when the at least one electronic component has a user-specific integrated circuit, ASIC.

In order to realize a particularly space-saving and efficient capacitor, the at least one passive element can have at least one dielectric insulator layer with a high relative permittivity (“high-k dielectric”), which is arranged between the first and the second electrode.

In semiconductor technology, a high-k dielectric is a material that has a higher dielectric constant than conventional silicon dioxide (ε _r = 3.9) or oxynitride (ε _r <6). The term "high-k" is borrowed from English, where the relative permittivity ε _{r is} often referred to as k or κ (kappa).

In order to improve the properties of integrated circuits, for example to reduce the power consumption of highly integrated circuits and memories or to achieve higher switching speeds, the structures are reduced in size. Due to the progressive miniaturization of microelectronic components, the semiconductor industry is increasingly reaching its physical limits and is confronted with higher leakage currents due to quantum mechanical effects. The tunnel current increases with the reduction of the gate dielectric thickness below 2 nm strong. Large capacities (for storing the status between the refresh cycles) with low leakage currents (power loss) are particularly important for memory production. If one considers z. B. a simple plate capacitor, the capacitance C is calculated as follows: $$\mathrm{C.}=\frac{{\epsilon }_0{\epsilon }_r\mathrm{A.}}{d}$$

Here d is the plate spacing, A the area of the capacitor plates, ε ₀ the absolute dielectric constant of the vacuum and the material constant ε _r the relative permittivity of the insulation layer.

Accordingly, by using high-k materials (larger ε _r ), the thickness of the insulator layer in MIS structures ( _{often also called MOS due to SiO 2} ) can be increased while maintaining the same capacitance, with leakage currents being drastically reduced through the thicker insulator.

In contrast, there are the low-k dielectrics, which are used as an insulator between the interconnects and reduce the parasitic capacitances that arise due to their low dielectric constant.

Various material systems are used, such as amorphous oxides of metals (e.g. Al ₂ O ₃ , Ta ₂ O ₅ ) or transition metals (e.g. HfO ₂ , ZrO ₂ ). Crystalline oxides of rare earths (e.g. Pr ₂ O ₃ , Gd ₂ O ₃ and Y ₂ O ₃ ) represent a more extensive approach, which enable lattice-adapted growth and thus a perfect interface between semiconductor and insulator. Other materials that can be used are BaTiO ₃ , Si ₃ N ₄ , BaO, and La ₂ O ₃ . The most important materials are TiO ₂ , ZrO ₂ , HfO ₂ , SiO ₂ , Si ₃ N ₄ and Al ₂ O ₃ . Of course, layer sequences of various of these materials can also be used.

In order to increase the capacitance of such a capacitor even further, it can be provided that alternating dielectric insulating layers and metallization layers are arranged between the first and second electrodes in order to form a multilayer capacitor, the metallization layers being alternately connected to the first or the second electrode.

As is known, multilayer capacitors, in particular multilayer ceramic capacitors (MLCC), are composed of a large number of stacked capacitors, so that metal layers alternate with insulator layers. The metal layers are in turn connected alternately to the first and the second electrode for electrical contacting. The advantage of such a multilayer capacitor is the compact design with high capacitance. Further layers, such as B. layers for mechanical stress relief, can also be provided in the multilayer capacitor.

For use in aqueous media, in particular for implantable electronic components, it is provided that the housing hermetically encapsulates the at least one active electronic component.

• Bereitstellen mindestens einer aktiven elektronischen Komponente,
• Aufbringen einer Metallisierungsstruktur zum Erzeugen einer ersten Elektrode,
• Ausbilden mindestens eines passiven elektrischen Elements an der aktiven elektronischen Komponente, so dass das passive elektrische Element mit der ersten Elektrode verbunden ist,
• Aufbringen eines elektrisch isolierenden Materials zum elektrischen Isolieren der ersten Elektrode,
• Anbringen eines elektrisch leitfähigen Gehäuses, in welchem die aktive elektronische Komponente wenigstens teilweise aufgenommen ist, wobei das passive elektrische Element mindestens eine zweite Elektrode aufweist, und wobei die zweite Elektrode durch mindestens einen Teil des Gehäuses gebildet ist.

The present invention also relates to an associated method for producing an integrated circuit arrangement, the method comprising the following steps:

• Providing at least one active electronic component,
• Applying a metallization structure to produce a first electrode,
• Forming at least one passive electrical element on the active electronic component so that the passive electrical element is connected to the first electrode,
• Applying an electrically insulating material for electrically insulating the first electrode,
• Attaching an electrically conductive housing in which the active electronic component is at least partially accommodated, the passive electrical element having at least one second electrode, and the second electrode being formed by at least part of the housing.

In this case, the at least one electronic component can have a base body with opposing base and top surfaces and side surfaces running transversely thereto, the at least one first electrode being arranged along at least one of the side surfaces.

For use in aqueous media it can be provided that the active electronic component has at least one electrical connection that is led to the outside through the housing and that the at least one electrical connection is electrically insulated from the housing by the electrically insulating material. A particularly high level of safety and long-term stability can be achieved if the housing has platinum, titanium and / or gold and / or the electrically insulating material has SiO ₂ and / or Si ₃ N ₄ .

The advantages of the present invention come into play in particular when the at least one electronic component has a user-specific integrated circuit, ASIC, has.

In order to realize a particularly space-saving and efficient capacitor, the at least one passive element can have at least one dielectric insulator layer with a high relative permittivity, which is arranged between the first and the second electrode. In order to increase the capacitance of such a capacitor even further, it can be provided that alternating dielectric insulating layers and metallization layers are arranged between the first and second electrodes in order to form a multilayer capacitor, the metallization layers being alternately connected to the first or the second electrode. The dielectric insulator layer can advantageously be applied to the metallization layer in an atomic layer deposition process, ALD. For example, the dielectric isolator layer can be high-k materials such as e.g. B. Al ₂ O ₃ , Ta ₂ O ₅ , TiO ₂ , HfO ₂ , Pr ₂ O ₃ , Gd ₂ O ₃ , Y ₂ O ₃ , BaTiO ₃ , SiO ₂ , Si ₃ N ₄ , BaO, La ₂ O ₃ , and / or ZrO ₂ .

According to an advantageous embodiment of the present invention, the at least one active electronic component is hermetically encapsulated in the step of attaching the electrically conductive housing.

• 1 eine schematische Schnittdarstellung einer integrierten Schaltungsanordnung gemäß einem ersten Aspekt der vorliegenden Erfindung;
• 2 eine schematische Schnittdarstellung einer integrierten Schaltungsanordnung gemäß einem weiteren Aspekt der vorliegenden Erfindung;
• 3 eine schematische Schnittdarstellung einer integrierten Schaltungsanordnung gemäß einem weiteren Aspekt der vorliegenden Erfindung.

For a better understanding of the present invention, it is explained in more detail using the exemplary embodiments shown in the following figures. The same parts are provided with the same reference numerals and the same component names. Furthermore, some features or combinations of features from the different embodiments shown and described can represent in themselves independent, inventive or inventive solutions. Show it:

• 1 a schematic sectional illustration of an integrated circuit arrangement according to a first aspect of the present invention;
• 2 a schematic sectional illustration of an integrated circuit arrangement according to a further aspect of the present invention;
• 3 a schematic sectional illustration of an integrated circuit arrangement according to a further aspect of the present invention.

The present invention is explained below with reference to the figures, and in particular initially with reference to the schematic sectional views of FIG 1 , explained in more detail. It is noted that in all of the figures the size ratios and in particular the layer thickness ratios are not necessarily shown true to scale. Furthermore, the three-dimensional structure of the integrated circuit arrangements is not shown in the figures. The integrated circuit arrangements usually have a rectangular outline shape in plan view. Of course, round, oval or polygonal shapes can also be selected.

1 shows an integrated circuit arrangement in the form of a schematic sectional illustration 100 according to a first advantageous embodiment. The integrated circuit arrangement 100 exhibits as active electronic component 102 an application specific integrated circuit (ASIC). The ASIC 102 has a basic body 104 with a top surface 106 and a base 108 . There are also side faces 110 arranged at an angle different from 90 °, so that the cross section of the base body 104 is trapezoidal. Of course, the ASIC 102 also be cuboid, with the side surfaces at right angles to the base and top surfaces.

For the creation of electrical connections that are to be led to the outside, and for the formation of the first electrode, various passive electrical elements are on the surface of the base body 104 a first, internal metallization layer 112 arranged.

According to the present invention, the integrated circuit arrangement 102 integrated capacitors. A first capacitor 120 is on one of the side faces 110 arranged and has a first electrode 114 through the structured first metallization layer 112 is trained. Another capacitor 116 is at the base 108 of the ASIC 102 educated. His first electrode 118 is also by structuring the first metallization layer 112 generated. Rear-side contacting of the first electrode can also be implemented by means of a through-silicon via (TSV) (not shown in the figure).

According to the invention is on each of the first two electrodes 114 , 118 a dielectric with high relative permittivity (high-k dielectric) 122, 124 is deposited. This dielectric insulating layer can, for example, Al ₂ O ₃ (ε _r = 9), Y ₂ O ₃ (ε _r = 15), La ₂ O ₃ (ε _r = 30), Ta ₂ O ₅ (ε _r = 26), TiO ₂ (ε _r = 80), HfO ₂ (ε _r = 25) and / or ZrO ₂ (ε _r = 25).

Furthermore, the remaining surface of the ASIC 102 with an electrically insulating material 126 coated. There are openings for vias 128 to the first metallization layer 112 intended. The electrically insulating material 126 may include any suitable organic or inorganic substance. For example, inorganic materials such as silicon dioxide or silicon nitride or the dielectric used for the capacitors are used.

For hermetically encapsulating the ASIC 102 comprises the integrated circuit arrangement 100 a housing 130 , which is made according to the invention from an electrically conductive material. The housing is advantageously made 130 made of metal. Particularly suitable for the manufacture of the hermetically sealed housing 130 are inert metals such as platinum, titanium or gold.

According to the present invention, the housing forms 130 the second electrodes 132 , 134 of the two capacitors 120 or. 116 . These second electrodes 132 , 134 are grounded during operation of the integrated circuit arrangement.

For making electrical contact with the contacts of the ASIC that are not connected to ground 102 and the first electrodes 114 , 118 are electrical connections 136 placed on the outside so that it passes through the electrically insulating material 126 from the rest of the housing 130 are isolated and form, for example, contact pads. In the schematic representation of the 1 is only a single connection area 136 shown. It goes without saying that there are usually more than one connection not connected to ground 136 intended.

Furthermore, one of the connection areas can also be provided 136 and not the case 130 to be connected to ground potential during operation. For implanted integrated circuit arrangements, however, it is advantageous if the conductive housing is at ground potential during operation.

Regarding 2 is now an integrated circuit 200 explained in detail according to a further advantageous embodiment.

The integrated circuit arrangement 200 has an active electronic component, such as an ASIC 202 , and an electrically conductive housing 230 on that the ASIC 202 hermetically encloses. The housing is advantageously made 230 made of metal. Particularly suitable for the manufacture of the hermetically sealed housing 230 are inert metals such as platinum, titanium or gold.

The active electronic component, for example an ASIC 202 , has a base 208 and a top surface 206 . Compared to the arrangement out 1 are the side faces 210 much smaller than the base and top areas 208 , 206 . Hence the top surface 206 partly for attaching a capacitor 220 used. A first electrode 214 is for this on the top surface 206 formed and with a high-k dielectric 222 coated. How regarding 1 mentioned, the dielectric insulating layer can, for example, Al ₂ O ₃ (ε _r = 9), Y ₂ O ₃ (ε _r = 15), La ₂ O ₃ (ε _r = 30), Ta ₂ O ₅ (ε _r = 26) , TiO ₂ (ε _r = 80), HfO ₂ (ε _r = 25) and / or ZrO ₂ (ε _r = 25).

Furthermore, according to the present embodiment, a second electrode 232 that are on the high-k dielectric 222 is deposited to form a plate capacitor, only in the area of the terminal 236 from the housing 230 formed while the area of the electrode that shared the high-k dielectric 222 is in contact, of an electrically insulating material 226 is covered.

At the in 2 The embodiment shown can either be the connection during operation 236 the second electrode 232 or the first electrode 214 be put on ground. In the event that the first electrode is connected to ground potential, it can also be provided that the first electrode is connected to the rest of the housing 230 is electrically connected (not visible in 2 ). The electrically insulating material 226 separates the connection area 236 and the entire second electrode 232 electrically from the rest of the housing 230 . The electrically insulating material 126 may include any suitable organic or inorganic substance. For example, inorganic materials such as silicon dioxide or silicon nitride or the dielectric used for the capacitor are used.

3 shows a further advantageous embodiment of an integrated circuit arrangement 300 according to the present invention. The integrated circuit arrangement 300 exhibits as active electronic component 302 an application specific integrated circuit (ASIC). The ASIC 302 has a basic body 304 with a top surface 306 and a base 308 . There are also side faces 310 arranged at an angle different from 90 °, so that the cross section of the base body 304 is trapezoidal.

The embodiment of the 3 corresponds to the embodiment of 1 in that a capacitor 320 on one side surface 310 of the ASIC 302 is arranged. In contrast to the arrangements described so far, the capacitor 320 designed as a multilayer capacitor with three layers of dielectric 322 alternating with first and second electrodes 312 , 332 are stacked on top of each other. Two first electrodes each 312 and two second electrodes each 332 are electrically connected to one another, as is known for a multilayer capacitor. As a result, the capacitance of the capacitor 320 can be significantly increased compared to the simple plate capacitor arrangement. The dielectric 322 is advantageously formed by a dielectric with high relative permittivity (high-k dielectric). This dielectric insulating layer can, for example, Al ₂ O ₃ (ε _r = 9), Y ₂ O ₃ (ε _r = 15), La ₂ O ₃ (ε _r = 30), Ta ₂ O ₅ (ε _r = 26), TiO ₂ (ε _r = 80), HfO ₂ (ε _r = 25) and / or ZrO ₂ (ε _r = 25).

Furthermore, the outermost second electrode 332 through the housing 330 formed which the ASIC 302 hermetically encloses. During operation, this electrode is expediently connected to ground potential. The case 330 is made according to the invention from an electrically conductive material. The housing is advantageously made 330 made of metal. Particularly suitable for the manufacture of the hermetically sealed housing 330 are inert metals such as platinum, titanium or gold.

Furthermore, the remaining surface of the ASIC 302 with an electrically insulating material 326 coated. There are openings for vias 328 to the first metallization layer (the electrical connection is not visible in the figure). The electrically insulating material 326 may include any suitable organic or inorganic substance. For example, inorganic materials such as silicon dioxide or silicon nitride or the dielectric used for the capacitors are used.

In summary, the present invention proposes a hermetic encapsulation of an ASIC with a metal surface, which at the same time serves as an electrode for a post-processed capacitance with a high-k material. The second electrode is applied directly to the ASIC or the insulator that is placed in between. The capacitor can be applied to all unused areas of the ASIC, in particular the side walls and the rear. To further increase the capacitance, a multilayer capacitor can be produced by alternating the arrangement of insulators and the two electrode surfaces.

The present invention has the advantage that a user can realize large capacitors on an area already invested and thus z. B. support capacitors, filters or block capacitors that otherwise have to be built discretely outside of the silicon chip. So z. B. Capacities for rectifying input signals can be implemented on very small ASICs, thus enabling a DC voltage-free supply. This is very helpful in particular for implantable ASICs (or ASICs to be used in general in an aqueous environment), since it prevents galvanic corrosion of the active components. In addition, for chips in an aqueous environment, an electrode, in particular mass, can hermetically seal the chip and thus increase the service life.

This enables the ASICs to be scaled to smaller and smaller units, which is an important goal for implantable systems.

List of reference symbols

100, 200, 300

Integrated circuit arrangement

102, 202, 302

Active electronic component; ASIC

104, 204, 304

Base body

106, 206, 306

Deck area

108, 208, 308

Floor space

110, 210, 310

Side face

112, 212, 312

First metallization layer

114, 214, 314

First electrode of the first capacitor

116

Second capacitor

118

First electrode of the second capacitor

120, 220, 320

First capacitor

122, 222, 322

High-k dielectric

124

High-k dielectric

126, 226, 326

Electrically insulating material

128, 228, 328

Via

130, 230, 330

casing

132, 232, 332

Second electrode of the first capacitor

134

Second electrode of the second capacitor

136, 236, 336

connection

Claims (16)

Integrated circuit arrangement (100) comprising: at least one active electronic component (102), at least one passive electrical element (120), an electrically conductive housing (130) in which the active electronic component (102) is at least partially accommodated, the passive electrical element (120) at least a first electrode (114) and a second Electrode (132), wherein the first electrode (114) inside the housing (130) is connected to the active electronic component (102), and wherein the second electrode (132) is formed by at least part of the housing (130) and wherein the active electronic component (102) is connected to at least one electrical connection (136) arranged on an outside of the integrated circuit arrangement (100) and the at least one electrical connection (136) is connected to the rest by an electrically insulating material (126) Housing is electrically isolated. Integrated circuit arrangement according to Claim 1 , wherein the at least one passive electrical element (120) has a capacitor, an inductance and / or a diode. Integrated circuit arrangement according to Claim 1 or 2 , wherein the at least one active electronic component (102) has a base body (104) with opposing base and top surfaces (108, 106) and side surfaces (110) running transversely thereto, and wherein the at least one first electrode (114) along at least one of the side surfaces (110) is arranged. Integrated circuit arrangement according to one of the preceding claims, wherein the at least one active electronic component (102) has a user-specific integrated circuit, ASIC. Integrated circuit arrangement according to one of the preceding claims, wherein the at least one passive element (120) has at least one dielectric insulator layer (122) with a high relative permittivity, which is arranged between the first and the second electrode (114, 132). Integrated circuit arrangement according to Claim 5 wherein dielectric insulator layers (322) and metallization layers are arranged alternately between the first and second electrodes (314, 332) in order to form a multilayer capacitor, and wherein the metallization layers are alternately connected to the first or the second electrode. Integrated circuit arrangement according to one of the preceding claims, wherein the housing (130) hermetically encapsulates the at least one active electronic component. A method for producing an integrated circuit arrangement (100), the method comprising the following steps: Providing at least one active electronic component (102), Applying a metallization structure (112) to produce a first electrode (114), Forming at least one passive electrical element (120) on the active electronic component (102) so that the passive electrical element (120) is connected to the first electrode (114), Applying an electrically insulating material (126) for electrically insulating the first electrode (114), Attaching an electrically conductive housing (130) in which the active electronic component (102) is at least partially accommodated, the passive electrical element (120) having at least one second electrode (132), and the second electrode (132) being at least part of the housing is formed. Procedure according to Claim 8 , wherein the at least one active electronic component (102) has a base body (104) with opposing base and top surfaces (108, 106) and side surfaces (110) running transversely thereto, and wherein the at least one first electrode (114) along at least one of the side surfaces (110) is arranged. Procedure according to Claim 8 or 9 wherein the active electronic component (102) has at least one electrical connection (136) led to the outside through the housing (130) and the at least one electrical connection (136) is electrically insulated from the housing by the electrically insulating material (126). Procedure according to Claim 10 , wherein the housing comprises platinum, titanium and / or gold, and / or wherein the electrically insulating material comprises SiO ₂ and / or Si ₃ N ₄ . Method according to one of the Claims 8 until 11 wherein the at least one active electronic component (102) has a user-specific integrated circuit, ASIC. Method according to one of the Claims 8 until 12th wherein the at least one passive element (120) has at least one dielectric insulator layer (122) with a high relative permittivity, which is arranged between the first and the second electrode (114, 132). Procedure according to Claim 13 wherein insulator layers and metallization layers are alternately arranged between the first and second electrodes (114, 132) in order to form a multilayer capacitor, and the metallization layers are alternately connected to the first or the second electrode. Procedure according to Claim 13 or 14th wherein the dielectric isolator layer (122) is applied to the metallization layer in an atomic layer deposition, ALD, process. Method according to one of the Claims 8 until 15th wherein in the step of attaching the electrically conductive housing the at least one active electronic component (102) is hermetically encapsulated.

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