DE10220584B3 - Dynamic memory cell and method of making the same - Google Patents

Abstract

An electrically conductive surface strap contact (20) in a DRAM memory cell (101) with a trench capacitor (1) and a planar selection transistor (2) establishes a connection between a diffusion region (3) of the transistor (2) and the trench capacitor (1) , wherein it at least partially covers the diffusion region (3) horizontally and is formed above the substrate surface. The storage node (15) of the trench capacitor (1) is enclosed by at least one oxide collar (21) for isolation from the diffusion regions (3, 4) on the substrate side. An oxide cover (23) lies directly on the oxide collar (21). An opening (24) in this oxide cover (23), which is filled with electrically conductive material and is connected to the surface strap contact, leads vertically from the surface to the storage node (15). In an advantageous layout, there is an array of MINT memory cells, each with an area of 8 F × 2 ×, in which areas of active areas are formed as long, contiguous bars that cross several cells (101).

Description

The present invention relates to an integrated dynamic memory cell with a planar selection transistor and a trench capacitor.

A dynamic memory is in the generally formed from an array of single transistor cells, wherein for example, each cell has a selection transistor and a trench capacitor includes. Random access to those in the storage node of the trench capacitor stored information takes place via a word line, which forms a gate contact of the selection transistor with the substrate. The information is about a bit line read out, which is connected to a first doped diffusion region is. An electrical impulse on the word line can be used an electrical connection from the first diffusion region to one second doped diffusion region can be switched in the cell, which is connected to the storage node of the trench capacitor is. The possible charge states The logic states "0" and "1" are assigned to the trench capacitor.

To achieve the highest possible integration densities and associated savings in material, space and costs, be as possible small cell sizes at the memory cells sought. The progressive downsizing a memory cell in the layout of a cell from the constantly evolving one Being able to separate lithography techniques is the cell area in units of the square of those currently achievable with lithography techniques minimum structure width F specified on a wafer. At present The selection transistors are usually memory modules in production arranged planar. The one arranged on the substrate surface of the wafer Gate contact must be at a distance corresponding to a minimal structure width 1 F from the trench capacitor. The intermediate area corresponds to that from the second diffusion area Room.

A bit line contact, also referred to as a diffusion contact, is arranged on the other side of the gate contact. With the condition that the distances to the gate contacts or trench capacitors of the neighboring cells must also be at least a minimum structure width 1 F, a minimum cell area of 8 F ² results for planar single transistor cells.

To manufacture such small cell areas to be able Particularly advantageous cell layouts were developed in which the mutual isolation of the cells on the one hand by a flat Trench isolation (STI) and on the other hand through Formation of so-called oxide collars (English collars) is achieved. The oxide collar provides insulation the storage node fill from the surrounding n- or p-doped Well of the selection transistor. It must be distinguished from the as Capacitor dielectric layer used in the lower area of the capacitor. This layer separates the storage node as a storage medium from one several trenches connecting, deeply buried doped region as a second capacitor plate (buried plate).

The STI causes isolation between the active diffusion areas of adjacent memory cells on the one hand and between the storage node and one across the storage node current passive word line in the memory cell on the other hand.

The memory cell concept described is also called MINT (Merged Isolation Node Trench) and saves cell area the cell isolation included in the trench wall. The contact to the diffusion area is done today a so-called buried strap. On the Gate contact side of the trench capacitor is located there is a gap in the insulating material in the upper trench wall Oxide collar and STI insulation. When manufacturing the trench capacitor At this point, arsenic is typically highly doped with arsenic deposited, which diffuses out at high temperatures and thus makes contact with the adjacent doped substrate.

Diffusion at the buried contact takes place with a penetration depth of 90 nm, for example. Target is that on the one hand the resistance in the buried contact at the substrate-trench capacitor transition preferably low-resistance is formed, but on the other hand the out-diffusion is not down to the depletion area of the substrate under the gate contact enough. This is the process of out-diffusion set maximum or minimum limits, which to the specified Lead value of 90 nm. With the current technology generation of 170 nm for lithographic Structure width and a distance of the trench capacitor from the gate contact of 125 nm results with the stated value for the diffusion depth, which was obtained from simulations, a distance of 35 nm between the out-diffusion area and the gate contact.

Would the for the diffusion needed Length greater than the distance between the gate contact and the trench capacitor and so that they reach into the depletion area of the gate contact, then could this has the consequence that the current in the off state and the threshold voltage of the selection transistor be modulated disadvantageously. This can cause the memory cell to fail and thus lead to a loss of yield in the production of storage. With the specified technology generation (170 nm) this condition becomes due to very tight overlay tolerances of less than 45 nm on the wafer, or 40 nm in the X direction based on one single chip adhered to.

A big problem arises from the fact that for the next technology generations, ie 140 nm, 110 nm etc. with approximately the same penetration depths of the outdiffusion, the distances of the trench capacitor from the gate contact will be so small that the selection transistor will also be affected while adhering to the tightest overlay tolerances. Even with the 170 nm technology generation, the value of 45 nm for the overlay tolerance can only be maintained by a considerable reduction in systematic errors, for example by using identical exposure tools for successive lithography steps. With the 140 nm technology generation there are approaches to reduce the thermal budget of the overall process during out-diffusion. Efforts are being made in the same direction to reduce the contact transition in its cross-sectional area, but both approaches lead to increased contact resistance.

In the publication DE 38 44 388 A1 describes a dynamic memory cell with random access, in which a connection between a doped region of the selection transistor of a memory cell and the trench capacitor storing the charge is established via a contact arranged above the substrate surface. The storage node is surrounded all around by an insulation collar below the substrate surface.

It is the object of the present invention to offer a DRAM memory cell architecture in which, on the one hand, the MINT concept with a memory cell area of 8 F ^{2 is} made possible, but on the other hand the problem of the distance of the trench or trench capacitor, which can no longer be reduced due to the out-diffusion and gate contact is released.

The task is solved by a DRAM memory cell with the features of claim 1 and by A method of manufacturing the DRAM memory cell according to claim 6. Further configurations of the memory cell are specified in the dependent claims.

One that can also be called a surface strap Contact consists of electrically conductive material, which the active diffusion area between the first word line and the trench capacitor - at least partially covered. This means in particular that the Contact above the substrate surface with the diffusion area is electrically connected.

The trench capacitor storage node is enclosed by at least one oxide collar, so no electricity from the diffusion area or the n or p well in the storage node flow can. An oxide cover lies directly on the oxide collar, the collar (English trench top oxide, TTO). This preferably closes plan with the substrate surface and closes thus the trench of the trench capacitor. Just through an opening in this oxide lid, which is filled with electrically conductive material, and vertically from the surface leads to the storage node material, electrical connections from Storage node to the outside allows. The opening or the electrically conductive material contained therein preferably has no electrically conductive connection with the Trench wall to the substrate. This will isolate the interior of the trench from the top of the oxide collar to the surface of the Substrates continued.

The electrically conductive material of the contact covered not just a diffusion area of the substrate, but also one first part of the trench opening, which is the opening included in the oxide lid. The contact is therefore preferably from a horizontal layer, which rests on the substrate and oxide cover surface, as well as the associated filling the opening in the oxide lid.

This arrangement is achieved by arranging it over the substrate surface Contact through a special shape of the second, passive Word line.

The passive word line which completely covers the trench is provided with a smaller width in cross section above the trench than in the regions between the trenches and the gate contacts or directly above the gate contacts. In configurations, two options are given, which are preferably also combined:
The word line has a smaller width than the trench, so that the contact arranged next to the passive word line can cover the first part of the oxide lid with the oxide lid opening, and / or the word line is eccentrically removed from the two gates at the location of the trench capacitor. Contacts of two ideal lines connecting adjacent cells in the Y direction are pushed out. It then only partially covers the trench capacitor opening, for example laterally offset. This concept can also be referred to as a "wiggled word line" concept.

The invention is particularly advantageous in the case of an 8 F ² MINT cell in which the distance of the gate contact from the trench capacitor is only about 1 F. The problem of the high depth of penetration when doping the substrate to form conventional buried contacts is avoided by the fact that the contacts are formed according to the invention via conductive material outside the substrate.

A particular advantage of the present invention results from a further embodiment: The shallow trench isolation for electrical isolation (English: shallow trench isolation, STI) of the doped or active areas from those of neighboring cells is formed for the individual memory cell in at least two non-contiguous areas. According to the invention, the insulation is only required on each long side of the selection transistor, while the insulation of the trench capacitor, for example to an adjacent trench capacitor of a further memory cell, is ensured by the oxide collar and the oxide cover according to the invention.

As the long side of a memory cell In this document, the side that designates the sequence first doped region, gate connection, second doped region and limit the trench capacitor laterally. As headers denoted those sides which are only the ends of this sequence limit: first doped region and trench capacitor.

So far, the formation of active Areas structured, for example, 6 F long bars lithographically structured. Two neighboring cells are mirror-symmetrical about a common bit line contact arranged along these bars. That is, along a word line are the gate contacts and the trench capacitors of two, respectively neighboring cells face each other. The formation of the STI trench between two trench capacitors for mutual isolation were required lithographic structuring that the structuring of the active areas do not require bars at their headers or long sides could be connected. Because the structuring of the active areas high demands on the lithographic techniques due to their small dimension, had to in optical exposure, the so-called optical proximity correction applied to the line-shortening effect called line shortening to compensate for the head ends of the beams, the too narrow lines even stronger comes into play.

According to the present invention can they active areas are now formed as long lines. So that will also advantageously solved the problem of line end shortening. Furthermore the susceptibility decreases against lens aberrations. The proximity effects are also reduced. Also receives the structure called the dummy line at the edge of the memory cell array a larger process window for the Structuring as if each active area of a cell individually should be isolated.

According to one embodiment, in addition to first oxide collar a second oxide collar in the trench directly arranged above the first oxide collar. The second oxide collar is in the Manufacturing deposited with a lower thickness, so that the im Oxide lid laterally offset opening for the Contact a sufficiently large transition area to that receives conductive material of the storage node. The thickness of the second oxide collar must however be big enough so that in the adjacent substrate no parasitic transistor arises.

An important advantage of the present Invention results from the fact that because of the here not intended diffusion area in a buried contact the associated problem of so-called VRT errors (variable Retention time) is avoided. The cause of these VRT errors are Relocations in the active area. The place of origin for the transfers is the point with the highest Tension density, the so-called triple point. Limit at the triple point the areas of the active areas, shallow trench isolation (STI) and the buried contact conventionally used together. As evasive measures so far only the introduction of a nitride interface in the area of the buried contact Available. The voltage density increases with increasing nitride interface thickness at the triple point reduced, reducing the likelihood of dislocations sinks. However, if the nitride interface is formed too thick, then the subsequent diffusion process may not be sufficient, so that the Resistance of the buried contact increases and the saturation current of the selection transistor falls.

The invention will now be based on a embodiment with the help of drawings explained become. Show in it

• 1 a cell layout of a DRAM memory cell according to the prior art (a) and the mutual arrangement of four such cells in a memory cell array (b),
• 2 a cross section through a DRAM memory cell with MINT layout according 1 with buried contact,
• 3 an inventive cell layout of a DRAM memory cell with surface contact (a) and the arrangement of four such memory cells in a memory cell array (b),
• 4 the cross section of a memory cell according 3 with surface contact.

The present invention is based on a comparison with a conventional DRAM memory cell 100 be described with 8 F ² MINT cell layout. A DRAM memory cell 100 with 8 F ² MINT cell layout according to the state of the art is in 1 shown in a schematic top view. In the right area of the 1 shown cell area is a trench capacitor 1 , which is essentially below a passive word line 8th located. The trench capacitor 1 is connected by a source area 3 with a gate contact on the side 2 which is essentially below an active word line 7 is arranged. The selection transistor is completed by a drain region 4 on which the bit line contact in the drawing level from above 5 to the electrical connection. Shallow isolation trenches 6 shield the active areas of the cell from those of the neighboring cells. In 1 not shown, the trench capacitor is isolated by oxide collars. It should be emphasized that the distance of the gate contact 2 to the trench capacitor 1 is exactly 1 F. Memory cells with a cell layout according to 1 could only be operated according to the prior art with buried contacts for the trench capacitor connection.

1b relates to the arrangement of four adjacent memory cells 100 in a memory cell array. For the sake of clarity, the shallow isolation trenches are 6 hatched, and the bit line contacts 5 colored black. In this arrangement, a word line sweeps over the representation of the 1b alternately in the Y direction, first a memory cell for gate contacting and then a trench of an adjacent DRAM memory cell as a passive word line B. The memory cell 100 is on one side through the bit line contact 5 limited, which on an active area connecting two adjacent memory cells, the drain area 4 is located, while on the other side between two trench capacitors there is an isolation trench separating the neighboring memory cells 6 located. As a result, two adjacent memory cells have an elongated, common active area, which is provided by a trench capacitor 1 to the next trench capacitor of an adjacent memory cell.

2 shows the cross section through the memory cell according to 1 , which is known from the prior art. The bit line seen here in longitudinal section 9 meets via the bit line contact 5 to the drain area 4 , which was produced for example by phosphorus doping in an implantation step. The word line shown here in cross section 7 consists of a stack containing a polysilicon layer 41 , a tungsten silicon layer 42 and a silicon nitride cap 43 , The gate contact is made by a gate oxide, not shown here 2 to the underlying depleted area of the p-well. The source area 3 is connected to the buried contact 50 , which was formed by diffusion out of a third poly-silicon filling of the trench highly doped with arsenic. The third polysilicon filling is connected to the second polysilicon filling 32 inside the trench capacitor 1 which by a first oxide collar 21 is completely isolated from the surrounding substrate. The oxide collar 21 reaches down in the trench to a height at which the storage node 15 with the first polysilicon filling 31 only of an ONO dielectric from the buried plate connecting several trench capacitors 71 is separated.

Passive word line 8th is the trench capacitor 1 through a shallow isolation trench 6 separated, which reaches up to an adjacent trench capacitor of an adjacent memory cell. The word lines 7 . 8th are laterally by spacers 44 and through nitride liners 45 isolated.

An embodiment of the present invention will be described below. 3a shows the cell layout of a DRAM memory cell according to the invention 101 , A contact formed on the substrate surface 20 covers a large part of the source area 3 and a first part 51 the opening of the trench capacitor 1 , The position of the gate contact 2 and the trench capacitor 1 remain behind compared to the example according to the prior art 1 unchanged. In contrast, the passive word line 8th to release the first part 51 the trench capacitor opening is shifted somewhat towards the edge of the memory cell and its cross-section is reduced at this position. According to an advantageous embodiment of the present invention, a mask is used in the production of the memory cell according to the invention when structuring the active areas, which forms these active areas as lines extending essentially over the entire memory cell field. This advantageously solves problems of line-end shortening during exposure with an appropriate mask. This corresponds to a non-isolated area in the layout 12 in the substrate surface at the edge of the memory cell, which was previously covered by a shallow isolation trench.

3b shows the arrangement of four such memory cells 101 in a memory cell array. The word lines 7 or 8 form serpentine lines, which can also be called wiggled word lines.

The cross section of the memory cell according to the invention 101 is in 4 shown. In contrast to the memory cell 100 According to the prior art, a memory cell is used in this embodiment according to the invention 101 a contact 20 between gate contact 2 and trench capacitor 1 on the substrate surface, ie on the source diffusion region doped with phosphorus, for example 3 educated. On the contact 20 is the liner 45 , The contact is arranged above the substrate surface and extends over a first part 51 the trench opening. There is an oxide lid in the trench opening 23 , A second part 52 the trench opening is made by a passive word line 8th covered, which according to 3a is laterally offset and has a narrower cross section at this point. Below the word line 8th isolates the oxide lid 23 the conductive materials 41 and 42 the second word line 8th of a third polysilicon filling 33 to form the storage node 15 of the trench capacitor 1 , Below the first part 51 there is an opening in the trench opening 24 inside the oxide lid 23 , which is filled with conductive material, for example polysilicon. It is part of the contact 20 to connect the storage node 15 with the doped diffusion area 3 ,

In the example according to the invention, the vertical structure of the trench capacitor comprises two further polysilicon fillings 32 . 33 in addition to the first polysilicon filling 31 in the lower area of the trench capacitor, as well as two oxide collars 21 . 22 of which the top oxide collar 22 has a smaller thickness. As a result, the transition area of the laterally lying opening 24 in the oxide lid 23 of contact 20 to the third polysilicon filling 33 of the storage node 15 advantageously enlarged.

In the following, a manufacturing method is briefly described, which advantageously leads to the DRAM memory cell 101 of the exemplary embodiment of the present invention: First, the steps for forming a trench are carried out, ie annealing a silicon substrate with subsequent oxidation, deposition of a nitride which later serves as an etch stop and a silicate glass as a mask for the trench structuring.

The silicate glass layer is then removed. An arsenic glass layer, for example 70 nm thick, is deposited in the trench, which serves as a doping source for forming the buried plate 71 serves. The height to which the arsenic glass reaches after a further etching step is defined in a coating, exposure and development step.

After the application of a further oxide layer (TEOS) of approximately 50 nm in thickness to protect the arsenic from diffusing outwards, the arsenic glass is annealed and then removed with the oxide layer. An NO layer of 30 nm is now deposited as a dielectric in the still empty trench. A first polysilicon filling follows 31 in a separation step, which is then up to a first height 81 is etched back. The exposed NO above the first height 81 is etched away. So the capacitor plates 71 . 15 and the intermediate dielectric is formed.

Furthermore, the side walls of the trench are oxidized and in a CVD step with a TEOS layer to form an approximately 80 nm thick first oxide collar 21 Mistake. After an annealing step to densify the TEOS layer, the oxide collar is etched back down to the nitride pad. The second polysilicon filling follows 32 , which is first planarized and then to a second height 82 is etched back.

To form a second oxide collar 22 with a third polysilicon filling 33 the steps from the sidewall oxidation and the deposition of a TEOS layer are repeated, with the second oxide collar 22 this time only has a thickness of about 40 nm. The second oxide collar 22 and the third polysilicon fill 33 be up to a third height 83 etched back.

The oxide lid 23 is now formed by deposition and planarization using CMP, so that the trench 1 is initially filled. In a lithographic step, the active areas are then stored as a plurality of memory cells 101 traversing long lines. The originally applied nitride and oxide pad remains in the area of the active areas, while the shallow isolation trenches are formed in the intermediate areas in etching and deposition steps.

In further steps, the gate contacts 2 or word lines 7 . 8th who have favourited Gate Spacers 44 and nitride liner formed, being for the word lines 7 . 8th a further lithography step is necessary. The nitride liner is used to form the contact 20 . 24 only to be allowed in those places where it is opened. This opening is made possible by a separate lithography step. The corresponding liner material is removed in an etching step and the oxide cover in one part 51 the trench opening opened. The resist applied in the lithography step is then removed.

Doping of the exposed surfaces is achieved by a BF ₂ implantation with low energy. The contact 20 . 24 is then produced by a poly-silicon deposition, with an annealing step ensuring the necessary diffusion. Treatment with KOH removes intrinsic polysilicon. The nitride liner is then removed, so that conventional methods can continue with the formation of the contact holes for contacting the source / drain diffusion regions.

1

dig (Grave capacitor)

2

Gate contact

3

Source region, second endowed area

4

Drain region, first endowed area

5

Bit line contact

6

flat Isolation trench, STI

7

First, active wordline

8th

Second, passive word line

9

bit

12

Not isolated area of the substrate

15

storage nodes

20

Contact above substrate surface, Surface strap

21

first Oxide collar

22

second Oxide collar

23

Oxide lid

24

Opening in Oxide lid

31

First Polysilicon filling

32

Second Polysilicon filling

33

third Polysilicon filling

34

third Polysilicon filling for diffusion of the ENLARGE

surrounded contact

41

Gate poly-silicon with gate oxide

42

Tungsten silicide

43

Silicon nitride

44

Silicon oxide spacers

45

Nitride liner

50

buried Contact, buried strap

51

first Part of the trench opening

52

second Part of the trench opening

71

buried Plate, buried plate

81

First Height, bottom edge first oxide collar

82

Second Height, top edge first oxide collar

83

third Height, top edge second oxide collar

100

Memory cell State of the art

101

Memory cell inventively

Claims (6)

Integrated dynamic memory cell ( 101 ) with - a substrate, - a trench capacitor ( 1 ) with a storage node ( 15 ), which has at least a first oxide collar ( 21 ) which encloses the storage node ( 15 ) from the substrate above a doped region buried in the substrate ( 71 ) isolated, - a planar selection transistor with a) a gate ( 2 ), on which a first word line ( 7 ) is connected, b) a first doped region ( 4 ) in the substrate on which a bit line ( 5 ) is connected, c) a second doped region ( 3 ) in the substrate, which is connected to the storage node ( 15 ) in the trench capacitor ( 1 ) by means of a contact ( 20 ) is electrically connected, - the contact ( 20 ), which is formed at least partially above the surface of the substrate so that it covers the second doped region ( 3 ) at least partially covered, characterized in that - the trench capacitor ( 1 ) has a first opening on the substrate surface, which first part ( 51 ) from the contact ( 20 ) and a second part ( 52 ) from a second word line ( 8th ) is covered, - an oxide cover ( 23 ) is arranged in the first opening, - a second opening ( 24 ) in the oxide cover ( 23 ) is formed, which is filled with electrically conductive material, the electrically conductive material with the contact ( 20 ) is connected, - the oxide cover ( 23 ) and the electrically conductive material of the second opening ( 24 ) on a surface of the electrically conductive filling facing the substrate surface ( 31 . 32 . 33 ) of the storage node ( 15 ) are arranged and the first opening of the trench capacitor ( 1 ) complete completely. Memory cell ( 101 ) according to claim 1, characterized in that the storage node ( 15 ) from the at least first oxide collar ( 21 ) and a second oxide collar ( 22 ) is enclosed in a ring-like manner, whereby - the first oxide collar ( 21 ) in a lower area of the storage node above the buried doped area from a first ( 81 ) up to a second height ( 82 ) is arranged and has a first oxide thickness, and - the second oxide collar ( 22 ) in an upper area of the storage node from the second height ( 82 ) up to a third height ( 83 ) is arranged and has a second oxide thickness, - the second oxide thickness is less than the first oxide thickness. Memory cell ( 101 ) according to one of claims 1 to 2, characterized in that the contact ( 20 ) has doped polysilicon. Memory cell ( 101 ) according to one of claims 1 to 3, characterized in that the second word line ( 8th ) in the area where the second part ( 52 ) the first opening of the trench capacitor ( 1 ) crosses, has a first width, and has a second width outside this area, and the second width is greater than the first width. Memory cell according to one of Claims 1 to 4, characterized in that the trench capacitor ( 1 ) has a diameter which is less than the first width of the second word line ( 8th ) is. Process for producing at least a first ( 101 ' ) second ( 101 '' ) and third memory cell ( 101 ''' ) according to one of claims 1 to 5, comprising the steps - providing a substrate, - Forming at least a first, second and third trench in the substrate, - First filling the trenches with a first conductive material ( 31 ) and etching back the first conductive material ( 31 ) up to a first height ( 81 ), - depositing an oxide to form a first oxide collar ( 21 ) in the trenches, - second filling of the trenches with a second conductive material ( 32 ) and then etching back the second conductive material ( 32 ) and the first oxide collar ( 21 ) up to a second height ( 82 ), - deposition of an oxide and subsequent planarization to form an oxide cover closing the trenches ( 23 ), - forming a shallow isolation trench ( 6 ) such that the first, second and third trenches are arranged in a common, contiguous substrate region which is separated from the flat isolation trench ( 6 ) is surrounded, - forming a first and a second word line ( 7 . 8th ) for each of the memory cells ( 101 ' . 101 '' . 10 ''' ), - etching a section of the oxide cover ( 23 ) to form contact openings ( 24 ) to the second conductive material ( 32 ) below the oxide cover ( 23 ), - doping the substrate to form first and second doped regions ( 3 . 4 ), - depositing a conductive material into the contact openings ( 24 ) and on the surface of the second doped regions ( 3 ) to form contacts ( 20 ) between the second endowed areas ( 3 ) and the conductive material ( 32 ) in the trenches.