DE19826388B4 - Error processing circuit for a receiving station of a data transmission system - Google Patents

Abstract

Error processing circuit for a receiving station of a system for transmitting binary data in the form of pulse sequences, wherein:
a. the system has a number of receiving stations connected to a first line (A) and a second line (B) via a dual-line bus;
b. a first logic value of the binary data through a high potential value on the first line (A) and a low potential value on the second line (B) and a second logic value of the binary data through a low potential value on the first line (A) and a high potential value is shown on the second line (B);
c. within each pulse train, not more than a predetermined number of like data bits may follow each other; and
d. the receiving point has:
d.1 a data output (Rx),
d.2 a decoder (CA, CB, CD) with three decoder outputs (ACA, ACB, ACD) of which
d.2.1 a first decoder output assigned to both lines (A, B), one from the difference between the ...

Description

The The invention relates to an error processing circuit for a receiving station a system for transmission binary Data in the form of pulse sequences. The system has a number of receiving stations on that over a dual line bus having a first line and a second line Line are connected. The receiving stations can be parts of network nodes of the Be a data transmission system, who are both capable of sending and receiving. For redundancy purposes become the binary data of the data transmission system simultaneously both over the first line as well over transmit the second line. In this case, a first logic value of the binary data is replaced by a high Potential value on the first line and a low potential value on the second line and becomes a second logic value of the binary data by a low potential value on the first line and a high one Potential value shown on the second line. The protocol of the data transmission system accordingly allowed to within each pulse train or data frame no more than a predetermined number of similar data bits follow one another.

at such a data transmission system it can be a CAN system. The term CAN stands for Controller Area Network. details Information can be found in the book "Controller-Area Network: CAN" by Konrad Etschberger, Carl Hanser Verlag 1994, ISBN no. 3-446-17596-2. Interesting in in particular, the section protocol properties are present context on pages 25 and 26 and data / frame format on the pages 37 to 43.

commitment find such CAN systems, for example in the automotive field.

For the CAN system there is a common supply voltage source, e.g. in shape a motor vehicle battery, for example, a battery voltage of 12V supplies. Furthermore each network node has a network node own, individual operating voltage source, from the supply voltage supplying the respective network node regulated operating voltage generated. Each operating voltage source delivers at a first connection Operating potential, for example, in the amount of 5 V, and at a second Connection Reference potential, for example ground potential or 0 V.

Of the Transmitting part of a network node has two resistors and two controllable electronic switches on that connected to the two wires of the double line bus are. One of these lines is over a first of these resistors with the operating potential (5 V) and a first of these switches connected to the reference potential (0 V). The other line is over the second resistor to the reference potential (0 V) and over the second switch connected to the operating potential (5 V). To the Sending digital messages will synchronize the two switches either in a conducting state or in a non-conducting one State controlled. For non-conducting controlled switches is present one line the operating potential and on the other line the reference potential. This switch state, for example assigned the logic value "1". at On the one line, the reference potential lies on the circuit-controlled switches and at the other line the operating potential. This switch state then the logic value "0" is assigned.

There the transmission parts of all broadcasting Network node regarding the two lines are connected in parallel, can the logic value "0" associated potential ratio the two lines by closing the two switches of a each of the senders Network nodes are generated. On the other hand, the non-conductive state the two switches of each network node through the conductive State of the two switches of another network node dubbed become. Therefore, one calls the logic value of a closed pair of switches is assigned (logic value "0"), dominant and the Logic value associated with a non-conductive pair of switches (Logic value "1"), recessive.

Of the Receiver part of each receiving network node has a Comparator on which the respective potentials on the two lines compared with each other. When a recessive bit is received (logic value "1") it is produced at the output of the comparator For example, a positive potential to which the logic value "1" is assigned. When receiving a dominant bits (logic value "0") is at the output the comparator a potential corresponding to the reference potential, which is then assigned the logic value "0". The comparator thus forms a deco for each of the sent Bit corresponding potential conditions on the two lines.

The two lines are used for redundancy reasons in addition to the system ground. The message information corresponding to the potential value of the respective transmitted bit is transmitted in this way both via the one line and via the other line. If one of the two lines fails, the further transmission mode can be limited to the line that has not failed. To detect line failures, two more comparators are provided, one of which has the potential of one line and the other the potential the other line with a lying between the operating potential and the reference potential center potential compares.

There may be a variety of line failures or line faults, such as short circuits between the two lines, short circuits to the system ground, shorts to the operating potential source, short circuits to the supply voltage source, or open lines. There are line errors that do not hinder secure decoding of the sent messages. There are other line faults that require certain measures to continue to allow for proper decoding. More details can be found in the DE 195 23 031 A1 ,

at a CAN network, the messages in the form of time from each other transmitted spaced pulse trains or frames. The usual CAN protocol provides that between the individual frame a minimum time interval is available and that within a frame can not be consecutive to more than 11 recessive or dominant bits.

From the DE 195 23 031 A It is known for a receiver-side decoder to use the already mentioned three comparators whose output signals by means of an error detection circuit to investigate for the presence of certain line errors and to make the result of this investigation depending, the output of which of the three comparators on one of the Error detection circuit controlled multiplexer to be connected to a data output of the receiving station. If the comparator which compares the potential values of the two lines supplies the potential value of the dominant logic value "0" for a longer period of time than is allowed under the CAN protocol, it is assumed that either the two lines are short-circuited to one another or the first line one Has short circuit to system ground, and is used as a data output that comparator, which compares the potential of the second line with a central potential value. That is to say, as soon as the comparator comparing the potential values of the two lines permanently has the dominant logic value "0" for the duration permitted by the CAN protocol, the potential changes on the second line are used for the decoding of the received data.

Now But there are line faults that are dominant in a permanent Logic value "0" at the output of the Potential values of the two lines of comparative comparator recognizable are, but where no change in potential on the second line occur. Such a case is given when the second Lead a short circuit to net node's own operating voltage source (5 V) out. Also with such a line fault, in the case of the known circuit arrangement on the output of the second line observing potential change Recourse to comparator. And since no potential changes occur there, the data decoding fails.

From the EP 0 529 602 A2 is an error processing circuit is known, by means of which, even when such a line fault nor a decoding of the transmitted data is possible, but with a comparatively complex, complex circuit arrangement. In addition to the three already at the DE 195 23 031 A used comparators needed from the EP 0 529 602 A2 known error processing circuit at least four counters, at least nine logic operation circuits, depending on the embodiment, a flip-flop.

The object of the invention is to remedy this situation and to make an error processing circuit available, by means of which also the occurrence of a line fault of the type mentioned in the penultimate paragraph still data decoding can be maintained, but with a much lower circuit complexity than in the EP 0 529 602 A2 ,

This succeeds with an error processing circuit in the claim 1 specified type, according to claims 2 to 6 can be further developed.

According to claim 7, the invention makes a data transmission system available, its receiving stations with an error processing circuit of inventive type are equipped so that the entire data transmission system is also secured against the mentioned error. According to claim 8 may such a data transmission system Be CAN system.

The present invention provides an error processing circuit for a receiving station of a system for transmitting binary data in the form of pulse trains, the system having a number of receiving stations connected via a dual-line bus to a first line and a second line; a first logic value of the binary data is represented by a high potential value on the first line and a low potential value on the second line and a second logic value of the binary data by a low potential value on the first line and a high potential value on the second line becomes; within each pulse train, not more than a predetermined number of like data bits may follow each other; and the receiving station comprises: a data output, a decoder having three decoder outputs, of which a first decoder output associated with both lines provides a first decoder output signal dependent on the difference between the potential values of both lines, a second decoder output assigned to the first line one of the difference between the potential value a second decoder output signal depending on the first line and a first center potential value and a third decoder output associated with the second line provides a third decoder output signal depending on the difference between the second line potential value and a second center potential value, the first center potential value and the second center potential value each between the high Potential value and the low potential value are in the error-free case and when line faults of a first fault group with a line fault on one of the two Lines at least the first decoder output and the occurrence of a second error group with a line fault on one of the two lines only the error-free other line associated decoder output properly decoded data supplies; a line state detector circuit by means of which in response to the Dekoderausgangssigna len error-free line conditions and line errors of the first line and line errors of the second line detectable and the respective detection result-dependent Umschaltsteuersignale are available; and a controllable switch, by means of which the data output in the detection of line conditions, in which only the second or the third decoder output properly decoded data, is connected to this decoder output and otherwise to the first decoder output. In this case, the line state detector circuit comprises a first logic circuit connecting the first decoder output signal and the second decoder output signal, a second logic circuit supplying the first decoder output signal and the third decoder output signal, a second logic signal supplying the first logic signal, and the second logic signal measuring second time measuring means, by means of which a temporal measurement of logic signal values of the first and second logic signal, which may mean a line fault, carried out and a first and second line error signal is generated when such a logic signal value is longer than one of the predetermined number of equal data bits corresponding time duration continues from its occurrence, and a the two line fault signals linking third logic circuit, which connects the two line error signals to the switching control signal pft.

Also in the error processing circuit according to the invention So it's not just watching if the decoder is related to the comparison of the potential values of the two lines permanently provides the dominant logic value "0" and in this Case on the evaluation only the potential values of the second Switched line, but it will be in the error consideration and error processing always the line conditions of both lines in terms still included potential change. This gives the opportunity with every line fault, in which a comparison of the potential values the two lines no longer allows data decoding at the data decoding really on the one of the two lines to resort to which ones still has potential change.

In the mentioned line fault, in which the second line is shorted to the operating voltage of the considered network node and in which the from the DE 195 23 031 A Known error processing circuit data decoding no longer allowed, because it switches in the data decoding just on this faulty line is also switched in the case of error processing circuit according to the invention for the data decoding on the first line, which still has potential change in this line error.

Since in the case according to the invention, in contrast to the error processing circuit according to EP 0 529 602 A2 for fault detection on the one hand and the choice of which of the three decoder output signals to serve as the decoded signal, each using a separate circuit, namely line state detector circuit on the one hand and the controllable switch to the other, both of which may be comparatively simple circuit arrangements, one arrives in the case of the invention with a fairly simple overall circuit.

In spite of of the simple circuit construction is also in the case of the invention possibility given, the potential value states on the two lines that would be interpreted as a line fault, though within the protocol of the data transmission system in error-free Performance may occur, in time to mask until it is clear from the minutes that it is really must be about line errors.

The first to third logic circuits may each be constructed with a NOR gate, and the fourth logic circuit may be an AND gate having an inverting input and a non-inverting input. The two time measuring devices can each be formed by a counter, which receives it via a counting clock The count clock pulses supplied count as long as it is enabled for counting via a count enable / reset input. A first logic value, for example "1", enables the counter to count and a second logic value, "0" in this example, resets the counter to an initial count state, preferably count 0. Potential value patterns on the two lines, which may occur in the case of line errors, release the counting of the one and / or the other counter and, if they take longer than the time allowed by the protocol of the data transmission system, lead to a potential change at the output of the respective counter. which is evaluated by the third logic circuit with the third NOR gate and the AND gate.

In known per se, the decoder can be constructed with three comparators of which a first compares the potential values of the two lines with each other and the other two the potential value of the first line or the compare the second line with a midpoint value between the high potential value and the low potential value, the with error-free line over transmit the two lines become.

Of the controllable changeover switch can be constructed with a multiplexer, the three entrances each of which is connected to one of the three comparator outputs is one connected to the data output of the receiving station Multiplexerausgang and three Umschaltsteuereingänge owns. From the latter is one with the counter output of the first counter, a second one with the output of the third NOR gate and a third one connected to the output of the AND gate.

Of the Multiplexer and the third logic circuit of the line state detector circuit are constructed and interconnected so that the with the data output the multiplexer output connected to the receiving point with the comparator output of the first comparator, the potential values of both lines compares with each other, always connected when both lines are faultless or if there are such line faults in which the comparator output of the first comparator still potential change provides, from which the transmitted Derive data. Construction and interconnection of multiplexer and third logic circuit are also chosen so that at Line errors in which at the output of the first comparator no Potential change and thus no more logic value changes occur the data output of the receiving point with the comparator output of connected to the second or the third comparator, as the case may be whether at the occurred line error at the comparator output of second or third comparator still potential change and thus Logic value changes appear.

The Invention as well as other objects and advantages of the invention will now be based on embodiments explained in more detail. In show the drawings:

1 an embodiment of a receiving station of a data processing system with a decoder and an error processing circuit according to the invention and a controllable switch;

2 an embodiment of an error processing circuit according to the invention;

3 a schematic representation of a controlled by the error processing circuit switcher; and

4 a table to explain the operation.

In the 1 embodiment shown comprises a dual-line bus with two lines A and B of a CAN system. This system comprises a plurality, for example about 40, network nodes. In 1 Circuit components of only a single network node are shown. The other network nodes are at least partially identical.

Everyone Network node is capable of transmitting and receiving and forms a transmitting station and a receiving station.

The first line A is connected via a first resistor RA to a network node's own operating potential source VK (for example 5 V), while the second line is connected via a second resistor RB to a reference potential source GND (for example 0 V). In addition, the first line A is connected to the reference potential source GND via a first switch SA, and the second line B is connected to the reference potential source VK via a second switch SB. The two switches are both simultaneously controlled to either a conducting state or a non-conducting state by means of a transmit signal source (not shown). In the non-conducting state of the two switches SA and SB is located on line A, the operating potential VK, for example, 5 V, and on the line B, the reference potential, for example, 0 V. This switch and potential state, the term "recessive" and the logic value "1" assigned. In the case of conducting switches SA and SB, the first line A is at the reference potential (0 V) and the second line B is at the operating potential (5 V). This switch and potential state are the term "dominant" and the logic value "0" assigned. In the case of a logic value change of the binary message signal transmitted via the double-line bus, a potential change of 5 V to 0 V or from 0 V to 5 V thus takes place on the two lines. Due to the synchronous control of both switches SA and SB, message pulses on both lines A and B are transmitted concurrently but in the opposite sense in terms of time in terms of amplitude.

The Potentials on the two lines A and B are due to the switching states of both switches SA and SB all involved network node determined. The non-conducting switch state the two switches SA and SB of one or more network nodes can by the conductive switch position of the two switches SA and SB one or more other network nodes are dubbed. For this reason becomes the non-conducting state of the two switches SA and SB of a Network node as recessive and its conductive switch state as dominant.

Of the Receive part of the respective network node comprises a decoder DEC with three Comparators CA, CB and CD.

With a first comparator CD becomes the difference between the potential formed on the line A and the potential on the line B. Assigns line A a higher one Potential as line B up, appears at the output of the comparator CD the logic value "1", otherwise the logic value "0". A recessive state or logic value "1" on the dual-line bus is thus a logic value "1" at the output of the comparator CD assigned while at a dominant state or logic value "0" the double-line bus at the output of the comparator CD a logic value "0" appears. The comparator CD serves therefore as a decoder for the message in the form of the described potentials over the Transfer double-line bus becomes.

One second comparator CA compares the respective potential of the line A with a middle potential in height for example, about 2.5V, which is between the high potential value of 5V and the low potential value of 0V. A third Comparator CB compares the potential of line B with a center potential, which is also about 2.5V, for example.

Find on the line A potential change instead, lead to this accordingly changing logic value changes between "1" and "0" at the output of the comparator CA. Remains the potential of the line A due to a line fault permanently on high potential value (5 V), appears at the output of the comparator CA permanently a logic value "1". Remains the potential value the line A due to a line fault permanently low Potential value of 0 V, appears permanently at the output of the comparator CA. the logic value "0".

At the Output of the comparator CB change between logic values "1" and "0" when both lines are faultless, while at a line B concerned Line fault depending on whether the potential of line B is permanent at high potential value 5 V or at low potential value 0 V. remains, permanently a logic value "0" or "1" appears.

Everyone Network node has its own operating voltage source, which from the entire data transmission system common supply voltage source, for example a motor vehicle battery, is gained as a regulated voltage. The supply voltage source is a system mass, in the case of a motor vehicle in the form of body panel, assigned. In practical embodiments is the reference potential GND of the network node's own operating voltage source usually equal to the system ground potential, namely 0 V. Considering one On-board CAN network, the two lines A and B of the dual-line bus usually along body parts. It can happen that a short circuit of the line A and / or the line B to system mass out, for example due to abrasion of the insulation of the affected line.

It can but also line faults in the form of short circuits to the operating potential occur.

To the already mentioned Protocol, as it applies to CAN networks, for example, are sent messages transmitted in the form of bursts or data frames, which have a prescribed temporal Minimum distance from each other and within which not more as a prescribed number of bits, namely 11 bits, same logic value may succeed each other.

• I: Fehlerfreier Leitungszustand:
• II: Kurzschluß der Leitung A mit der netzknoteneigenen Betriebsspannung (5 V)
• III: Kurzschluß der Leitung A mit Masse (0 V)
• IV: Kurzschluß der Leitung B mit der netzknoteneigenen Betriebsspannung (5 V)
• V: Kurzschluß der Leitung B mit Masse (0 V)
• VI: Kurzschluß der Leitungen A und B miteinander

If line faults are disregarded in which a short circuit to the supply voltage of the overall system is present, in the case of a CAN system for a motor vehicle, that is to say for the battery voltage, the following line states are possible:

• I: faultless line condition:
• II: Short circuit of line A with the network node's own operating voltage (5 V)
• III: Short circuit of line A to ground (0 V)
• IV: Short circuit of line B with the network node's own operating voltage (5 V)
• V: Short circuit of line B to ground (0 V)
• VI: Short circuit of wires A and B with each other

In these six different conduction states, logic values of "1" for recessive bits and "0" for dominant bits of logic value at the outputs of the three comparators CA, CB and CD result in logic value patterns as in 4 are shown. This shows the following:
In the fault-free line state, each of the three comparators CA, CB and CD at its output provides potential changes between "1" and "0" when switching between recessive (abbreviated in the table with r) and dominant (abbreviated in the table with d) to the both lines. In the error states II and V, the comparator outputs of both the comparator CD and the comparator CB and the comparator CA supply logic value changes when changing between r and d. When the errors III and IV occur, only the output of the comparator CB or of the comparator CA supplies a logic value change when changing between r and d, while the comparators CD and CA or CD and CB show no more logic value changes. In the case of the line fault VI, at the output of none of the three comparators, a logic value change occurs at a change between r and d.

These logic value patterns in the table of 4 mean:
In fault-free line state I and in the occurrence of line faults II and V, the comparator CD can be used for the decoding of the received data bits, since in all these three cases, switching between r and d is accompanied by logic value changes at the output of CD. In the case of faults II and V, therefore, there is no need to change over to the line fault-free case I.

This is different when the line faults III and IV occur. In these two fault cases, no more logic value changes take place at the output of the comparator CD, but its output remains permanently at a logic value "0" corresponding to the dominant state. The output of CD can therefore no longer be used for data decoding. Like the table in 4 shows, but in both cases still take place at the output of one of the two comparators CA and CB logic value change, so that in case of error III, the output signal from CB and in case of error IV, the output signal from CA for proper data decoding can be used.

Out This realization has resulted in the teaching according to the invention, in all cases also line fault cases, then for to use the data decoding on the output signal of the comparator CD, when it shows between "1" and "0" when switching between r and d logic value change. In case of line faults in which this is not the case, according to this Doctrine for data decoding on the output signal of that of the recourse to two other comparators CA and CB, the change at between r and d still logic value change between "1" and "0" supplies. This means that in error-free case I and in the presence of line faults II and V, the data decoding based on the output of the comparator CD, in the case of line fault III under evaluation of the output signal of the comparator CB and in case of error IV under evaluation of the output signal of the comparator CA.

in the Error VI leads even this teaching is not possible a data decoding. A data decoding is also in case of error VI enables but with measures, with which the present invention is not concerned.

Logic value patterns at the outputs of the comparators CA, CB and CD, as shown in the table in 4 are shown in connection with the line faults II to V, occur even in error-free lines when no change between r and d occurs over several consecutive data bits, because data bits of the same binary value follow one another. However, as indicative of a line fault, such logic value patterns at the outputs of CA, CB and CD are to be evaluated only if the condition that a logic value change does not take place at the output of one or two of the three comparators lasts longer than the protocol of data transmission system is permitted. If one considers, for example, in the CAN system used in the motor vehicle sector, in which no more than 11 identical data bits are allowed consecutively within a pulse train or a data frame, a line fault should only be assumed if at least one of the three comparators CA, CB and CD a potential change for such a period has not taken place, which corresponds to the duration of more than 11 bits of data. How long this period of time is depends on the bitrate with which the data transfer takes place, which leads to a certain time per data bit. 11 bits of data, for example, require a duration of 1.1 ms at a bit rate of 10 kHz and a duration of 110 μs in the case of a bit rate of 100 kHz. In the case of a CAN protocol and these two bit rates, it is therefore not possible to assume a line fault for logic value patterns at the outputs of CA, CB and CD that correspond to cases II to V if at the output of at least one comparator a logic value change for a longer period of time than 1.1 ms or 110 μs has no longer taken place.

In 1 are outputs ACA, ACD and ACB of the comparators CA, CD and CB connected to inputs of an error processing circuit FVS whose output forms a data output Rx of the considered receiving point.

The error processing circuit FVS includes a line state detector circuit which includes the in 2 1, and a switch in the form of a multiplexer MUX, which is controlled by the line state detector circuit, schematically in FIG 3 is shown and has an output which forms the data output Rx of the considered receiving point.

In the 2 In block diagram form illustrated embodiment of a line state detector circuit has on the input side a first logic circuit L1 in the form of a first NOR gate and a second logic circuit L2 in the form of a second NOR gate. Both NOR elements each have two input terminals and one output terminal. A first input terminal of each of these two NOR gates is connected to the output ACD of the comparator CD, while the second input of the first NOR gate to the output ACA of the comparator CA and the second output of the second NOR gate to the output ACB of the Comparator CB is connected. The line state detector circuit also has two counters Z1 and Z2, each serving as a time measuring device, each having a count clock input ZE1 or ZE2, a count enable / reset input F1 or F2 and a counter output ZA1 or ZA2. In a practical embodiment of the line state detector circuit, the two counters are each enabled by a logic value "1" at the count enable / reset input for counting count clock pulses and by a logic value "0" at the count enable / reset input F1 or F2 to an initial state, preferably count " 0 ", reset. When one of the two counters Z1, Z2 has reached a predetermined count, it outputs a logic value "1" at its counter output ZA1 or ZA2, while in the reset state and before reaching this count value it outputs a logic value "0". The frequency of the clock pulses CLK fed to the two counting clock inputs ZE1 and ZE2 from a clock pulse source (not shown) is selected such that a logic value "1" only appears at the corresponding counter output ZA1 or ZA2 if the logic value "1" appears on the counter Count enable / reset input F1 or F2 has passed a time period which is greater than the time duration of 11 data bits. In this way, the occurrence of a logic value "1" at the count enable / reset input F1 or F2 is masked or inhibited in terms of its breakdown to the corresponding counter output ZA1 or ZA2 time for a duration corresponding to the time duration of 11 data bits. A logic value state "1" at the count enable / reset input F1 or F2 thus becomes effective at the counter output ZA1 or ZA2 only if it lasts longer than permitted by the CAN protocol.

The Output signals at the counter outputs ZA1 and ZA2 are linked by means of a third logic circuit, which a third NOR member L3 and an AND gate L4 comprises wherein the AND gate has an inverting and a non-inverting input having. A first and a second input of the third NOR gate is with counter output ZA1 or the counter output ZA2 connected. The inverting input of the AND gate is with the counter output ZA1 connected while whose non-inverting input is connected to the counter output ZA2.

Of the counter output ZA1 forms a first switching control signal output UA1, the output of the third NOR gate L3 forms a second switching control signal output UA2 and the output of the AND gate L4 form a third switching control signal output UA3 of the line state detector circuit.

The in 3 The multiplexer shown has three multiplexer inputs ME1, ME2 and ME3, which are connected to the outputs ACB, ACD and ACA of the three comparators CB, CD and CA, respectively. In addition, the multiplexer MUX has three switching control inputs UE1, UE2 and UE3, which are connected to the switching control signal outputs UA1, UA2 and UA3, respectively, of the line state detecting circuit.

The Line state detector circuit is designed so that at each Line state only one of the three Umschaltsteuersignalausgänge UA1 to UA3 has a logic value "1", the other two Umschaltsteuersignaleingänge on the other hand the logic value "0". Consequently, the Data output Rx of the considered receiving point in each line state in a defined way with a certain one of the outputs ACB, ACD and ACA of the three comparators CB, CD and CA, respectively.

In the fault-free line state I, the counter outputs ZA1 and ZA2 also remain after a counting enable of the two counters Z1 and Z2 on an output-side logic value "0" which leads to a logic value "1" at the changeover control signal output UA2. In the case of the line states II and V, a logic value "1" also appears at the second changeover control signal output UA2. In the fault-free line state I and in the error states II and V, the data output Rx is thus connected to the output ACD of the first comparator CD, ie the data decoding is based on the output signal of the comparator CD comparing the potential values of the two lines A and B. In the case of the line fault III, a logic value "1" appears at the first switching control signal output UA1, so that the data output Rx from the multiplexer MUX is connected to the output ACB of the comparator CB and the data decoding is connected to the output signal of the potential change sel the line B monitoring comparator CB is supported. In the case of the line fault IV, the logic value "1" appears at the third switching control signal output UA3 so that the data output Rx from the multiplexer MUX is connected to the output ACA of the comparator CA and the data decoding is based on the output of the comparator CA monitoring the line A for potential change monitoring.

consequently will be in all line conditions I to V is a line state or Error processing performed, for switching through the data output Rx to the output of a controls such comparator whose output signal in the existing Line state a secure decoding of the received data bits allows.

in the Contrary to the known error processing circuit it can So in the error processing circuit according to the invention do not come at that one of the line errors II to V, the data decoding to the output signal supported by a comparator which does not allow data decoding because that with this Comparator monitored Line has no potential changes due to the line fault.

Claims (8)

Error processing circuit for a receiving station a system for transmission binary data in the form of pulse trains, wherein: a. the system a number Receiving points has over a dual line bus having a first line (A) and a second one Line (B) are connected; b. a first logical value of the binary data by a high potential value on the first line (A) and a low potential value on the second line (B) and a second Logic value of the binary Data by a low potential value on the first line (A) and a high potential value on the second line (B) becomes; c. within each pulse train no more than one predetermined number of similar data bits may follow each other; and d. the receiving point has: d.1 a data output (Rx), d.2 a decoder (CA, CB, CD) with three decoder outputs (ACA, ACB, ACD) of which D.2.1 a first decoder output assigned to both lines (A, B) from the difference between the potential values of both lines (A, B) dependent provides first decoder output, d.2.2 one of the first Line (A) associated second decoder output on from the difference between the potential value of the first line (A) and a first Mid potential value dependent second decoder output signal d.2.3 and one of the second Third decoder output assigned to line (B) from the difference between the potential value of the second line (B) and a second one Mid potential value dependent third decoder output signal, wherein d.2.4 the first Mid potential value and the second mid potential value between each the high potential value and the low potential value D.2.5 and in the error-free case (I) and when line faults occur a first error group (II, V) with a line error on one the two lines (A, B) at least the first decoder output (ACD) and upon the occurrence of a second error group (III, IV) with a Line fault on one of the two lines (A, B) only the the decoder output (ACA, ACB) provides properly decoded data; d.3 a line state detector circuit (L1-L4, Z1, Z2), by means of which in dependence from the Dekoderausgangssignale error-free line conditions and Line fault of the first line (A) and line fault of the second one Line (B) detectable and depending on the respective detection result switching control signals are available; wherein the line state detector circuit (L1-L4, Z1, Z2) comprises: d.3.1 a first decoder output signal and the second decoder output signal linking, a first logic signal supplying first logic circuit (L1); d.3.2 is the first decoder output signal and the third decoder output signal linking, a second logic signal supplying second logic circuit (L2); d.3.3 one the first Logic signal measuring first time measuring device (Z1) and a the second logic signal measuring second time measuring device (Z2), by means of which a time measurement of logic signal values of the first and second Logic signal, which may mean a line fault, carried out and a first and second line error signal is then generated when such a logic signal value longer than a time corresponding to the predetermined number of equal data bits continues from its occurrence; and d.3.4 one the two line fault signals linking third logic circuit (L3, L4), which the two line error signals linked to the switching control signal; d.4 a controllable Switch (MUX), by means of which the data output (Rx) at the Detection of line conditions, where only the second (ACA) or third (ACB) decoder output provides perfectly decoded data with this decoder output (ACA, ACB) and otherwise connected to the first decoder output (ACD) becomes. The error processing circuit of claim 1, wherein each of the first (L1) and second (L2) logic circuits is provided with a NOR gate having an ers The first input is connected to the first decoder output (ACD) and the second input is connected to the second (ACA) or third (ACB) decoder output. Error processing circuit according to claim 2, wherein which the first (Z1) and the second (Z2) Zeitmeßeinrichtung each with a counter with a count enable / reset input (F1, F2), a count clock input (ZE1, ZE2) and a counter output (ZA1, ZA2) are constructed and their count enable / reset inputs (F1, F2) with the output of the first (L1) or second (L2) logic circuit, their clock inputs (ZE1, ZE2) each with a count clock pulse source (CLK) and their counter outputs (ZA1, ZA2) with a first or second input of the third Logigschaltung (L3) are connected. An error processing circuit according to claim 3, wherein soft a. the third logic circuit (L3, L4) having a third NOR gate (L3), which has a first input, a second input and a Output, and an AND gate (L4) having an inverting input, a non-inverting input and an output constructed is b. the first input of the third NOR gate (L3) and the inverting input of the AND gate (L4) with the counter output (ZA1) of the first counter (Z1) and the second input of the third NOR gate (L3) and the non-inverting one Input of the AND gate (L4) with the counter output (ZA2) of the second counter (Z2) are connected, c. the counter output (ZA1) of the first counter (Z1), the output of the third NOR gate (L3) and the output of the AND gate (L4) a first (UA1), a second (UA2) or a third (UA3) switching control signal output, at which a first, a second and a third Umschaltsteuersignal is removable. An error processing circuit according to claim 4, wherein which the controllable switch (MUX) constructed with a multiplexer is one of the first multiplexer input connected to the first decoder output (ACD) (ME1), a second one connected to the second decoder output (ACA) Multiple input (ME2) and one with the third decoder output (ACB) connected to the third multiplexer input (ME3), one with the Data output (Rx) connected multiplexer output and one with the first switching control signal output (UA1) connected first switching control input (UE1), one connected to the second switching control signal output (UA2) second switching control input (UE2) and one with the third switching control signal output (UA3) connected third switching control input (UE3), wherein the data output (Rx) depending on whether as a switching control signal to be evaluated potential value ("1") at the first (UE1), the second (UE2) or the third (UE3) switching control input occurs with the third (ACB), first (ACD) and second (ACA) comparator outputs, respectively combines. Error processing circuit according to one of claims 1 to 5, in which a. the decoder (CA, CB, CD) with a first Comparator (CD), a second comparator (CA) and a third Comparator (CB) is constructed, b. each having a first comparator input, a second comparator input and a comparator output (ACA, ACB, ACD), wherein: c. the two comparator inputs of the first comparator (CD) with one of the two lines (A, B), the first comparator input of the second comparator (CA) with the first line (A), the second comparator input of the third comparator (CB) with the second line (B) and the second comparator input of the second comparator (CA) and the first comparator input of the third comparator (CB) each with a reference voltage source (Vm), which the corresponding one The middle potential value provides, is connected, and d. the comparator output (ACD) of the first comparator (CD) the first decoder output, the Comparator output (ACA) of the second comparator (CA) the second Decoder output and the comparator output (ACB) of the third comparator (CB) forms the third decoder output. Data transfer system with a double-line bus and a plurality of receiving stations, each one error processing circuit according to one of claims 1 to 6 have. Datenübertraungssystem according to claim 7, as a CAN system and according to the CAN protocol is constructed.