DE68929444T2 - Self-scanning arrangement of light-emitting components - Google Patents

Description

The present invention relates to a self-scanning type light-emitting element array in which light-emitting elements are integrated on a single substrate, and a method of driving the array.

Typical light-emitting elements are an LED (light-emitting diode) and an LD (laser diode).

In the LED, a pn or pin junction of a compound semiconductor (GaAs, GaP, GaAlAs or the like) is formed, and a forward bias is applied to the junction so that carriers are injected into the junction. The LED uses the light emission phenomenon that occurs by carrier recombination.

In the LD, a waveguide is arranged in the LED. When a current exceeding a given limit is supplied, injected electron-hole pairs are amplified and an inverted population state is established. Light generated by two parallel reflecting mirrors using a cleavage surface is returned to an active layer, causing laser oscillation. A laser beam is then emitted from an end face of the waveguide.

Negative resistance elements (light-emitting thyristors, laser thyristors, and the like) are known as a light-emitting element having the same light-emitting mechanism as that of the LED and the LD. In the light-emitting thyristor, a pnpn structure is formed by a compound semiconductor described above, and a thyristor using lithium is put into practical applications.

Figs. 22 and 23 show the basic structure and current-voltage characteristics of the negative resistance element with the light-emitting function (here referred to as a light-emitting thyristor). The structure shown in Fig. 22 is the same as that of a thyristor in which a pnpn structure is formed on an n-type GaAs substrate. Fig. 23 also shows the same s-shaped negative resistance characteristic as that of the thyristor. Not only a two-terminal thyristor shown in Fig. 22 but also a three-terminal thyristor shown in Fig. 24 are known. The gate terminal of the three-terminal thyristor has the function of controlling an ON voltage. The ON voltage is converted into a voltage as the sum of a gate voltage and a diffusion potential. After the thyristor is turned on, the gate voltage is substantially the same as the cathode voltage. When the cathode electrode is grounded, the gate voltage becomes zero volts. As is well known, the cutoff voltage of the light-emitting thyristor is lowered when light is incident on it from the outside.

A waveguide can be formed in the light-emitting thyristor to form a laser thyristor by completely the same principle as that of LD (Tashiro et al., Lecture to the Japan Society of Applied Physics, Autumn 1987, No. 18p-ZG-10).

The light emitting element described above, particularly the LED, is commercially available in a manner that a large number of elements are formed on a compound semiconductor substrate and are cut into pieces and individually packaged. An LED for a contact image sensor and a light source for a printer is commercially available as an LED array in which a plurality of LEDs are arranged on a single chip. A contact image sensor, an LED printer and the like require a scanning function of the light emitting points by these light emitting elements to specify reading or writing points.

However, in order to perform optical scanning using the above-mentioned conventional light-emitting elements, each LED formed in the LED array must be connected to a drive IC by wire bonding or the like and must be driven by the IC. For this reason, when a large number of LEDs are arranged, wire bonding must be performed for portions corresponding in number to the LEDs, and a large number of drive ICs are required, resulting in high cost. Space for arranging the drive ICs must be secured, and it is difficult to achieve a compact array. A pitch between adjacent LEDs is determined depending on the wire bonding technique, and it is difficult to reduce the pitch.

Solid State Electronics, Volume 20, No. 5, (1977), pages 469-472 describe a self-scanning light-emitting array using optical coupling between the elements. The abstract of JP-A-60 201 679 and US-A-3 696 389 describe an array of light-emitting elements.

The invention provides a self-scanning light-emitting array comprising:

an array of light-emitting elements with electrically controllable switch-on thresholds, the array being composed of a plurality of blocks each having a plurality of light-emitting elements,

Coupling means electrically connecting the control electrodes of adjacent blocks of the light-emitting elements so that a block in a threshold-reduced state changes the threshold of a next block so that it enters a threshold-reduced state, the coupling means not serving to interconnect the control electrodes within each block, and

at least two phase clock devices operable to provide clock pulses of a plurality of phases to blocks corresponding to the respective phases so that each clock pulse propagates a turn-on operation and a threshold state in one direction of the array.

The invention also provides an array of self-scanning light-emitting elements comprising:

an array of light-emitting elements, the switch-on threshold levels of which can be electrically controlled,

a coupling element having electrical unidirectionality and connecting the control electrodes together in an element array direction for controlling the threshold levels of the light emitting element that is turned on and changing the threshold level of an adjacent light emitting element that is turned on next, and

driving means connected to the light emitting elements for supplying drive pulses thereto in parallel for transmitting a turn-on operation in the array direction at an interval of clock pulses while a change in the threshold level propagates in an array direction, the driving means being formed of two phases, the light emitting elements belonging to the respective phases being alternately arranged and connected to common drive lines corresponding to the respective phases, and the driving means being arranged such that the light emitting elements are alternately driven in first and second phases in response to two-phase driving pulses in which the trailing edge of one pulse overlaps the leading edge of the next pulse.

The invention will now be described by means of non-limiting embodiments E-1, E-2 and F-1 to F-8 with reference to the accompanying drawings in which:

Fig. 1 is a schematic circuit diagram of a light-emitting element array using light in the embodiment A-1,

Fig. 2 is a schematic sectional view of an array of light-emitting elements using light in an embodiment A-2,

Fig. 3 is a schematic plan view of an array of light-emitting elements using light in an embodiment A-3,

Figs. 4 and 5 are schematic sectional views of the light-emitting element array using light in the embodiment A-3,

Fig. 6 is a schematic sectional view of an array of light-emitting elements using light in an embodiment A-4,

Fig. 7 is a schematic plan view of an array of light emitting elements using light in an embodiment A-5,

Fig. 8 is a schematic sectional view of the array of light emitting elements using light in the embodiment of A-5,

Fig. 9 is a schematic circuit diagram of a light-emitting element arrangement using a potential in an embodiment B-1,

Fig. 10 is a schematic sectional view of a light emitting element array using a potential in an embodiment B-2,

Fig. 11 is a schematic plan view of a light emitting element array using a potential in an embodiment B-3,

Figs. 12 and 13 are schematic sectional views of the light emitting element arrangement using a potential in the embodiment B-3,

Fig. 14 is a schematic plan view of a light emitting element array using a potential in an embodiment B-4,

Fig. 15 is a schematic sectional view of the light-emitting element arrangement using a potential in the embodiment B-4,

Fig. 16 is a schematic circuit diagram illustrating a method of driving a light emitting element array in an embodiment C and a timing diagram showing pulse waveforms,

Fig. 17 is a schematic sectional view of a proximity image sensor in an Application 1,

Fig. 18 is a schematic sectional view of an optical printer in an Application 2,

Fig. 19 is a schematic sectional view of an optical printer head in the Application 2,

Fig. 20 is a schematic plan view of an optical display in application 2,

Fig. 21 is a schematic sectional view showing a structure of a light-emitting thyristor of a double heterostructure,

Fig. 22 is a schematic sectional view showing a structure of a light-emitting thyristor,

Fig. 23 is a graph showing the current-voltage characteristics of the light-emitting thyristor,

Fig. 24 is a schematic sectional view showing a structure of a three-terminal thyristor,

Fig. 25 is a block diagram of an array of light emitting elements in an embodiment D-1,

Fig. 26 is a graph showing the characteristics of the light emitting thyristor,

Fig. 27 is a sectional view of an embodiment D-2,

Fig. 28 is a plan view of the embodiment D-2,

Fig. 29 is a plan view of an embodiment D-3,

Fig. 30 is a sectional view of an embodiment D-3,

Fig. 31 is a plan view of an embodiment D-4,

Fig. 32 is a sectional view of an embodiment D-4,

Fig. 33 is an equivalent circuit diagram of a light-emitting element arrangement in an embodiment E-1,

Fig. 34 is a circuit diagram showing a pn image of the equivalent circuit of the Embodiment E-1,

Fig. 35 is a sectional view of an embodiment E-2,

Fig. 36 is an equivalent circuit diagram of an arrangement of light-emitting elements in an embodiment F-1,

Fig. 37 is a schematic view showing a structure of a light-emitting element array in an embodiment F-2,

Fig. 38 and 39 show a plan view and a sectional view of an arrangement of light-emitting elements in an embodiment F-3,

Fig. 40 is an equivalent circuit diagram of a light-emitting element arrangement in an embodiment F-4,

Fig. 41 is an equivalent circuit diagram of a light-emitting element arrangement in an embodiment F-5,

Fig. 42 and 43 show a plan view and a sectional view of an arrangement of light-emitting elements in an embodiment F-6,

Fig. 44 is an equivalent circuit diagram of a light-emitting element arrangement in an embodiment F-7,

Fig. 45 and 46 show a plan view and a sectional view of an arrangement of light-emitting elements in an embodiment F-8,

Fig. 47 is an equivalent circuit diagram showing an embodiment G-1,

Fig. 48 is a sectional view showing an embodiment G-2,

Fig. 49 is a plan view showing an embodiment G-3,

Fig. 50 and 51 are sectional views showing an embodiment G-3,

Fig. 52 is a schematic view showing a basic structure of the embodiments H

Fig. 53 is an equivalent circuit diagram of an embodiment H-1,

Fig. 54 is a partial plan view of the embodiment H-1,

Fig. 55 is a sectional view of a laser thyristor section of the embodiment H-1,

Fig. 56 is a sectional view of a light deflector portion of the embodiment H-1,

Fig. 57 is a perspective view of the laser thyristor section and the light deflector section,

Fig. 58 is a drive timing diagram of the embodiment H-1,

Fig. 59 is an equivalent circuit diagram of an embodiment H-2,

Fig. 60 is a perspective view showing a structure of a light deflector used in the embodiment H-2,

Fig. 61 is a view showing the principles of an optical scanning system by deflection, and

Fig. 62 is a view showing the principle of an optical scanning system using an array.

Embodiments A

The embodiments A described below use light as an interaction medium between the elements and are therefore not embodiments of the present invention.

(Embodiment A-1)

Fig. 1 is an equivalent circuit diagram of the principle of an embodiment A-1. This diagram shows a case where a most common three-terminal light-emitting thyristor whose light-emitting threshold voltage and current can be controlled from the outside is used as an example of a light-emitting element.

The light-emitting thyristors T(-2) to T(+2) are arranged in a row. Each of the three transfer clock lines (φ1, φ2 and φ3) is connected to the corresponding anode electrodes of every third light-emitting element. A light-emitting thyristor has the characteristics that its turn-on voltage is lowered when it detects light. When light-emitting thyristors are arranged so that light emitted from an ON-turned light-emitting element is incident on another interacting light-emitting element, the turn-on voltage of an element near the ON-turned element or an element arranged to receive sufficient light from the ON-turned element is lowered.

The operation of the equivalent circuit diagram of Fig. 1 is described below. Suppose that a high level pulse voltage is applied to the transmission clock line φ3 and a light emitting thyristor T(0) is turned on. Light LI emitted from the light emitting thyristor T(0) is incident on the light emitting thyristors T(-1) and T(+1), thereby lowering their ON voltages. Since the light emitting thyristors T(-2) and T(+2) are located farther away than the light emitting thyristors T(-1) and T(+1), the incident light is weak and their ON voltages are not lowered as much. In this state, a high level pulse voltage is applied to the next clock line φ1. Since the ON voltage of the light-emitting thyristor T(+1) is reduced by the influence of light compared to that of the light-emitting thyristor T(-2), when the high level voltage of the transfer clock is set to a value between the ON voltages of the light-emitting thyristors T(+1) and T(-2), only the light-emitting thyristor T(+1) is turned on and the light-emitting thyristor T(-2) may remain off. Thus, the light-emitting thyristors T(+1) and T(0) are turned on simultaneously. When a low level voltage is applied to the clock line φ3, the light-emitting thyristor T(0) is turned off and only the light-emitting thyristor T(+1) is turned on. Thus, an ON state has been transferred.

Based on the above-mentioned principle, the high level voltages of the transfer clocks φ1, φ2 and φ3 are set to slightly overlap so that the ON states of the light emitting elements are transferred one after another. More specifically, one light emitting point is transferred sequentially.

According to this embodiment, a self-scanning type light-emitting element arrangement can be realized, which cannot be achieved by the prior art.

(Embodiment A-2)

In the embodiment A-1, an equivalent circuit diagram has been shown and described. In an embodiment A-2, an IC structure of the arrangement of the embodiment A-1 is described below.

Fig. 2 is a schematic view of the structure. A p-type semiconductor layer 23, an n-type semiconductor layer 22 and a p-type semiconductor layer 21 are formed on a grounded n-type GaAs substrate 1. The multilayer structure is patterned into light-emitting elements T(-2) to T(+2) by photolithography or the like and etching. Each electrode 40 has an ohmic contact with the corresponding p-type semiconductor layer 21 and an insulating layer 30 which serves as a protective film for preventing short circuits between an element and wiring and at the same time preventing deterioration of characteristics. The insulating layer 30 is made of a material that allows light having a light emission wavelength of a light-emitting thyristor to pass therethrough.

The p-type semiconductive layer 21 serves as an anode of this thyristor, and the n-type GaAs substrate 1 functions as a cathode. Each of the three transfer clock lines (φ1, φ2, and φ3) is sequentially connected to the anode electrodes 40 of every third light-emitting element.

It is well known that the ON voltage of a light-emitting thyristor is changed depending on the amount of light falling on the element. Therefore, if the light-emitting thyristors are arranged such that light emitted from an ON light-emitting thyristor falls on adjacent light-emitting thyristors, the ON voltages of the light-emitting thyristors adjacent to the ON thyristor are reduced compared to the case where no light is emitted.

In the structure shown in Fig. 2, the insulating layer 30 is formed of a film transparent with respect to a light emission wavelength. When a light-emitting thyristor T(0) is in an ON state, light L0 is emitted upward and light LI is well input to the adjacent elements T(-1) and T(+1), thereby lowering their ON voltages.

The operation of the array of light emitting elements is the same as that of Embodiment A-1.

Based on the above-mentioned principle, the high level voltages of the transfer clocks φ1, φ2 and φ3 are turned on so as to slightly overlap, and the ON states of the light emitting elements are sequentially transferred. More specifically, a light emitting point is sequentially transferred. According to this embodiment, an integrated array of self-scanning type light emitting elements using light coupling, which cannot be achieved by the prior art, can be realized.

(Embodiment A-3)

In this embodiment, a practical structure of the embodiment A-2 will be described.

Fig. 3 is a plan view of this embodiment, and Figs. 4 and 5 are sectional views taken along lines X-X' and Y-Y' in Fig. 3, respectively. Isolation grooves 50 are formed between adjacent light-emitting elements T(-2) to T(+1). Light barriers 61 are partially formed in the isolation grooves 50 so that light from an ON light-emitting element is not caused to be incident on other than the two adjacent elements.

In this embodiment, projections of a panel 60 are used as the light barriers 61. However, other materials may be used or other shapes may be employed. A contact hole C₁ is formed in an upper electrode of each light-emitting element and is electrically connected to an electrode 40. A contact hole C₂ is a through hole to be connected to a corresponding transmission clock line Φ₁, Φ₂ or Φ₃.

The transfer clock line Φ1 is connected to the light emitting elements T(-2) and T(+1), the transfer clock line Φ2 is connected to the light emitting element T(-1), and the transfer clock line Φ3 is connected to the light emitting element T(0).

Fig. 4 is a sectional view taken along a line XX' in Fig. 3. This line is parallel to the direction of the array of the light emitting elements, and Fig. 4 shows a state of the light emitting elements arranged in a row. An insulating film 30 for preventing the short circuit between each light-emitting element and the electrode 40 and an insulating film 31 as an insulating interlayer for preventing a short circuit between the electrode 40 and the transfer clock line are formed to surround the insulating groove 50 so as to be adjacent to the insulating groove 50 of each light-emitting element. These insulating films 30 and 31 are formed of transparent insulating films so as not to affect the light coupling between adjacent elements, or may be formed of insulating films that can properly absorb light so as to be able to adjust light coupling between adjacent elements. Furthermore, an insulating film that properly absorbs light and a transparent insulating film may be stacked to have an appropriate film thickness. With this structure, the light coupling between adjacent elements can be established, and a transfer operation (light scanning operation) can be performed. The film structure of the light-emitting element is the same as that shown in Fig. 21 (described later).

Fig. 5 is a sectional view taken along a line Y-Y' in Fig. 3. This line is perpendicular to the arrangement direction of the light-emitting element array, and Fig. 5 shows a connection state of wires and electrodes. The contact hole C₁ leading to the upper electrode of each light-emitting element is formed in the insulating film 30 and is led out to an outer portion through the electrode 40. The electrode 40 is connected to the transfer clock line φ₃ via the through hole C₂.

A manufacturing process for realizing this embodiment is as follows.

An n-type GaAs layer 24b, an n-type AlGaAs layer 24a, a p-type GaAs layer 23a, an n-type GaAs layer 22a, a p-type AlGaAs layer 21b, and a p-type GaAs layer are sequentially formed and stacked on an n+ -type GaAs substrate 2 by tactical growth. The insulating grooves 50 are formed using a photo-etching technique. Thereafter, an insulating film 30 is formed, and the contact holes C1 are formed therein using the photo-etching technique. A metal electrode layer is then formed by a deposition or sputtering method, and the electrodes 40 are formed using the photo-etching technique. The insulating film 31 is formed, and the through holes C2 are formed using the photo-etching technique. A metal terminal layer is then formed by a deposition or sputtering method, and the transfer clock lines (φ1, φ2 and φ3) are formed by the photoetching technique. With the above-mentioned process, the structure of this embodiment is completed.

Although not described in this embodiment, a transparent protective film may be formed on the transmission clock lines. It is not advantageous that the thickness of the insulating film is too large to deteriorate the light transmittance and increase the amount of the external output light, part or all of the upper insulating film of the light-emitting element may be removed, for example, by photoetching.

According to this embodiment, an integrated array of self-scanning type light-emitting elements can be manufactured.

(Embodiment A-4)

In the embodiments A-2 and A-3, the light-emitting thyristor is adopted as the light-emitting element. However, the present invention is not limited to this, and various other light-emitting elements may be adopted.

In this embodiment, for example, a case where a laser thyristor is used will be described.

Fig. 6 is a sectional view when a laser thyristor is used as a light-emitting element. The light-emitting elements (laser thyristors) T(-1) to T(+1) are formed to have the following structure. An n-type AlGaAs layer 125, a p-type AlGaAs layer 124, an i-type (undoped) GaAs layer 123, an n-type AlGaAs layer 122, and a p-type AlGaAs layer 121 are sequentially stacked on an n-type GaAs substrate 1. The p-type AlGaAs layer 121 and the n-type AlGaAs layer 122 are patterned as shown in Fig. 6. The shape shown in Fig. 6 is the same as that of a conventional stripe type laser diode. The entire width of the p-type AlGaAs layer 121 and the partial width of the n-type AlGaAs layer 122 are 10 µm or less. Other portions are the same as those described in Figs. 2 to 5 above.

In the operation of the laser thyristor, the same operation as in a conventional light-emitting thyristor is performed until a current component supplied to the thyristor reaches a laser oscillation current, and light emitted from a current component below the laser oscillation current is isotropically output. A laser beam is output in a direction perpendicular to the film surface of Fig. 6. Therefore, the laser beam does not contribute to the light coupling between adjacent elements, and light emitted from a current component below the laser oscillation current contributes to the light coupling. Other mechanisms of the transfer operation are the same as those in the embodiment A-2.

(Embodiment A-5)

7 and 8 show an embodiment A-5 which is a practical structure of the embodiment A-4. Fig. 7 is a plan view and Fig. 8 is a sectional view taken along line XX' in Fig. 7. A manufacturing method of the structure shown in Fig. 7 will be briefly described below. An n-type AlGaAs layer 125, a p-type AlGaAs layer 124, an i-type (undoped) GaAs layer 123, an n-type AlGaAs layer 122, a p-type AlGaAs layer 121 and an upper electrode layer 20 are sequentially stacked on an n-type GaAs substrate 1 (a p-type GaAs layer for improving ohmic contact may be formed between the p-type AlGaAs layer 121 and the upper electrode layer 20). The upper electrode layer 20 is patterned into a rectangular shape having the same width as that of the n-type AlGaAs layer 125 in Fig. 8. Using the electrode pattern 20 as a mask, the p-type AlGaAs layer 121 to the n-type AlGaAs layer 125 is etched. In this case, the element isolation grooves 50 are formed. The upper electrode pattern 20 is further etched into a stripe shape having a width of 10 µm or less. Using the new electrode pattern 20 as a mask, the p-type AlGaAs layer 121 and the n-type AlGaAs layer 122 are etched. The n-type AlGaAs layer 122 is not completely removed but is partially peeled off. An insulating film 30 is formed on the resulting structure, and through holes C₂ are formed by photoetching. Thereafter, a metal terminal layer for the transfer clock lines is formed by deposition or sputtering, and the transfer clock lines (φ₁, φ₂ and φ₃) are formed by photoetching. Finally, the end faces of an output side of the laser beam are formed by cleavage or the like to have good parallelism, thereby completing the structure of this embodiment.

In a conventional integrated array of light emitting elements, the pn junction diodes are independently formed on a single substrate, are individually externally led using a wire bonding technique, and are driven by applying a voltage through drive ICs. Thus, assembly such as a wiring bonding process is cumbersome, resulting in high cost. In contrast, in a light emitting element array according to this embodiment, only three transfer clock terminals need to be externally led, and assembly is remarkably simplified. At the same time, the space for the drive ICs can be omitted, and a compact array of self-scanning light emitting elements can be produced as a whole. In a conventional array, the alignment pitch of the light emitting elements is predetermined depending on the bonding technique. However, the above-mentioned embodiments A-1 to A-5 are free from such a limitation, and a light emitting element array with a smaller pitch can be manufactured. Thus, an application to a device with a very high resolution can be achieved.

In the embodiments A-1 to A-5, it is assumed that the transfer clock pulses have three phases, i.e., φ1, φ2 and φ3. The number of phases may be increased to four or five to achieve a more stable transfer operation. A larger amount of light emitted from a light-emitting thyristor T(0) is caused to impinge on a light-emitting thyristor T(+1) than on a light-emitting thyristor T(-1) so that the elements can be controlled by two-phase clocks. For example, the light-emitting thyristors are arranged in a plane asymmetric pattern so that a larger amount of light is emitted to the right in the arrangement.

In the above embodiment, the simplest structure of the light-emitting thyristor has been described. The scope of the present invention includes the adoption of a more complex structure and a multilayer structure to increase the light emission efficiency. This also applies to many embodiments described later. For example, a double heterostructure may be employed. Fig. 21 shows an example of a double heterostructure (Tashiro et al. Lecture to the Japan Society of Applied Physics, Spring, 1987, No. 28p-ZE-8). In this structure, an n-type GaAs layer 24b (with a thickness of 0.5 µm) is formed on an n-type GaAs substrate 1. An n-type AlGaAs layer 24a (1 µm) with a wide band gap, a p-type GaAs layer 23a (5 nm), an n-type GaAs layer 22a (1 µm), a p-type AlGaAs layer 21b (1 µm) with a wide band gap, and a p-type GaAs layer 21a (0.15 µm) for making an ohmic contact with a lead electrode are sequentially stacked on the GaAs layer 24b. A light-emitting layer is the n-type GaAs layer 22a (1 µm) sandwiched between the layers 23a and 21b. Injected electrons and holes are trapped in the GaAs layer 22a with a narrow band gap and recombine in this region to emit light.

The light-emitting element does not always have to be a light-emitting thyristor and in particular, it is not limited if its turn-on voltage is changed by light. For example, the laser thyristor mentioned above can be used.

In the above embodiment, a pnpn thyristor structure was exemplified. A structure whose threshold voltage is lowered by light and which is caused to perform a transfer operation by using this function is not limited to the pnpn structure or any other specific structure if it can achieve the above function. For example, if a multilayer structure of six layers or more is used instead of a four-layer pnpn structure, the same effect can be expected and the same self-sensing function can be achieved. Furthermore, the same effect can be achieved if another type of thyristor, such as a static induction thyristor (SI) or a field-controlled thyristor (FCT), is used. The SI thyristor or FCT has a structure in which a central p-type semiconductor layer, which serves as a current block, is replaced by a depletion layer (S. M. Sze, Physics of Semiconductor Devices, 2nd edition, pages 238-240).

In embodiments A-1 to A-5, the light-emitting elements are arranged in a row, but they do not have to be arranged along a straight row. For example, the elements may be arranged in a zigzag manner depending on the applications. The elements may be arranged in two rows away from the center.

According to the present invention, the light-emitting elements may be formed by individual parts or may be integrated by any means.

Embodiment B

The embodiments B described here use a potential as an interaction medium. They do not form part of the invention and are only illustrative.

(Embodiment B-1)

The embodiments A-1 to A-5 shown in Figs. 1 to 8 use the coupling by means of light. This embodiment uses the coupling by means of a potential.

Fig. 9 is an equivalent circuit diagram of an embodiment B-1 of the present invention. The characteristic feature of this embodiment is that a resistance network is added to the arrangement of the embodiment A-1, i.e., Fig. 1.

As the light-emitting elements, the light-emitting thyristors T(-2) to T(+2) are used. The light-emitting thyristors T(-2) to T(+2) have gate electrodes G-2 and G+2, respectively. A power source voltage VGK is applied to each gate electrode through a corresponding load resistor RL. The gate electrodes G-2 to G+2 are electrically connected to each other through resistors RI to achieve interaction. Each of the three transfer clock lines φ1, φ2 and φ3 is sequentially connected to the anode electrodes of every third light-emitting element.

The function is described below. Suppose that the transfer clock φ3 goes to H level and the light emitting element T(0) is turned on. In this case, a potential at the gate electrode G0 is reduced to about 0 V due to the characteristic of the three-terminal thyristor (about 1 V for a silicon thyristor). Suppose that the power source voltage VGK is 5 V, the gate voltage of each light emitting thyristor is determined by the network of the load resistors RL and the resistors RI. A gate voltage of an element located closest to the light emitting element T(0) is reduced by the largest amount, and a gate voltage is increased when an element is disconnected from T(0). This can be expressed as follows:

VG0 < VG1 = VG-1 < VG2 = VG-2 (1)

A difference between these voltages can be set by appropriately selecting the values of the load resistors RL and the resistors RI.

As is well known, a turn-on voltage VON in the anode side of the three-terminal thyristor is higher than a gate voltage VG by a diffusion voltage Vdf.

VON = VG + Vdf (2)

Therefore, when a voltage applied to the anode is set to be higher than the turn-on voltage VON, the corresponding light-emitting thyristor is turned on.

In a state where the thyristor T(0) is turned on, an H-level voltage VH is applied to the next transfer clock pulse φ1. The clock pulse φ1 is simultaneously applied to the light-emitting elements T(+1) and T(-2). If the value of the H-level voltage VH is set to fall within the following range, only the light-emitting element T(+1) can be turned on.

VG-2 + Vdf > VH > VG+1 + Vdf (3)

Thus, both the light emitting element T(0) and T(+1) are turned on. When the H-level voltage VH of the clock pulse φ3 is deactivated, the light emitting element T(0) is turned off and an ON state can be transmitted.

In this way, the gate electrodes of the light-emitting thyristors are connected via the resistor network, thus providing a transfer function to the light-emitting elements.

With the above-mentioned principle, the H-level voltages VH of the transfer clock lines Φ1, Φ2, and Φ3 are set to slightly overlap sequentially, so that the ON states of the light-emitting elements are sequentially transferred. More specifically, a light-emitting point is sequentially transferred. According to this embodiment, a self-scanning type light-emitting element array, which cannot be achieved by a prior art technique, can be realized.

(Embodiment B-2)

In Embodiment B-1, an equivalent circuit has been described by way of example. In Embodiment B-2, an IC structure of the arrangement of Embodiment B-1 is described.

Fig. 10 shows a structure of this embodiment. An n-type semiconductor layer 24, a p-type semiconductor layer 23, an n-type semiconductor layer 22 and a p-type semiconductor layer 21 are sequentially formed on a grounded n-type GaAs substrate 1. Isolation grooves 50 for isolating the multilayered structure in light emitting elements T(-1) to T(+1) are formed by, for example, photolithography or the like and etching. Each anode electrode 40 has an ohmic contact with the p-type semiconductor layer 21, and each gate electrode 41 has an ohmic contact with the n-type semiconductor layer 22. An insulating layer 30 prevents the short circuit between the elements and the terminal layers and also serves as a protective film for preventing the deterioration of the characteristics. The insulating layer 30 is preferably made of a material that allows light having a light emission wavelength of a light-emitting thyristor to pass through well. The n-type GaAs substrate 1 serves as a cathode of each thyristor. Three transfer clock lines φ1, φ2 and φ3 are connected to the anode electrodes of the light-emitting elements. The gate electrodes are connected to the resistance network via the load resistors RL and interaction resistors RI.

When the light coupling described in the embodiment A occurs, it affects the transfer operation of this embodiment. The gate electrodes 41 are partially formed in the isolation grooves 50 between the light-emitting elements to provide a structure for preventing light coupling.

The structure of this embodiment is the same as the equivalent circuit shown in the embodiment B-1 (Fig. 9) and performs the same operation. Therefore, when the H pulse voltages of the transfer clock lines φ1, φ2 and φ3 are set to slightly overlap each other, an ON state of light emitting thyristors is sequentially transferred. More specifically, a light emission point is sequentially transferred.

(Embodiment 8-3)

Figs. 11, 12 and 13 show an embodiment B-3. This embodiment represents an actual structure of the embodiment B-2. Fig. 11 is a plan view of this embodiment, and Figs. 12 and 13 are sectional views taken along lines X-X' and Y-Y' in Fig. 11, respectively.

The light-emitting elements T(-1) to T(+1), the isolation grooves of the light-emitting elements, and a field layer 60 and the like are the same as those in the embodiment A-3. A two-dimensional resistor 63 forms a resistance network connecting the gate electrodes. Light emitted from the light-emitting elements is prevented from being input into the resistor 63 by light-absorbing blocks 62. In this embodiment, a portion of the field layer 60 is used as an optical barrier. However, other materials may be used or another shape may be adopted. An upper electrode of each light-emitting element is guided via a guide via hole C₁ using an electrode layer 40. A clock line Φ₁ is connected to the light-emitting elements T(-2) and T(+1), a clock line Φ₂ is connected to the light-emitting elements T(-2) and T(+1), and a clock line Φ₂ is connected to the gate electrodes. is connected to the light-emitting element T(-1) and a clock line φ3 is connected to the light-emitting element T(0). The resistor 63 is externally led using each contact hole C3 and is connected to a gate electrode 41 of each element. The other end portion of the resistor 63 is connected to a power source line 42 for supplying a voltage VGK through the contact hole C3.

Fig. 12 is a sectional view taken along line XX' in Fig. 11. This line extends along an arrangement direction of the light-emitting element array, and Fig. 12 shows an arranged state of the light-emitting elements. Short-circuit prevention insulating films 30 for preventing the short circuit between the light-emitting elements and the electrodes 40 and 41, insulating films 31 as insulating interlayers for preventing short circuits between the electrodes 50 and the transfer clock lines and the like formed in the insulating grooves 50 of the light-emitting elements are the same as those in the embodiment A-3. These insulating films 30 and 31 must be transparent insulating films so that light can be efficiently output to an external portion. In this case, as described above, in order to prevent the transfer operation from being influenced by light coupling, the gate electrodes 41 may be advantageously formed in the insulating grooves 50 to shield light.

Fig. 13 is a sectional view taken along the line Y-Y' in Fig. 11. This line extends perpendicular to the arrangement direction of the light-emitting element array, and Fig. 13 shows a connection state of the wiring and the electrodes. The light-emitting element terminal contact holes C₁ for the upper electrodes are formed in the insulating films 30 and are externally routed using the electrode layers 40. Each electrode layer 40 is connected to the transfer clock line φ₃ via a through hole C₂ on the field layer 60. As the resistor 63 for the resistor network, an n-type GaAs layer 22a of an n-type semiconductor layer is used in this embodiment. This layer may be another layer and another type of film may be formed by, for example, sputtering without using a semiconductor layer.

Each gate electrode 41 is formed to extend into the insulation groove 50 such that light emitted from the light-emitting element does not affect the resistance of the resistor 63.

The following manufacturing process for realizing this embodiment can be used.

An n-type GaAs layer 24b, an n-type AlGaAs layer 24a, a p-type GaAs layer 23a, an n-type GaAs layer 22a, a p-type AlGaAs layer 21b, and a p-type GaAs layer 21a are sequentially grown on an n+ -type GaAs substrate 21 by an epitaxial growth method. Isolation grooves 50 are then formed by photoetching. Portions of the light-emitting elements and the p-type GaAs layer 21a and the p-type AlGaAs layer 21b in the resistor portion are removed by photoetching using another mask. Thereafter, an insulating film 30 is formed, and contact holes C1 are formed by photoetching. A metal electrode layer is formed by deposition or sputtering, and the electrodes 40 and 41 are then formed by photoetching. Further, an insulating film 31 is formed and through holes C2 are formed by photoetching. A metal terminal layer is then formed by deposition or sputtering, and the transfer clock lines φ1, φ2 and φ3 are formed by photoetching. With the above process, the structure of this embodiment is completed.

Although not expressly described in this embodiment, a transparent protective film may be formed on the transfer clock lines. If it is not advantageous that the thickness of the insulating film is too large to deteriorate the light transmittance and reduce the amount of light output to the outside, part or all of the upper insulating film of the light-emitting element may be removed by, for example, photoetching.

According to this embodiment, a self-scanning type light-emitting element array can be manufactured.

(Embodiment B-4)

In the embodiments B-2 and B-3, the light emitting thyristor is adopted as the light emitting element. In this embodiment, a case where a laser thyristor is used will be described below.

Fig. 14 shows an embodiment B-4. Fig. 14 is a plan view and Fig. 15 is a sectional view taken along a line X-X' in Fig. 14.

The reference numerals such as T(-1) to T(+1) of the light-emitting elements (laser thyristors) and the like are the same as those in the above embodiment.

A manufacturing method of Fig. 14 is described below. An n-type AlGaAs layer 125, a p-type AlGaAs layer 124, an i-type (undoped) GaAs layer 123, an n-type AlGaAs layer 122, a p-type AlGaAs layer 121, and an upper electrode layer 20 are sequentially stacked on an n-type GaAs substrate 1 (a p-type GaAs layer for improving ohmic contact may be formed between the p-type AlGaAs layer 121 and the upper electrode layer 20). The upper electrode layer 20 is patterned into a rectangular shape having the same width as that of the n-type AlGaAs layer 125 in Fig. 15. Using the electrode pattern 20 as a mask, the p-type AlGaAs layer 121 to the n-type AlGaAs layer 125 are etched to form element isolation grooves 50. The upper electrode pattern 20 is further etched into a stripe shape having a width of 10 µm or less. Using the new electrode pattern 20 as a mask, the p-type AlGaAs layer 121 and the n-type AlGaAs layer 122 are etched. The n-type AlGaAs layer 122 is not completely removed but partially remains. The isolation films 30c, 30b and 30a are then formed on the resulting structure. Note that the three insulating films include the insulating films 30c and 30a and the light-shielding film 30b, so that two functions, i.e., the insulating and the light-shielding functions, are provided. When a SiO₂ film is used as the insulating film, it allows a light component having a light emission wavelength of 870 nm from GaAs to pass through it, it can induce light coupling. Thus, the light-shielding film 30b formed of a light-absorbing material, e.g., amorphous silicon, must be formed between the insulating films. Of course, when a material having both having both the insulating and light-shielding functions is used, only one layer may be formed. Contact holes C₁ are formed by photoetching, and a resistor 63 is formed thereon and is photoetched. An insulating film 31 as an insulating interlayer is formed on the resulting structure, and through holes C₂ are formed by photoetching. In this case, the through holes on the resistor 63 can be formed only through the insulating film 31. However, the through holes on the upper electrode 20 must be carefully formed because the insulating films 31, 30c, 30b and 30a must be removed simultaneously. A metallic conductor layer for the transfer clock lines is then formed by deposition or sputtering, and the transfer clock lines φ₁, φ₂ and φ₃ and a power source line VGK are formed by photoetching. Finally, the end face of a laser beam output side is formed by cleavage or the like to have good parallelism, thereby completing the structure of this embodiment.

The light-emitting element arrays in Embodiments B-1 to B-4 have a self-scanning function as in Embodiments A, which cannot be achieved by a conventional light-emitting element array, and which provides the effects of efficient assembly, compactness, reduction in pitch, and the like.

In the embodiments B-1 to B-4, it is assumed that the transfer clock pulses have three phases, i.e., φ1, φ2 and φ3. The number of phases may be increased to four or five to achieve a more stable transfer function.

In the above embodiments, the light-emitting elements are arranged in a row. However, the elements need not be arranged in a row, but may be arranged in a zigzag manner depending on the applications. The elements may be arranged in two rows away from the center line.

The light-emitting element does not have to be a light-emitting thyristor. The present invention is not particularly limited to any element as long as the turn-on voltage of a light-emitting element is changed by an external potential. The light-emitting element may be a laser thyristor as described above.

According to the present invention, the light-emitting elements may be formed by individual parts or may be integrated by any means.

The structure of the light-emitting thyristor is not particularly limited. For example, a more complex structure and a multilayer structure can be adopted, and an arbitrary structure formed of six or more layers can be adopted as described in Embodiments A.

In the series of embodiments A and B of the present invention, a semiconductor substrate is used as a substrate and its potential is set to 0 V (ground potential) However, the present invention is not limited to this. Other materials may be used for the substrate. For example, an n-type GaAs layer corresponding to the n-type GaAs substrate 1 of this embodiment is formed on a Cr-doped semi-insulating GaAs substrate, and the structure described in the above embodiments may be formed thereon. Alternatively, a semiconductor film is formed on an insulating substrate made of, for example, glass, alumina or the like, and the structure of this embodiment may be formed using this semiconductor.

The structure of the laser is not limited to that described in the above embodiments. For example, a TJS type, a BH type, a CSP type, a VSIS type, and the like can be used (S. M. Sze, Physics of Semiconductor Devices, 2nd edition, pp. 724-730). As the material, AlGaAs has been mainly described. However, other materials can be used (e.g., AlGaInP, InGaAsP, ZnSe, GaP, and the like).

In embodiments A and B, an ON light-emitting element has a main influence on adjacent light-emitting elements, and the adjacent light-emitting elements become light-emitting elements that are driven next. However, the present invention is not limited to this. For example, an ON element may influence every other element so that an ON state may be transmitted to every other element.

The various modifications described above can be applied to the following numerous embodiments.

Embodiment C

An embodiment C described below relates to a driving method of the light-emitting element arrays produced by the embodiments A and B described above, which also does not form part of the invention.

(Embodiment C-1) Operating method of light-emitting element array

Fig. 16 is a view for explaining an embodiment C-1. Fig. 16 shows an equivalent circuit showing a driving principle and pulse waveforms applied to the terminals.

In this embodiment, the current sources I₁, I₂, and I₃ are arranged in parallel with transfer clock pulses Φ₁, Φ₂, and Φ₃, and a current amount IT is controlled by a light emission signal ΦI.

A function is described below. A light-emitting element T(0) is turned on in response to a start pulse ΦS. When the transfer pulses Φ1, Φ2 and Φ3 are applied sequentially, an ON state is transferred. This mechanism has already been described in embodiments A and B.

Suppose that a light emitting element T(3) is caused to emit light with a higher intensity, the light emission signal φI is synchronously set to a high level when a light emission point has reached the position of the element T(3). In synchronism with the signal φI, currents flow from the current sources I₁, I₂ and I₃. The anode of the ON element T(3) can draw current from the current sources. Since other light emitting elements are in an OFF state, they cannot draw the currents, and the currents flowing into these elements flow out to a driver which generates the transfer clock pulses. Therefore, the anode current of the ON light emitting element is increased, and the light emission intensity is also increased.

Fig. 16 also shows a waveform of the light emission intensity L. As is obvious from this waveform, the light emission intensity of the light emitting element T(3) is increased compared with other light emission intensities obtained when no currents flow from the power sources. When this driving method is used, the light emission intensity at an arbitrary position can be increased and an optical location writing function can be performed.

When laser thyristors are used as light-emitting elements of this embodiment, if the anode current of the transfer clock is set to be a threshold current of laser oscillation, no laser beam is emitted in a normal transfer state, and a laser beam can be emitted only when a light emission signal is input.

Applications

Applications described below relate to an application of the light emitting element arrangements in Embodiments A and B and the driving method described in Embodiment C.

(Application 1) Application to contact type image sensors

Fig. 17 shows the principle of a contact type image sensor as a first application of the present invention. In this application, a function of moving a light emission point can be realized by the present invention and is applied to position sensing.

In Fig. 17, an amorphous silicon photosensor is formed on a glass substrate. In a conventional sensor, the photosensor is divided into 100 µm pixels, and these pixels are sampled by reader ICs to extract the outputs. The illumination is uniformly performed by LEDs. In a method described here, the amorphous silicon photosensor is not divided into pixels, but the illumination is sampled.

In Fig. 17, an electrode A2 acting as a light shielding layer, an amorphous silicon layer A3, a transparent electrode A4 and an electrode A5 are formed on a glass substrate A1. This structure utilizes the phenomenon that the resistances of the electrodes A2 and A5 with incidence of light, since the electrical conductivity of the amorphous silicon layer A3 is increased by light. A transparent protective layer A6 is formed on this structure, and a document A7 is brought into contact with the layer A6. A light emitting element array A10 of this embodiment is arranged on a side opposite to the document A7 with respect to the glass substrate A1. A scanning beam A11 from the array A10 passes through an array of rod lenses A9, then passes through a window A8 formed at the central portion of the photosensor for beam insertion, and is then focused on the document A7.

The array of light emitting elements A10 has the function of sequentially shifting a light emission point according to the present invention. Thus, a focal point on the document is sequentially shifted accordingly. When the color tone changes due to the presence of a character on the document A7, the reflection rays A12 from the document change accordingly. Changes in the ray intensity are read by the photosensor of the amorphous silicon layer A3.

When the light-emitting element array includes laser thyristors, a light-emitting element array with a large amount of light can be obtained due to their high quantization efficiency, thereby saving power consumption and allowing high-speed reading.

In this manner, the array of light emitting elements according to the present invention can be applied to reading characters or an image of a document or the like, and a wide range of application for a facsimile system, a bar code reader, a copier and the like can be expected.

(Application 2) Application in optical printers and displays

As a second application of the present invention, an application to an optical printer will be described below. Conventionally, an application to an optical printer using a module in which a drive IC is connected to each pixel of an LED array is known. Fig. 18 shows the principle of an optical printer. A layer of a material such as amorphous silicon having an optical conductivity (photosensitive body) is formed on the surface of a photosensitive cylindrical roller B1. The roller B1 is rotated in the direction of arrow a at a printing speed. The surface of the photosensitive body is uniformly charged by a charger B7. An optical print head having a light emitting element array B8 irradiates an optical dot image to be printed onto the photosensitive body to neutralize a charge of a portion irradiated with a light beam. The toner is attracted in accordance with the charged state on the photosensitive body by a developing unit B10. The toner image is transferred to a paper sheet B9 fed from a cassette B11 via a transfer unit B2. The toner image on the Paper sheet B9 is heated by a fixing unit B3 and is fixed thereon. The sheet B9 is then transferred to a stacker B4. The charge on the roller which completes the transfer is neutralized over the entire surface by a discharge lamp B5, and the remaining toner is removed by a cleaner B6.

The light emitting element array according to the present invention is driven by the driving method described in the embodiment C-1 and is applied to the optical print head having a light emitting element array B8. Fig. 19 shows the structure of the optical print head B8. The head B8 is constituted by a light emitting element array B12 and a rod lens array B13 so that a focal point of the lenses is formed on the photosensitive drum B1. When the driving method described in the embodiment C-1 is used, a light emission intensity can be increased at a position where an optical writing operation is to be performed while transmitting an ON state in the light emitting element array of the present invention. Therefore, image data can be written on the photosensitive drum.

When the light-emitting element array includes laser thyristors, a light-emitting element array with a large amount of light can be achieved due to their high quantization efficiency, thereby saving power consumption, or allowing high-speed writing access, i.e., printing.

Thus, the present invention can be applied to the optical printer.

The light-emitting element array for the optical printer has a linear arrangement. When the arrays are arranged two-dimensionally, a display can be prepared. This structure is shown in Fig. 20. When N light-emitting element arrays B14 are arranged, a signal from ΦI (1) to ΦI (N) can be written. When an integrated light-emitting element array is used, a high-density display element can be produced. When independent light-emitting elements are combined, a large-area display can be produced.

Embodiments D

The embodiments D described here may simplify a structure of the light-emitting element array in the embodiments B described above, and do not form part of the invention.

(Embodiment D-1)

Fig. 25 is an equivalent circuit diagram showing the principle of an embodiment D-1. In this embodiment, a three-terminal light-emitting thyristor whose light-emitting threshold voltage and current can be externally controlled is used as a light-emitting element. The light-emitting thyristors T(-2) to T(+2) are aligned in a series. Each light-emitting thyristor is represented as a combination of the transistor Tr1 and Tr2. The transistor Tr1 is a pnp transistor, and the transistor Tr2 is an npn transistor. Each connection resistor RL between adjacent light-emitting thyristors is connected between the base terminals of the adjacent npn transistors Tr2. Each of the three transfer clock lines φ1, φ2 and φ3 is repeatedly sequentially connected to the anode electrodes of every third light-emitting thyristor. A resistor Re for regulating a current of the clock line is provided on each clock line.

The operation is described below. Suppose that a transfer clock φ3 goes to an H level and a light-emitting thyristor T(0) is turned on. In this case, the base of the npn transistor Tr2(0) is set to a potential capable of allowing an ON current of the light-emitting thyristor T(0) to flow. This potential is transmitted to the base terminals of the npn transistors Tr2(-1) and Tr2(1) of the adjacent light-emitting thyristors T(-1) and T(1) through the corresponding connection resistors RL, and their base currents flow. As long as the transfer clock lines φ1 and φ2 are set to the low level, the light-emitting thyristors T(-1) and T(1) are kept turned off. When the resistance of the connection resistor RL is low, the npn transistors Tr2(-1) and Tr2(1) have performances capable of flowing the same current as the ON current of the light-emitting thyristor T(0). However, when the resistance of the connection resistor RL is high, the base currents of the npn transistors Tr2(-1) and Tr2(1) are regulated by the connection resistors RL, and the current driving performances of the npn transistors Tr2(-1) and Tr2(1) are lowered. The base currents of the npn transistors Tr2(-2) and Tr2(2) which are farther away than the npn transistors Tr2(-1) and Tr2(1) are further lowered, and their current driving performances are lowered more.

As is well known, when the base current amount of the npn transistor Tr2, i.e., the current drive power, is increased, the ON voltage of the light-emitting thyristor is lowered. Fig. 26 shows this state. The anode voltage (emitter voltage of the pnp transistor Tr1) is plotted along the abscissa, and the anode current is plotted along the ordinate. In Fig. 26, the ON voltage VS is free from an external influence. An ON voltage VS(1) represents an ON voltage of the light-emitting thyristor T(1), and an ON voltage VS(-2) represents an ON voltage of the light-emitting thyristor T(-2). A minimum voltage necessary for maintaining an ON state is called a holding voltage Vh. The ON voltages of the light-emitting thyristors T(-1) and T(1) which are closest to the ON light-emitting thyristor T(0) are lowered for the reasons mentioned above and reach the ON voltage VS(1). The ON voltages of the next light-emitting thyristors T(-2) and T(2) become the ON voltage VS(2) because the influence of the base current is small.

In Fig. 25, a clock pulse φ1 is applied to the light emitting thyristors T(1) and T(-2) in addition to the clock pulse φ3. Since their ON voltages are the ON voltages VS(1) and VS(-2) from For the reasons mentioned above, if the high level voltage of the clock pulse is set to be a value between the ON voltages VS(1) and VS(-2), only the light emitting thyristor T(1) can be turned on. If the clock pulses φ1, φ2 and φ3 are set so that their high level intervals overlap, the ON light emitting element is sequentially transferred. Thus, a light emitting element array capable of scanning itself can be realized.

As described above, according to the present invention, only one resistor connecting adjacent light-emitting elements is required, and the light-emitting element array can be formed by a simple manufacturing process.

In this embodiment, three-phase transmission clock pulses are used. The light-emitting element array of this embodiment can be driven by clock pulses having four or more phases.

(Embodiment D-2)

In the embodiment D-1, the equivalent circuit has been described. In an embodiment D-2, the IC structure of the device in the embodiment D-1 is described. The essence of this embodiment lies in a structure in which a connection resistor for performing an electrical connection is formed by using a portion of a light emitting element, so that a resistance element can also be formed by the same process as the light emitting thyristor.

Fig. 27 is a sectional view of the structure of this embodiment. An n-type semiconductor layer 24, a p-type semiconductor layer 23, an n-type semiconductor layer 22 and a p-type semiconductor layer 21 are formed on a grounded n-type GaAs substrate 1. Isolation grooves 50 for separating the above structure into individual light-emitting elements T(-2) to T(2) are formed by photolithography or the like and etching.

The n-type GaAs substrate 1 serves as the cathode of each thyristor. Each of the transfer clock lines φ1, φ2 and φ3 is connected to every other p-type semiconductor layer 21 serving as the anodes of the light-emitting elements. The characteristic feature of this structure is that the p-type semiconductor layer 23 constituting the thyristors is connected through the elements. The internal resistance of the p-type semiconductor layer 23 functions as the connection resistance RL in the embodiment D-1 shown in Fig. 25.

Fig. 28 is a plan view showing the structure of this embodiment. In the light emitting elements T(-2) to T(2) when viewed from above in Fig. 27, inner rectangles correspond to the p-type semiconductor layers 21, and a portion around them corresponds to the p-type semiconductor layer 23. In this structure, notches 55 are formed in the p-type semiconductor layer 23. The notches 55 are used for changing the value of the connection resistance RL described in the embodiment D-1. When a large notch 55 is formed, the resistance of the connection resistance RL is increased. Therefore, in this embodiment, the connection resistance RL can be changed and optimized as desired, thereby achieving a more stable transmission operation.

The structure of this embodiment is the same as that of the equivalent circuit in the embodiment D-1 (Fig. 25) and performs the same operation. Therefore, if the high level voltages of the transfer clocks φ1, φ2 and φ3 are set to slightly overlap sequentially, the ON states of the light-emitting thyristors are sequentially transferred. That is, a light emission point can be sequentially shifted.

As described above, according to this embodiment, no gate electrode is required, and a resistor for connecting adjacent light-emitting elements only needs to be formed. In addition, the connection resistor RL can be formed by a semiconductor layer constituting the light-emitting elements. As can be understood from the above description, the structure of this embodiment can be formed by a simple manufacturing process. In these embodiments, it is assumed that the transfer clock pulses have three phases, i.e., φ1, φ2, and φ3. The number of phases can be increased to four or five to achieve a more stable transfer operation.

(Embodiment D-3)

Figs. 29 and 30 show an embodiment D-3. This embodiment is a practical structure of the embodiment D-2. Fig. 29 is a plan view, and Fig. 30 is a sectional view taken along the line X-X' in Fig. 29.

The plan view of Fig. 29 will now be described. The transfer clock lines Φ1, Φ2 and Φ3 are connected to underlying anode electrodes 40 via through holes C2. Each anode electrode 40 is connected to a p-type GaAs layer 21a as a p-type semiconductor layer of each light-emitting element. In the light-emitting elements T(-2) to T(2), a p-type GaAs layer 23a as a p-type semiconductor layer is shown around the rectangular p-type GaAs layers 21a. Notches 55 described in the embodiment D-2 are formed in the layer 23a to optimize the resistance of a connection resistor RL.

The sectional view of Fig. 30 will now be described. The light emitting elements are formed as follows. An n-type GaAs layer 24b, an n-type AlGaAs layer 24a, a p-type GaAs layer 23a, an n-type GaAs layer 22a, a p-type AlGaAs layer 21b and a p-type GaAs layer 21a are sequentially formed on an n-type GaAs substrate 1. Isolation grooves 50 for isolating the resulting structure into individual light emitting elements are formed by photolithography or the like and etching. The grooves 55 are notches for changing the value of the connection resistance RL. Although not shown in this sectional view, the connection resistance RL is a p-type semiconductor layer and employs the p-type GaAs layer 23a in this embodiment. A Insulating layer 30 provides electrical insulation between the anode electrodes 40 and the semiconductive layers. As the material of the insulating layer 30, a material that does not allow light from the light-emitting elements of this embodiment to pass through is preferably used in view of optical insulation between the light-emitting elements. The insulating layer may have a multi-layered structure so that it has an insulating function and an optical insulating function. In addition, when the optical insulating function is provided, a window must be formed so that light can be emitted to the outside. An insulating film 31 as an insulating interlayer performs insulating isolation between the anode electrodes 40 and the clock lines.

The manufacturing process of the embodiment D-3 is described below. The n-type GaAs layer 24b, the n-type AlGaAs layer 24a, the p-type GaAs layer 23a, the n-type GaAs layer 22a, the p-type AlGaAs layer 21b, and the p-type GaAs layer 21a are sequentially formed on the n-type GaAs substrate 1. The isolation grooves 50 are formed to isolate the light-emitting elements. The notches 55 are then formed to form the connection resistor RL. The isolation film 30 is formed, and the contact holes C1 are formed therein. The electrodes 40 are formed on the resulting structure. The isolation film 31 is formed, and through holes C2 are formed therein. Thereafter, the clock line electrodes Φ1, Φ2 and Φ3 are formed. With the above-mentioned process, the structure of this embodiment D-3 is completed.

As described above, according to this embodiment, no gate electrode is required, only a resistor for connecting the light-emitting elements needs to be formed, and the connection resistor RL can be formed by a semiconductor layer constituting the light-emitting elements. As is apparent from the above description, the structure of this embodiment can be formed by a simple manufacturing process.

The order of this process does not always have to be that described above. For example, the formation order of the isolation grooves 50 and the notches 55 may be reversed. A transparent insulating film may be formed on the structure shown in Fig. 30 to improve reliability. If it is not advantageous that the thickness of the insulating film is too large to deteriorate transmissions of light and to reduce the amount of light output to the outside, a part or all of the upper insulating film of the light-emitting element may be removed by, for example, photoetching. In this embodiment, GaAs and AlGaAs layers are used as semiconductor layers. However, the present invention is not limited to these, and other semiconductors may be used.

(Embodiment D-4) Application to laser

In the embodiments D-1 to D-3 described above, light-emitting thyristors were described as light-emitting elements. In the following embodiment, the case of using laser thyristors will be described.

31 and 32 show an embodiment D-4. In the embodiment D-4, the present invention is applied to a laser. Fig. 31 is a plan view of the embodiment D-4, and Fig. 32 is a sectional view thereof.

A manufacturing method is briefly described below. An n-type AlGaAs layer 125, a p-type AlGaAs layer 124, an i-type (undoped) GaAs layer 123, an n-type AlGaAs layer 122, a p-type AlGaAs layer 121 and an upper electrode layer 20 are sequentially stacked on an n-type GaAs substrate 1. The upper electrode layer 20 is patterned into a rectangular shape having the same width as that of the i-type GaAs layer 123 in Fig. 32. Using the electrode pattern 20 as a mask, the p-type AlGaAs layer 121 to the i-type GaAs layer 123 are etched. In this case, the element grooves 50 are formed. The upper electrode pattern 20 is further etched into a stripe pattern (current injection portion of a laser thyristor) having a width of 10 µm or less. Using the new electrode pattern 20 as a mask, the p-type AlGaAs layer 121 and the n-type AlGaAs layer 122 are etched. The n-type AlGaAs layer 122 is not completely removed but remains partially. The notches 55 are formed by photoetching. Thereafter, an insulation film 30 is formed.

The insulating film preferably has two functions, i.e., an insulating function and a light-shielding function, and can be formed of a plurality of types of films. When a SiO2 film is used as the insulating film, it allows light having a light-emission wavelength of 870 nm from GaAs to pass through, it can induce light coupling. Thus, a light-shielding film made of light absorption material such as amorphous silicon must be formed between the SiO2 films.

The contact holes C1 are formed by photoetching. A metal connection layer for the transfer clock lines is formed by deposition or sputtering, and the transfer clock lines φ1, φ2 and φ3 are then formed by photoetching. Finally, the end face of a laser beam output side is formed by cleavage or the like to achieve good parallelism, thereby completing the structure of this embodiment.

In the structure of this embodiment, when p and n conductivity types are reversed, the structure of this embodiment can function as described above when a bias condition and the like are inverted. Such a modification is also included in the scope of the present invention.

Embodiment E

The embodiments E described below represent another example of simplifying the structure of the light-emitting element arrays in the previously described illustrative embodiments B.

(Embodiment E-1)

Fig. 33 is an equivalent circuit diagram of an embodiment E-3. In this embodiment, a typical three-terminal light-emitting thyristor is used as a light-emitting element, whose light-emitting threshold voltage and current can be controlled from the outside.

The light-emitting thyristors T(-1), T'(-1), T(0), T'(0), T(1) and T'(1) are arranged in a row. The light-emitting thyristors T(-1) and T'(-1), T(0) and T'(0), and T(1) and T'(1) form blocks. Each block is a group of light-emitting elements to which an identical clock line pulse is applied. In this embodiment, each block is formed by two elements. Each of the light-emitting thyristors T(-1), T(0) and T(1) is represented by a combination of the transistors Tr1 and Tr2, and each of the light-emitting thyristors T'(-1), T'(0), and T'(1) is represented by a combination of the transistors Tr3 and Tr4. The transistors Tr1 and Tr3 are pnp transistors, and the transistors Tr2 and Tr4 are npn transistors. The transistors Tr1 and Tr3 are connected to the clock lines, and the transistors Tr2 and Tr4 are connected to a bias voltage and a ground potential.

As the connection between the light emitting thyristors, the base electrodes (hereinafter referred to as first gates) of the transistors Tr1 and Tr3 are connected to each other within each block, and the base electrodes (hereinafter referred to as second gates) of the transistors Tr2 and Tr4 are connected to each other between different blocks. Each of the three transfer clock lines φ1, φ2 and φ3 is sequentially connected to the emitter electrodes of the transistors Tr1 and Tr3 of every third block. Each clock line has a current limiting resistor Re.

A function is described below. Suppose that the transfer clock Φ1 goes to the high level and the light-emitting thyristors T(-1) and T'(-1) are turned on. In this case, the base potentials of the transistors Tr2(-1) and Tr4(-1) are set to a high potential (about 1 V) capable of flowing a current. Since the base of the transistor Tr4(-1) is connected to the base of the transistor Tr2(0), the light-emitting thyristor T(0) tends to be turned on. The influence of an ON state is given only to the light-emitting thyristor T(0) and is not given to the light-emitting thyristor T'(0). Similarly, in a block (-2), only the light-emitting thyristor T'(-2) tends to be turned on. It does not affect the light-emitting thyristor T'(-2). The ON block does not affect the next blocks, e.g. blocks (-3) and (1).

In this state, when the next transfer clock φ2 is set to an appropriate high level voltage, the light emitting thyristor T(0) is immediately turned on.

The base terminals of the transistors Tr3(0) and Tr3(0) are set to a potential of substantially zero because the light-emitting thyristor T(0) is turned on. Thus, a current flows through the transistor Tr3(0). For this reason, the light-emitting thyristor T'(0) is also turned on successively. On the other hand, another block (e.g., (-3)) to which the transfer clock φ2 is applied is not affected by the block (-1) and thus is not turned on. The range of a high level voltage capable of performing the transfer operation is considerably wide. The transfer operation can be performed on the low voltage side within the range of 1.5 to 2 V and on the high voltage side within the range up to a voltage defined by a breakdown voltage of the light-emitting thyristor. When the transmission block φ1 goes to the low level, the block (-1) is turned off and the ON state is shifted from the block (-1) to the block (0).

When the clock pulses φ1, φ2 and φ3 are set so that their high level voltages overlap each other, the ON light emitting elements are sequentially transferred. Thus, a light emitting element array capable of performing the self-scanning can be realized.

As described above, according to this embodiment, a self-scanning function can be realized without using a resistor for connecting the light-emitting elements, and a high level voltage of the transfer clock pulse suitable for the transfer can have a considerable margin, i.e., can be in a range of 1.5 to 2 V for a low voltage side and up to a breakdown voltage of the light-emitting thyristor for the high voltage side.

In this embodiment, the operation was described using the three-phase clock pulses. However, the structure of this embodiment can operate using clocks of four or more phases, as a matter of course. In Fig. 33, the light-emitting elements are arranged in a row. However, a linear arrangement need not be employed. For example, the light-emitting elements may be arranged in a zigzag pattern or may be arranged two lines away from the center, depending on the applications. In this embodiment, the description was made using only light-emitting thyristors. However, the present invention is not limited to this as long as a device having a similar function is used. A laser thyristor may be used as the light-emitting element. The light-emitting elements may be formed as individual parts or may be integrated by any means as described in the next embodiment.

(Embodiment E-2)

The equivalent circuit has been described in the embodiment E-1. In an embodiment E-2, an IC structure of the device in the embodiment E-1 is described.

Fig. 34 shows a more illustrative view of the equivalent circuit diagram of Fig. 33. Each light-emitting thyristor is basically expressed as a structure in which a total of four p- and n-type semiconductor layers are stacked in a predetermined order. In the pnpn structure, a pnp section corresponds to the transistors Tr1 and Tr3 in Fig. 33, and an npn section corresponds to the transistors Tr2 and Tr4. In Fig. 34, the connection relationship in Fig. 33 is replaced by the pnpn structure.

Fig. 35 shows a practical structure of Fig. 34. An n-type semiconductor layer 24, a p-type semiconductor layer 23, an n-type semiconductor layer 22 and a p-type semiconductor layer 21 are sequentially formed on a grounded n-type GaAs substrate 1. The resulting structure is patterned into individual light-emitting elements T(-1) to T(1) by means of photolithography or the like and etching, thereby forming the structure shown in Fig. 35.

The characteristic feature of this structure is that the light-emitting elements T'(0) and T(0) and the light-emitting elements T'(0) and T(1) have common lower pn- sections and the upper pn-sections of the light-emitting elements T(-1) and T'(-1), the light-emitting elements T(0) and T'(0) and the light-emitting elements T(1) and T'(1) are connected via a conductor material. The light-emitting thyristors have anode electrodes 40 and gate electrodes 41 (first gate terminals) and are separated from each other by an insulating layer 30.

Of the light-emitting thyristors T and T', the thyristors T are used in practice as light-emitting elements, and the thyristors T' are used for connecting adjacent elements. Light L�0 is output upward.

The structure of this embodiment is the same as the equivalent circuit shown in the embodiment E-1 (Fig. 33) and performs the same operation. Therefore, if the high level voltages of the transfer clocks φ1, φ2 and φ3 are set to slightly overlap sequentially, the ON state of the light-emitting thyristors is sequentially transferred. That is, a light emission point can be sequentially shifted.

As described above, according to this embodiment, no resistor is necessary for connecting the light-emitting elements, and the high-level voltage transfer range of the transfer clock pulse can have a considerable range, i.e., can have a range of 1.5 to 2 V on the low-voltage side and can reach up to a breakdown voltage of the light-emitting thyristor on the high-voltage side.

In the structure of this embodiment, when p and n conductivity types are reversed, the structure of this embodiment can function as described above when a bias condition and the like are inverted. Such a modification is also included in the scope of the present invention.

Embodiments F

The embodiments F described below can simplify drive circuits of the light-emitting element arrays in the illustrative embodiment B described earlier.

(Embodiment F-1)

In an embodiment F-1 described here, a diode is used as a means for the electrical connection.

Fig. 36 is an equivalent circuit showing the principle of the embodiment F-1. In this embodiment, a most common three-terminal light-emitting thyristor is used as a light-emitting element whose light-emitting threshold voltage and current can be controlled externally. Reference symbols T(-2) to T(+2) denote light-emitting thyristors arranged in a series. Reference symbols G-2 to G-2 denote gate electrodes of the light-emitting thyristors T(-2) to T(+2). Reference symbol RL denotes a load resistance of each gate electrode; D-2 to D2 denote diodes for performing electrical interaction, and VGK denotes a voltage source voltage. Each of the two transfer clock lines ?? and φ2 is sequentially connected to the anode electrodes of every other individual light emitting thyristor.

A function is described below. Suppose that the transfer clock φ2 goes to the high level and the light-emitting element T(0) is turned on. Under this condition, the potential of the gate electrode G0 is reduced to about 0 V due to the characteristics of the three-terminal thyristor (to about 1 V in the case of a silicon thyristor). When the voltage VGL is 5 V, the gate voltages of the light-emitting thyristors are determined by the network of diodes D-2 to D2. The gate voltage of an element near the light-emitting element T(0) is lowered the most, and the gate voltages are increased the more the elements are farther away from the element T(0). However, the effect of lowering a voltage occurs only for the right half of the element T(0) due to the unidirectional and asymmetric characteristics of the diode. More specifically, the gate voltage at the gate G₁ is set to be higher than that of the gate G₀ by a diffusion potential Vdf of the diode, and the gate voltage at the gate G₂ is set to be higher than that of the gate G₁ by a diffusion potential Vdf of the diode. On the other hand, no current flows through the gate G₋₁ corresponding to the left half because the diode D₋₁ is reverse biased and thus has the same potential as the voltage VGK. The next transfer clock pulse φ₁ is applied to the next elements T(1), T(-1), T(3), T(-3), and the like. Of these elements, the element T(1) has the smallest ON voltage, that is, about 2 Vdf. An element with the second lowest ON voltage is T(3), and the voltage is about 4 Vdf. The ON voltages of the elements T(-1) and T(-3) are about VGK + Vdf. In this way, the high level voltage of the transfer clock pulse is set to fall within the range between 2 Vdf to 4 Vdf, so that only the element T(1) can be switched on and the transfer function can be performed.

In the equivalent circuit of this embodiment, only the diode is used as an element for connecting the gate electrodes of the light-emitting thyristors. However, a resistor may be connected in series with the diode. In this case, the potential difference between the gates G₀ and G₁ is larger than the diffusion potential Vdf of the diode, and the range of the high-level clock voltage capable of performing the transfer function can be expanded.

In this embodiment, a function using two-phase transfer clock pulses has been described. The structure of this embodiment can of course operate when clocks of three or more phases are used.

(Embodiment F-2)

In the embodiment F-1, the equivalent circuit was described. In the embodiment F-2 described below, an IC structure of the arrangement of the embodiment F-1 is described. The essence of this embodiment lies in the structure in which a diode for performing the electrical coupling is formed by using a portion of a light-emitting element, so that a diode can be formed in the same process as that for manufacturing the light-emitting thyristor.

Fig. 37 shows a general structure of the embodiment F-2. An n-type semiconductor layer 24, a p-type semiconductor layer 23, an n-type semiconductor layer 22 and a p-type semiconductor layer 21 are sequentially formed on a grounded n-type GaAs substrate 1. Isolation grooves 50 for isolating the above-mentioned structure into individual light-emitting elements are formed by photolithography or the like and etching. Reference symbols T(-2) to T(+2) denote these individual light-emitting elements. The anode electrodes 40 have ohmic contact with the corresponding p-type semiconductor layers 21, and the gate electrodes 41 have ohmic contact with the corresponding n-type semiconductor layers 22. Insulating layers 30 are formed to prevent short circuit between the elements and the interconnections and at the same time serve as protective films for preventing deterioration of the characteristics.

The insulating layers 30 are preferably formed of a material that allows light having a light emission wavelength of a light emitting thyristor to propagate well therethrough. The n-type GaAs substrate 1 serves as a cathode for each thyristor. Each of the two transfer clock lines φ1 and φ2 is sequentially connected to the anode electrodes 40 of every other individual light emitting element. A load resistor RL is connected to each gate electrode. On the other hand, if light coupling occurs between the elements, the transfer operation of this embodiment may be influenced by the light coupling. To prevent this, each gate electrode extends partially into the isolation groove between the adjacent light-emitting elements so that a structure is inserted that prevents light coupling.

The structure of this embodiment is the same as the equivalent circuit shown in the embodiment F-1 (Fig. 36) and performs the same operation. Therefore, when the high level voltages of the transfer clocks φ1 and φ2 are set to alternately slightly overlap, the ON state of the light emitting thyristors is sequentially transferred. That is, one light emitting point is sequentially transferred. According to this embodiment, a two-phase driven self-scanning type light emitting element array can be realized by an integrated circuit.

In this embodiment, the transfer clock pulses are assumed to have two phases, i.e., Φ1 and Φ2. However, the number of phases may be increased to three or four to obtain a more stable transfer function.

(Embodiment F-3)

38 and 39 show an embodiment F-3. This embodiment is a practical structure of the embodiment F-2. Fig. 38 is a plan view of this embodiment, and Fig. 39 is a sectional view taken along the line Y-Y' in Fig. 38. Reference numerals T(-2) to T(+1) denote light-emitting elements.

A load resistor 63 connected to the gate terminal of each light-emitting thyristor is represented by RL and is formed by a semiconductor layer constituting the light-emitting thyristor. Diodes D-2 to D-1 are connected to thyristors T(-2) to T(+1), respectively. The anode of each diode is connected to the gate terminal of the next light-emitting thyristor and the load resistor 63.

The semiconductor layers and electrodes are connected through via holes C1 as via holes. The via holes C2 are via holes for connecting the anode electrodes 40 of the light-emitting thyristors and the transfer clock lines φ1 and φ2. A power source line 42 is connected to a power source voltage VGK and the load resistors RL. The power source line 42 is formed simultaneously with the gate electrodes 41. Note that the gate electrodes 41 also serve as non-shielding layers for preventing the light-emitting elements T(-2) to T(+1) from affecting each other with their light emission.

Fig. 39 is a sectional view of this embodiment. The light-emitting elements are formed as follows. An n-type GaAs layer 24b, an n-type AlGaAs layer 24a, a p-type GaAs layer 23a, an n-type GaAs layer 22a, a p-type AlGaAs layer 21b and a p-type GaAs layer 21a are sequentially formed on an n-type GaAs substrate 1. Isolation grooves 50 for isolating the resulting structure into individual light-emitting elements are performed by photolithography or the like and etching. An isolation groove 51 is formed to connect the light-emitting element T(0) and the coupling diode T(0). Each load resistor 63 (RL) is formed on the n-type GaAs layer 22a of the light emitting element. The resistor may be formed of another layer. For example, the resistor may be formed of the p-type GaAs layer 23a or may be formed as a resistance region.

A manufacturing process of the embodiment F-3 is described below. The n-type GaAs layer 23a, the n-type GaAs layer 22a, the p-type AlGaAs layer 21b, and the p-type GaAs layer 21a are sequentially formed on the n-type GaAs substrate 1. The isolation grooves are then formed to isolate the light-emitting elements and the resistors. The isolation grooves 51 are formed to separate the light-emitting diodes and the coupling diodes. The resistors 63 are formed in the same process as the process of forming the isolation grooves 51. More specifically, the p-type GaAs layer 21a and the p-type AlGaAs layer 21b are removed. The insulating films 30 are formed, and the contact holes C1 are formed therein. Thereafter, the electrodes 40, 41 and 42 are formed. The insulating films 31 are formed as insulating interlayers, and the through holes C₂ are formed. Thereafter, the electrodes φ₁, and φ₂ are formed. With the above-mentioned process, the structure of the embodiment F-3 is completed.

(Embodiment F-4)

In an embodiment F-4, a transistor is used as an electrical connection device.

Fig. 40 shows an equivalent circuit of the embodiment F-4. Each light-emitting thyristor described in the embodiment F-1 is expressed by a combination of a pnp transistor Tr1 and an npn transistor Tr2. The collector of the transistor Tr1 is connected to the base of the transistor Tr2, and the base of the transistor Tr1 is connected to the collector of the transistor Tr2, so that these transistors are caused to perform the same operation as the thyristor. The base of the transistor Tr1, for example, the collector of the transistor Tr2 corresponds to the gate of a three-terminal thyristor. Combinations of the transistors Tr1 and Tr2 are expressed by T(-1) to T(1). In the embodiment F-4, unlike the embodiment F-1, adjacent elements are connected to each other via a pnp transistor Tr3 without using the diodes. The base of the transistor Tr3 is connected to the base of the transistor Tr1, and the collector of the transistor Tr3 is connected to the base of the transistor Tr2. The transfer operation in this case is the same as that described in the embodiment F-1. That is, the thyristor in the embodiment F-1 can be regarded as a combination of the transistors Tr1 and Tr2, and the diode in the embodiment F-1 can be regarded as the transistor Tr3.

A detailed device structure in the embodiment F-4 is the same as that shown in the embodiments F-2 and F-3.

(Embodiment F-5)

Fig. 41 is an equivalent circuit of an embodiment F-5. In the embodiment F-5, the power source VGK and the load resistors RL are omitted from the equivalent circuit shown in the embodiment F-1. The equivalent circuit of the embodiment F-1 uses the fact that the ON voltage of the thyristor is determined with respect to the power source voltage VGK, the gate voltage of the ON element becomes almost 0 V, and this influences the neighboring elements via the diodes. In the embodiment F-5, the power source VGK is omitted. The function of this embodiment is described below.

Assume that a high level clock voltage is applied to the transfer clock line φ2 and a light emitting thyristor T(0) is turned on. The potential of a gate G0 becomes almost 0 V. In this case, the voltage at a gate G-1 of an adjacent light emitting thyristor T(-1) is indeterminate because a diode D-1 is reverse biased when the voltage at the gate G-1 exceeds 0 V and because no current flows. The voltage at a gate G1 of a light emitting thyristor T(1) cannot become larger than a diffusion potential Vdf of a diode D0. For this reason, the ON voltage of a light emitting thyristor T(-1) is determined by the device structure of the light emitting thyristor T(-1). Meanwhile, the ON voltage of the light emitting thyristor T(1) becomes a voltage larger than the potential at the gate G₀ by the potential Vdf', i.e., by about 2Vdf. If the ON voltage defined by the device structure is set to be larger than 2Vdf, two-phase driving can be achieved as described in the embodiment F-1.

According to the embodiment F-5, neither a power source nor load resistors are required, and the interconnection layers for the two transmission clocks only need to be formed, resulting in a simple structure.

(Embodiment F-6)

Figs. 42 and 43 show a structure of an embodiment F-6. The structure shown in Figs. 42 and 43 corresponds to an actual structure of the equivalent circuit shown in the embodiment F-5. Fig. 42 is a plan view, and Fig. 43 is a sectional view taken along a line X-X' in Fig. 42.

This structure is explained below. The transfer clock lines φ1 and φ2, the light-emitting elements T(-1) to T(1) are the same as those described above. The gate electrodes 41 connect the coupling diodes D-1 to D1 and the gates of the light-emitting elements. The portion of the light-emitting element shown in Fig. 43 is substantially the same as that shown in Fig. 39.

A manufacturing process of the embodiment F-6 will be described below. An n-type GaAs layer 24b, an n-type AlGaAs layer 24a, a p-type GaAs layer 23a, an n-type GaAs layer 22a, a p-type AlGaAs layer 21b and a p-type GaAs layer 21a are are sequentially formed on an n-type GaAs substrate 1. Isolation grooves 50 are then formed to separate the light-emitting elements. The isolation grooves 51 are formed to separate the light-emitting diodes and the coupling diodes. That is, the p-type GaAs layer 21a and the p-type AlGaAs layer 21b are removed. Insulating films 30 are formed and contact holes C₁ are formed therein. Thereafter, the electrodes 41 and the transfer clock lines φ₁ and φ₂ are formed. With the above-mentioned process, the structure of the embodiment F-6 is completed.

The characteristic feature of the structure of the embodiment F-6 is that, unlike the embodiment F-3, two-phase interconnection layers are not used. As can be seen from Fig. 42, the interconnection patterns can be formed without overlapping and only one interconnection layer needs to be formed. Since a resistor can be omitted, the manufacturing process can be simplified and the manufacturing cost can be further reduced.

(Embodiment F-7)

Fig. 44 is an equivalent circuit of an embodiment F-7. The embodiment F-7 corresponds to a reformulation of the embodiment F-5 as an equivalent circuit using transistors. The structure of the embodiment F-7 is substantially the same as that of the embodiment F-4 except that the load resistor is omitted in the embodiment F-4, and its operation is the same as that of the embodiment F-5. The actual structure of the embodiment F-7 is the same as that of the embodiment F-6.

In this way, the structure of this embodiment can be formed by the equivalent use of transistors.

(Embodiment F-8) Application to laser

In the above embodiments, the light-emitting thyristors were described as light-emitting elements. In the following embodiment, a case where laser thyristors are used will be described.

Figs. 45 and 46 show a structure of an embodiment F-8. Fig. 45 is a plan view of the embodiment F-8, and Fig. 46 is a sectional view thereof. Basically, a thyristor section is formed as a laser thyristor, and a coupling diode is provided in its cavity section. This structure adapts the equivalent circuits of the embodiments F-5 and F-7.

A manufacturing method will be briefly described. An n-type AlGaAs layer 125, a p-type AlGaAs layer 124, an i-type (undoped) GaAs layer 123, an n-type AlGaAs layer 122, a p-type AlGaAs layer 121 and an upper electrode layer 20 are sequentially stacked on an n-type GaAs substrate 1.

The upper electrode layer 20 is then photoetched into a rectangular shape having the same width as that of the n-type AlGaAs layer 125 in Fig. 46. Using the electrode pattern 20 as a mask, the p-type AlGaAs layer 121 to the n-type AlGaAs layer 125 are etched to form element separation grooves 50. The upper electrode pattern 20 is further etched into a stripe pattern (current injection portion of a laser thyristor) having a width of 10 µm or less and a coupling laser diode pattern (D-1 to D-1 portions). Using these patterns as masks, the p-type AlGaAs layer 121 and the n-type AlGaAs layer 122 are etched. The n-type AlGaAs layer 122 is not completely removed, but is partially retained. Thereafter, an insulating film 30 is formed. The insulating film preferably has two functions, i.e., an insulating function and a light-shielding function, and can be formed by a plurality of types of films. When a SiO₂ film is used as the insulating film, it allows a light emission wavelength of 870 nm from GaAs to transmit, it can induce light coupling. Thus, a light-shielding film made of a light absorption material such as amorphous silicon must be formed between the SiO₂ films. Contact holes C₁ are formed by photoetching. A metallic connection layer for the transfer clock lines is formed by deposition and sputtering, and the transfer clock lines Φ₁ and Φ₂ are then formed by photoetching. Finally, the end face of a laser beam output side is formed by cleavage or the like to obtain good parallelism, thereby completing the structure of this embodiment.

In this embodiment, the equivalent circuits of Embodiments F-5 and F-7 are applied to a laser. Alternatively, the equivalent circuits in Embodiments F-1 and F-4, i.e., including resistors, may of course constitute a laser.

In the structure of this embodiment, when the p and n conductivity types are reversed, the structure of this embodiment can operate as described above when a bias condition and the like are inverted. Such a modification is also included in the scope of the present invention.

In the above embodiments, control electrodes of adjacent light-emitting elements are connected to each other via an electrical device to form a network. Every other light-emitting element is connected to each other so that two systems of sensing functions can be provided in a single light-emitting element array. In a two-dimensional or three-dimensional light-emitting element array, the light-emitting elements are connected to four or six or more light-emitting elements via an electrical device.

Embodiments G

The embodiments G described here may expand a range of the transfer clock pulse voltage in the embodiments F described above and do not form part of the invention.

(Embodiment G-1)

Fig. 47 is an equivalent circuit showing the principle of an embodiment G-1. In this embodiment, the most common three-terminal light-emitting thyristor is used as a light-emitting element whose light-emitting threshold voltage and current can be externally controlled. Each thyristor is formed by a combination of a pnp transistor Tr1 and an npn transistor Tr2. The base of a transistor Tr3 is connected to the base of the npn transistor Tr2 and forms a current mirror circuit in combination with the npn transistor Tr2. The light-emitting thyristors T(-1) to T(1) are arranged in a series and are connected to each other via the current mirror circuits.

The light-emitting thyristors T(-2) to T(2) have gate electrodes G-1 to G+2, respectively. Each gate electrode has a load resistance RL. A power source voltage VGK is applied to the gate electrode. Each of the two transfer clock lines φ1 and φ2 is connected to the anode electrodes (emitters of the transistor Tr1) of every other single light-emitting thyristor. Each clock line has a resistance Re for limiting a current on the clock line.

A function is described below. Suppose that the transfer clock φ2 goes to the high level and the light emitting element T(0) is turned on. In this case, the potential at the gate electrode G0 is reduced to almost 0 V due to the characteristics of the three-terminal thyristor (to about 1 V in the case of a silicon thyristor). When the power source voltage VGK is 5 V, a current limited by the resistor RL flows from the gate G0. A current limited by the resistor Re flows from the emitter (anode). Since the transistors Tr2 and Tr3 form the current mirror circuit, the transistor Tr3 has a current drive power proportional to the transistor Tr2. With this current drive power, a current is drawn through the resistor RL connected to the collector of the transistor Tr3, so that the potential of the gate electrode G1 of the adjacent light-emitting element T(1) is lowered. By appropriately setting the drive power of the transistor Tr3, the potential of the gate electrode G1 can be reduced to almost zero. Since the ON voltage of the light-emitting element T(1) becomes a voltage larger than the potential of the gate electrode G1 by a diffusion potential Vdf, the ON state can be transmitted to the light-emitting element T(1) when the voltage of the transfer clock φ1 is larger than the diffusion potential Vdf.

In this way, the ON voltage of the light emitting element T(1) is lowered, while the ON voltage of the light emitting element T(-1) arranged on the opposite side is not changed. Even if the potential at the Gate G₀ is reduced to almost zero, the voltage of the gate G₈₁ for determining the ON voltage of the light emitting element T(-1) is not affected thereby.

As described above, the light-emitting element array using the current mirror circuits is driven by transfer clock pulses ranging from Vdf to VGK + Vdf and can be driven with a wide voltage range for VGK.

In this embodiment, the load resistor RL does not always have to be used, and the light emitting element array can operate without this resistor.

In this embodiment, two-phase transfer clock pulses are used. However, the structure of this embodiment can operate using clock pulses of three or more phases.

(Embodiment G-2)

In the embodiment G-1, the equivalent circuit has been described. In an embodiment G-2, the structure of the device in the embodiment G-1 is described. The essence of this embodiment lies in a structure in which a current mirror circuit (Tr2 and Tr3) can be formed in the same process as that of manufacturing the light-emitting thyristor.

Fig. 48 shows a general structure of the embodiment G-2. An n-type semiconductor layer 24, a p-type semiconductor layer 23, an n-type semiconductor layer 22 and a p-type semiconductor layer 21 are sequentially formed on a grounded n-type GaAs substrate 1. Isolation grooves 50 are then formed by photolithography or the like and etching so that the above-mentioned structure is patterned into individual light-emitting elements T(-1) to T(+1). The anode electrodes 40 have an ohmic contact with the p-type semiconductor layers 21, and the gate electrodes 41 have an ohmic contact with the n-type semiconductor layers 22. Insulating layers 30 are formed to prevent the short circuit between the elements and the connections, and at the same time, they serve as protective films for preventing the deterioration of the characteristics. Portions surrounded by a dashed line correspond to the transistors Tr3 and are connected to the gate electrodes 41. Each transistor Tr3 has a collector (22), a base (23), and an emitter (24). Each transistor Tr1 has an emitter (21), a base (22), and a collector (23). Each transistor Tr2 has a collector (22), a base (23), and an emitter (24).

The base of the transistor Tr2 is electrically connected to the base of the transistor Tr3. The collectors of these transistors are separated from each other. Each gate electrode 41 is connected to a power source VGK through a load resistor RL, and the substrate 1 is grounded. The substrate 1 serves as the emitter of the transistors Tr2 and Tr3.

The insulating layers 30 are preferably formed of a material that allows light having a light emission wavelength of a light emitting thyristor to pass therethrough. On the other hand, if light coupling occurs between the elements, the transfer operation of this embodiment may be affected by the light coupling. To prevent this, each gate electrode partially extends into the isolation groove between the adjacent light-emitting elements to employ a structure capable of preventing the light coupling.

The structure of this embodiment is the same equivalent circuit shown in the embodiment G-1 (Fig. 47) and performs the same operation. Therefore, when the high level voltages of the transfer clocks φ1 and φ2 are set to alternately overlap slightly, the ON state of the light emitting thyristors is sequentially transferred. That is, one light emission point is sequentially transferred.

(Embodiment G-3)

Figs. 49, 50 and 51 show an embodiment G-3. This embodiment represents a practical structure of the embodiment G-2. Fig. 49 is a plan view of this embodiment, Fig. 50 is a sectional view taken along the line X-X' in Fig. 49, and Fig. 51 is a sectional view taken along the line Y-Y' in Fig. 49.

Fig. 49 is described below.

A load resistor RL connected to the gate of each light-emitting thyristor is represented by a load resistor 63 and is formed by a semiconductor layer constituting the light-emitting thyristors T(-1) to T(1). The collectors of the current mirror transistors Tr3(-1) to Tr3(1) are connected to gate electrodes 41 via the contact holes C₁. The contact holes C₁ are via holes for connecting the semiconductor layers and the electrodes. Anode electrodes 40 of the light-emitting thyristors are connected to transfer clock lines φ₁ and φ₂ via via holes C₂ as through holes. A power source line 42 is connected to a power source voltage VGK and is connected to the load resistors 63 (i.e., RL). The power source line 42 is formed simultaneously with the gate electrodes 41. The gate electrodes 41 also serve as light-shielding layers to prevent the light-emitting elements T(-2) to T(+1) from influencing each other with their light emission.

Fig. 50 is a sectional view taken along line X-X', and Fig. 51 is a sectional view along line Y-Y'. The light-emitting elements are formed as follows. An n-type GaAs layer 24b, an n-type AlGaAs layer 24a, a p-type GaAs layer 23a, an n-type GaAs layer 22a, a p-type AlGaAs layer 21b, and a p-type GaAs layer 21a are sequentially formed on an n-type GaAs substrate 1. The isolation grooves 50 for isolating the resulting structure into individual light-emitting elements are formed by photolithography or the like and etching. An isolation groove 51 is formed to separate the light-emitting element T(0) and the current mirror transistor Tr3. Each load resistor 63 (RL) is formed from the n-type GaAs layer 22a of the light emitting element.

The resistor may be formed from another layer. For example, the resistor may be formed from the p-type GaAs layer 23a, or may be formed as another resistor region.

A manufacturing process of the embodiment G-3 is described below. The n-type GaAs layer 24b, the n-type AlGaAs layer 24a, the p-type GaAs layer 23a, the n-type GaAs layer 22a, the p-type AlGaAs layer 21b, and the p-type GaAs layer 21a are sequentially formed on the n-type GaAs substrate 1. The isolation grooves are then formed to isolate the light-emitting elements and the resistors. The p-type GaAs layer 21a and the p-type AlGaAs layer 21b corresponding to gate guide portions and unaffected portions of the transistor Tr3 are removed, and the isolation grooves 51 are formed. In the step of removing these p-type layers 21b and 21a, a portion of the p-type GaAs layer 22a functioning as resistors 63 is simultaneously removed. The insulating films 30 are formed, and the contact holes C1 are formed therein. After that, the electrodes 40, 41 and 42 are formed. The insulating films 31 are formed as interlayer insulating layers, and the through holes C2 are formed. After that, the electrodes φ1 and φ2 are formed. The structure of the embodiment F-3 is completed by the above-mentioned method.

Embodiments H

The embodiments H described here relate to composite elements each formed by combining the light-emitting element array described above and a light deflector. They do not form part of the invention.

(Embodiment H-1)

When a composite element of this embodiment is applied to an optical scanning apparatus used in, for example, an optical printer, high-resolution optical scanning can be realized.

There are two typical scanning systems employed in a conventional optical printer. One system has a device H for deflecting a laser beam La or the like emitted from a light emitting element T as shown in Fig. 61. The other system causes an array T of n light sources arranged in series to flash and scan sequentially or causes a shutter arrangement to open/close and scan (Fig. 62).

A typical device of a light deflection system is a polygonal rotary mirror, which has the advantages of a large deflection angle and high resolution. However, such a device is not easily made compact, an optical system requires complex adjustment, and tends to be affected by mechanical vibration. The device is therefore not suitable for an application requiring high precision. As a light deflector capable of eliminating such disadvantages, it is known to use the modulation of the refractive index using an acousto-optical effect, an electro-optical effect or the like. Since such a deflector is a solid member, it can be easily made compact. Since the deflector does not include a movable portion, it can be easily adjusted and is not easily affected by mechanical vibration. Therefore, a scanning light spot has high positional accuracy. However, the deflection angle is small and the resolution is low compared with deflection by a mechanical device such as a polygonal rotary mirror, thereby limiting the application range. In general, optical scanning by deflection has the advantage that the number of light sources can be reduced. Such an advantage, however, leads to difficulties in maintaining the light intensity on a light receiving surface 100 for a wide optical scanning width.

An optical scanning system using a light source array or a shutter array does not originally include a movable portion, and it is also advantageous that the total scanning width can, in principle, be desirably increased in proportion to the number of array elements. However, a large scanning width requires a lot of array elements such as optical shutters, so that the number of integrated circuits (ICs) for driving these elements is correspondingly increased. As a result, the manufacturing process such as terminal bonding becomes complicated. This problem can be solved by using a light emitting element array according to the present invention, and the number of circuits for driving the light emitting element array can be greatly reduced, thereby easily enabling an increase in the optical scanning width.

When the above-mentioned self-scanning array is used, the scanning width can be easily increased in an optical scanning system by using a large number of light-emitting elements. However, the light-emitting elements and the light spots being scanned have a 1:1 correspondence regardless of the scanning width. Therefore, in order to improve the resolution of the light spot, the light emission area of the light-emitting elements must be reduced and the inter-element distance must be shortened. However, the light emission area has a low limit as long as one light-emitting element is required to provide a light output of a certain intensity. Therefore, optical scanning using the array makes it difficult to reduce the distance of the light spots below a certain limit to improve the resolution.

According to a composite element array of this embodiment, the conventional problem can be solved. For example, a large number of light-emitting elements described in the embodiments B are arranged linearly, two-dimensionally or three-dimensionally, and control electrodes of the light-emitting elements are connected as shown in Fig. 9. A light deflector capable of controlling an output direction of light emitted from each light-emitting element is provided to each light-emitting element so that a composite element array is formed.

As the light deflector, arbitrary elements such as one for causing a gradient of a refractive index with the injection of a current, one for applying an electric field to control a refractive index, and the like can be used as long as they can deflect incident light.

In this embodiment, as shown in Fig. 52, a large number of light deflectors H are paired with light-emitting elements T and arranged linearly. A light deflector that receives a light beam La emitted from the light-emitting element T(i) is represented by H(i).

The basic operation of the composite element array having the above structure is described below. A light beam is emitted from a light deflector H(0) and reaches a point x0 on a light receiving surface 100. Control is performed such that the light deflector H(0) starts a deflection operation at the same time when the light emitting element T(0) is turned on. A deflection beam from the light deflector H(0) is moved in a direction of arrow d and reaches an end point x1 on the light receiving surface 100. At the same time, the deflection beam causes the next light emitting element T(1) to emit light and the light deflector H(1) to start the operation. In this case, adjustment is performed to cause the position of a light spot formed by the deflected light beam to radiate to the end point x₁ to coincide with the spot position of the deflection start point (x₁) of the light deflector H(1).

Thus, if similar settings and controls are made, continuous optical scanning over a large area can be realized by this system. If the resolution of the light deflectors H is represented by N, the accuracy can be increased N times without increasing the number of light-emitting elements.

When the number of light-emitting elements is M, the total number of elements is 2 M when the light deflectors are added to the light-emitting elements. Therefore, when N > 2, the accuracy can be improved compared with an array containing only the 2 M light-emitting elements. Thus, even if the resolution of the light deflector used in this embodiment is not so high, a remarkable effect can be achieved.

An AlGaAs/GaAs type composite element of embodiment H-1 is described in detail below.

A semiconductor laser having a light deflection function is described in Electronic Letters, volume 23, page 361 (1987). Two electrodes are arranged on two sides of a semiconductor waveguide along which the light output from a semiconductor laser propagates, and currents having asymmetrical magnitudes are injected into the electrodes so that a refractive index of a waveguide portion is caused to have a gradient, thereby performing light deflection.

In this embodiment, a semiconductor fiber having good beam convergence is used as the light-emitting element T. Since threshold current control is performed, a laser thyristor is used. A light deflector H employs a device using current injection as in the above-mentioned article, with two electrodes formed by thyristors to achieve control by an external signal. The light-emitting elements T and the light deflectors H are arranged in an arrangement as shown in Fig. 52 and are connected in the same manner as the network shown in Fig. 9, thus forming an array of component elements.

Fig. 53 shows an inter-element electrical connection. A plurality of light emitting elements T are connected to each other via resistors RI and RL in the same manner as in Fig. 9. A plurality of current injection elements H1 and H2 constituting a plurality of light deflectors H receive a power source voltage V'GK through load resistors R'L at their gate electrodes. The gate electrodes are electrically connected via the resistors R'I so as to provide interaction. These light-emitting elements T and the current injection elements H1 and H2 are connected such that currents IT controlled by the light emission signals φI, φI', and φI" flow into the elements through the lines φ1, φ2, φ3, φ1', φ2', φ3', φ1", φ2" and φ3'''.

Fig. 54 is a partial plan view of a composite element array for realizing the above-mentioned electrical connection and light coupling. This arrangement is an example, and another connection pattern may be employed as long as the elements are arranged so that the laser output beams La from the laser thyristors T are efficiently incident on the light deflectors H. The resistors RI in this embodiment may be replaced by diodes as described in the embodiments F. The number of clock lines can thus be reduced to two. Figs. 55 and 56 show sectional structures corresponding to a portion of an AlGaAs/GaAs type laser thyristor array T (X-X' in Fig. 54) and a light deflector portion H (Y-Y' in Fig. 54).

The device structure of the composite element will be briefly described. The laser thyristor T and the light deflector H have a common crystal layer structure. This is not a necessary condition. However, in order to simplify the manufacturing process, a common crystal layer is preferably used. An appropriate n-type GaAs buffer layer (though not shown in Fig. 55) is formed on an n-type GaAs substrate 1. An n-type AlGaAs layer 125, a p-type AlGaAs layer 124, an i-type (undoped) GaAs layer 123, an n-type AlGaAs layer 122, and a p-type AlGaAs layer 121 are sequentially formed on the buffer layer. A p-type GaAs layer may be formed on the uppermost contact layer of the resulting structure. The i-type (undoped) GaAs layer 123 serves as an active layer of the laser, and the AlGaAs layers 122 and 124 formed on the two main surfaces of the layer 123 serve as cladding surfaces. In the laser thyristor T of this embodiment, fins 53 are formed by partially removing the uppermost layer 121 up to the center of the upper cladding layer 122. The laser structure is not always limited to this, and a buried structure may be used. The gate electrodes 41 are formed on the n-type AlGaAs layer 122 and serve as the upper cladding layer. One end face 66 (Fig. 54) on the side of the deflector H of an optical resonator of the laser thyristor T is formed by, for example, dry etching. The other end face 67 may be formed by a cleaving method.

The light deflector H is composed by the same multilayer structure as that of the laser thyristor T. The current injection elements H1 and H2 are arranged at symmetrical positions with respect to a light propagation direction and have the same thyristor structures as the laser thyristor T. The p-type AlGaAs layers 121 immediately below the upper electrodes 71 and 72 are insulated by an insulation groove 52 to prevent lateral current flow. The gate electrodes 41 are formed on the n-type AlGaAs layer 122 by removing the upper layer in the same manner as in the laser thyristor section. Each light deflector H is arranged in a position capable of efficiently receiving a beam La output from the laser. However, the laser and the deflector may be electrically insulated.

Fig. 57 is a perspective view of a composite element described in the above-mentioned article (Electronic Letters, 1987).

The crystal growth used in the above element formation can be achieved by LP-CVD, MO-CVD or MBE. In this embodiment, the light emission wavelength is about 900 nm because the laser employs a GaAs active layer. However, the material is not limited to GaAs. When AlGaAs is used, the wavelength can be shortened to about 780 nm, while when InGaP or AlGaInP is used, it can be shortened to the order of 600 nm. These materials can be selected depending on the applications.

A driving method of the composite optical scanning element is described below. Under the connection relations shown in Fig. 53, the clock pulses are sequentially applied to the laser thyristors T(-1), T(0) and T(1) via the lines φ2, φ3 and φ1 at times shown in Fig. 58 so that they are turned on. A laser driving current is supplied from the line φI to turn on and scan each laser. Pulses, which rise by Δt earlier than the clock pulses are sequentially applied to the thyristor pairs H1(-1), H2(-1), H1(0), H2(0), H1(1) and H2(1) of the light deflectors H(-1), H(0) and H(1) via lines Φ1', Φ1"Φ2',Φ2",Φ3' and Φ3". For example, the clock pulse is applied to the line Φ3, and the pulses are applied to the two thyristors H1(0) and H2(0) of the light deflector H(0) from the lines Φ3' and Φ3" immediately before the laser T(0) is turned on, so that these thyristors are turned on. When the laser T(0) is turned on, the symmetrical ramp signals IT1 and IT2 from the lines Φ1' and Φ2" are applied to the thyristors H1(0) and H2(0). The clock pulse will become zero when the next clock pulse is sent to the line Φ1, and the ramp currents will return to the original values. Thus, the thyristors H1(0) and H2(0) will be turned off. At this time, the thyristors H1(1) and H2(1) of the adjacent light deflectors H(1) have already been turned on and have started a deflection operation when the adjacent laser T(1) is turned on. The elements will be operated with the same timings thereafter.

(Embodiment H-2)

In an embodiment H-2, a light deflector of a type of controlling a refractive index by an electric field is used as the light deflector H to form a composite element. As is well known, a light deflector using such an effect can be realized by using a dielectric crystal prism having an electro-optical effect. In the case of a semiconductor, not only the electro-optical effect but also the Franz-Keldysh effect or a quantum trapping Stark effect using a quantum well can be used by applying a reverse bias to a junction. When such a composite effect is applied to a semiconductor waveguide, a semiconductor deflector can be easily derived from the above dielectric element in an analogous manner. Fig. 60 shows its structure.

In this structure, an n-type AlGaAs layer 125, an i-type (undoped) GaAs layer 123, a p-type AlGaAs layer 121 are formed on an n-type GaAs substrate 1, and the electrodes 73 and 74 are formed on two main surfaces of the resulting structure. A negative voltage is applied to the electrode 74 relative to the electrode 73, the i-type (undoped) GaAs layer 123 is depleted, and an electric field is applied thereto. Depending on the electric field intensity, the refractive index of the i-type (undoped) GaAs layer 123 is changed. The refractive index under the electrode 74 is therefore different from the refractive index of other regions, and this difference can be externally controlled. Thus, the direction of an output beam Lh can be controlled.

The light deflector H and the laser thyristor T are combined to realize a composite element. The same laser thyristor and arrangement as in the embodiment H-1 can be used. However, since the light deflector of this embodiment is used in a reverse bias state, the power consumption is small. and no problem arises even if all the elements are always operated. In this case, only the clock line for the light emitting element T needs to be formed as shown in Fig. 59, and no gate electrodes for the light deflector H are required. Only one line for supplying a common ramp voltage V'GK is formed. Of course, the start and end points of this ramp voltage must be made to coincide with the turn-on and turn-off clocks of each laser.

Note that the light deflector H in Fig. 60 has a simplest structure and that another structure may be employed. For example, an optical waveguide layer may have a quantum well layer. In this case, a quantum well laser thyristor is preferably employed to assist the manufacturing process.

The electrode shape is not limited to that shown in Fig. 60 as long as it can effectively form an asymmetric refractive index distribution. Furthermore, the constituent materials only need to have the above-mentioned effect, and at least the materials described in the embodiment H-1 can be used.

As described above, when light deflectors are added to the light-emitting elements, the resolution of the scanning light spots can be improved without increasing the number of light-emitting elements, as compared with a composite element having only one light-emitting element array. Since the threshold current or voltage of the light-emitting elements can be controlled and their control electrodes are connected by electrical means, a simple scanning system can be constructed only by applying drive clocks. Drive circuits are not complicated for an array including light deflectors.

The above embodiments solve the conventional problems such as the number of wire connections, drive ICs, miniaturization and reduction in pitch by providing a self-scanning function for a light-emitting element array itself. When the light-emitting element array scans itself, ICs are not required and thus the wire connection can be omitted.

The above embodiments also provide a light emitting device that can perform the stable and reliable power-on self-sensing.

The above embodiments provide a light emitting device that can facilitate external self-scanning control and that can widen a control range so as not to cause erroneous operation.

The above embodiments provide a self-scanning light-emitting element array having a simple integrated circuit structure to simplify its manufacture.

The above embodiments provide a self-scanning light-emitting element array having a simple integrated circuit structure to simplify its manufacture.

The above embodiments provide a self-scanning light-emitting element array having a directivity in a self-scanning function in a direction of the element array so that the power-on transmission can be performed by two-phase clocks.

The above embodiments provide a self-scanning light-emitting element array that enables control to increase the luminance of at least one element at an arbitrary position in the light-emitting element array to obtain an image display function.

The above embodiments provide a self-scanning light-emitting element array that can obtain the light spot scanning performance sufficiently finer than the array pitch of light-emitting elements.

The above embodiments provide a method of driving a light-emitting element array, which is suitable for stably and reliably performing self-scanning of the light-emitting element array and for simplifying an integrated circuit structure of the array.

The above embodiments include a method of driving a light emitting device in which the power-on transfer is operated in response to clocks and the transfer control and the synchronous control of an image display are realized.

Claims (11)

1. A self-scanning light-emitting array comprising: an array of light-emitting elements (T) with electrically controllable switch-on thresholds, the array being composed of a plurality of blocks, each having a plurality of light-emitting elements, coupling means which electrically connect the control electrodes of adjacent blocks of the light-emitting elements (T) so that a block in a threshold-reduced state changes the threshold of a next block so that it enters a threshold-reduced state, the coupling means not serving to connect control electrodes within each block to one another, and at least two phase clock devices operable to provide clock pulses of a plurality of phases to blocks assigned to the corresponding phases, such that each clock pulse propagates a turn-on operation and a threshold state in a direction of the array. 2. The array of claim 1, wherein each of the light emitting elements comprises an element in which a plurality of layers of p- and n-conductivity type semiconductors are stacked. 3. An array according to claim 2, in which semiconductors of a second conductivity type each connecting a semiconductor of a first conductivity type connected in a line arranged to carry a drive pulse of the corresponding phase are connected to each other in a block, and the semiconductors of the first conductivity type each connecting the semiconductor of the second conductivity type to which a bias voltage is applied in common with the light-emitting elements are connected to each other between adjacent blocks. 4. An array according to claim 3, in which: the drive pulses form a three-phase clock signal, the blocks belonging to the corresponding phases being arranged in the order of the first, second and third phases and being connected to common drive lines corresponding to the three phases, and the drive pulses are arranged to drive the blocks in the order of the first, second and third phases, with a trailing edge of one pulse overlapping the leading edge of the next pulse in the named order. 5. Array of self-scanning light-emitting elements, comprising: an array of light-emitting elements, the turn-on threshold levels of which can be electrically controlled, a coupling element having electrical unidirectionality and connecting the control electrodes together in an element array direction for controlling the threshold levels of the light emitting element that is turned on and changing the threshold level of an adjacent light emitting element that is turned on next, and driving means connected to the light emitting elements for supplying drive pulses thereto in parallel for transmitting a turn-on operation in the array direction at an interval of clock pulses while a change in the threshold level propagates in an array direction, the driving means being formed of two phases, the light emitting elements belonging to the respective phases being alternately arranged and connected to common drive lines corresponding to the respective phases, and the driving means being arranged such that the light emitting elements are alternately driven in first and second phases in response to two-phase driving pulses in which a trailing edge of one pulse overlaps a leading edge of the next pulse. 6. The array of claim 5, wherein the coupling element comprises a diode. 7. The array of claim 5, wherein each of the light emitting elements comprises an element in which a plurality of layers of p- and n-conductivity type semiconductors are stacked. 8. The array of claim 7, wherein a semiconductor of a second conductivity type contacting a semiconductor of a first conductivity type connected to a line for supplying the corresponding drive pulse is used as each of the control electrodes, and the semiconductor of the first conductivity type is locally formed on the semiconductor of the second conductivity type to form a diode as the coupling element, the diode connecting the control electrode of an adjacent light-emitting element. 9. The array of claim 8, further comprising load resistors for connecting the control electrodes of the light emitting elements to a constant voltage conduction path. 10. The array of claim 5, wherein the coupling element is a base-emitter junction of a transistor. 11. Array according to one of claims 1 to 4, wherein the clock means has three phases and is connected to the light emitting elements (T) in a sequential manner via three transmission lines (Φ1, Φ2, Φ3) and the coupling means comprises resistors (RI).