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FR3018139B1 - Circuit integre a composants, par exemple transistors nmos, a regions actives a contraintes en compression relachees - Google Patents

Circuit integre a composants, par exemple transistors nmos, a regions actives a contraintes en compression relachees Download PDF

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Publication number
FR3018139B1
FR3018139B1 FR1451616A FR1451616A FR3018139B1 FR 3018139 B1 FR3018139 B1 FR 3018139B1 FR 1451616 A FR1451616 A FR 1451616A FR 1451616 A FR1451616 A FR 1451616A FR 3018139 B1 FR3018139 B1 FR 3018139B1
Authority
FR
France
Prior art keywords
integrated circuit
nmos transistors
component integrated
compression stresses
compressed compression
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1451616A
Other languages
English (en)
Other versions
FR3018139A1 (fr
Inventor
Christian Rivero
Guilhem Bouton
Pascal FORNARA
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Rousset SAS
Original Assignee
STMicroelectronics Rousset SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Rousset SAS filed Critical STMicroelectronics Rousset SAS
Priority to FR1451616A priority Critical patent/FR3018139B1/fr
Priority to US14/627,281 priority patent/US9269771B2/en
Priority to CN201510091800.3A priority patent/CN104882446B/zh
Priority to CN201520120163.3U priority patent/CN204424255U/zh
Publication of FR3018139A1 publication Critical patent/FR3018139A1/fr
Priority to US14/953,692 priority patent/US9899476B2/en
Priority to US15/864,451 priority patent/US10211291B2/en
Application granted granted Critical
Publication of FR3018139B1 publication Critical patent/FR3018139B1/fr
Priority to US16/241,762 priority patent/US10490632B2/en
Priority to US16/657,409 priority patent/US10770547B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/60—Peripheral circuit regions
    • H10B20/65—Peripheral circuit regions of memory structures of the ROM only type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/795—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in lateral device isolation regions, e.g. STI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)

Abstract

Circuit intégré, comprenant un substrat (1) et au moins un composant défavorablement sensible aux contraintes en compression (TRN) disposé au moins partiellement au sein d'une région active (10) du substrat (1) limitée par une région isolante (2). Le circuit comprend au moins une tranchée électriquement inactive (20) située au moins dans ladite région isolante et contenant un domaine interne (203) configuré pour permettre une réduction de contraintes en compression dans ladite région active.
FR1451616A 2014-02-28 2014-02-28 Circuit integre a composants, par exemple transistors nmos, a regions actives a contraintes en compression relachees Expired - Fee Related FR3018139B1 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FR1451616A FR3018139B1 (fr) 2014-02-28 2014-02-28 Circuit integre a composants, par exemple transistors nmos, a regions actives a contraintes en compression relachees
US14/627,281 US9269771B2 (en) 2014-02-28 2015-02-20 Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stresses
CN201510091800.3A CN104882446B (zh) 2014-02-28 2015-02-28 包括具有含弛豫压应力的有源区域的例如nmos晶体管的部件的集成电路
CN201520120163.3U CN204424255U (zh) 2014-02-28 2015-02-28 集成电路
US14/953,692 US9899476B2 (en) 2014-02-28 2015-11-30 Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stresses
US15/864,451 US10211291B2 (en) 2014-02-28 2018-01-08 Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stresses
US16/241,762 US10490632B2 (en) 2014-02-28 2019-01-07 Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stresses
US16/657,409 US10770547B2 (en) 2014-02-28 2019-10-18 Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stresses

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1451616 2014-02-28
FR1451616A FR3018139B1 (fr) 2014-02-28 2014-02-28 Circuit integre a composants, par exemple transistors nmos, a regions actives a contraintes en compression relachees

Publications (2)

Publication Number Publication Date
FR3018139A1 FR3018139A1 (fr) 2015-09-04
FR3018139B1 true FR3018139B1 (fr) 2018-04-27

Family

ID=50473672

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1451616A Expired - Fee Related FR3018139B1 (fr) 2014-02-28 2014-02-28 Circuit integre a composants, par exemple transistors nmos, a regions actives a contraintes en compression relachees

Country Status (3)

Country Link
US (5) US9269771B2 (fr)
CN (2) CN204424255U (fr)
FR (1) FR3018139B1 (fr)

Families Citing this family (4)

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FR3007198B1 (fr) * 2013-06-13 2015-06-19 St Microelectronics Rousset Composant, par exemple transistor nmos, a region active a contraintes en compression relachees, et procede de fabrication
FR3018139B1 (fr) * 2014-02-28 2018-04-27 Stmicroelectronics (Rousset) Sas Circuit integre a composants, par exemple transistors nmos, a regions actives a contraintes en compression relachees
FR3025335B1 (fr) 2014-08-29 2016-09-23 Stmicroelectronics Rousset Procede de fabrication d'un circuit integre rendant plus difficile une retro-conception du circuit integre et circuit integre correspondant
US11101273B1 (en) * 2020-02-25 2021-08-24 Nanya Technology Corporation Semiconductor structure having word line disposed over portion of an oxide-free dielectric material in the non-active region

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Also Published As

Publication number Publication date
US20180130881A1 (en) 2018-05-10
US20160093696A1 (en) 2016-03-31
US10770547B2 (en) 2020-09-08
US10490632B2 (en) 2019-11-26
CN104882446B (zh) 2018-03-20
US9899476B2 (en) 2018-02-20
US20190165105A1 (en) 2019-05-30
US9269771B2 (en) 2016-02-23
US20150249132A1 (en) 2015-09-03
FR3018139A1 (fr) 2015-09-04
CN204424255U (zh) 2015-06-24
CN104882446A (zh) 2015-09-02
US20200052073A1 (en) 2020-02-13
US10211291B2 (en) 2019-02-19

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