GB2148635A - Integrated circuit memories - Google Patents

Abstract

An integrated circuit memory comprises a plurality of magnetic memory elements (10) and an integrated circuit comprising semiconductor switches (9) arranged to be selectively activated to allow electric current to pass adjacent a selected memory element (10) for the reading and writing of data bits at that memory element (10). <IMAGE>

Description

SPECIFICATION Integrated circuit memories This invention relates to integrated circuit memories, and relates particularly to magnetic memories. Magnetic memories, particularly magnetic core memories, have been used as storage devices for many years, but semiconductor memories have now supplanted magnetic memories in most computer applications. Monolithic RAMs are constructed using integrated circuit technology and employing bipolar or MOS transistors for the storage and supporting circuits. These memories provide the advantages of low cost and small size, but have the disadvantage of volatility of storage.

Stand-by batteries and CMOS techniques have been used to provide or simulate nonvolatile read/write memories.

According to the present invention there is provided a random access memory comprising a plurality of memory elements provided by respective magnetic zones of the memory, the memory also including, as an integrated circuit, semiconductor devices arranged to be selectively activated to allow the passage of current adjacent a selected one of said zones to create a magnetic field in that zone for the reading and/or writing of a data bit.

It will be appreciated that the invention concerns a random access semiconductor memory device which uses areas of magnetic material as memory elements with sufficient magnetic retentivity that the memory is inherently non-volatile. This is to be contrasted with bubble memories which are serial access devices, do not store data at fixed locations and require bias magnetic fields for their operation.

Addressing, buffering, read amplification, and other control functions can be implemented using semiconductor integrated circuit technology. The magnetic material is magnetised using current passed adjacent to the material so that magnetisation in one direction is a digitial "0" and magnetisation in the other direction is a digital "1" (or it could be an analog signal stored as different levels of magnetism). Read out can be achieved by applying a write signal and by sensing the consequent change of field in the magnetic material, or by using the magnetic field of the material directly to affect semiconductor devices (e.g. using the Hall effect) in a way that can be detected for non-destructive read out.

In one embodiment, the magnetic material is provided by a plane or sheet of material, or by an array of discreet elements of magnetic material, integrated during manufacture with the semiconductor devices. In the alternative, the sheet or array of magnetic material could be in the form of a non-rotating, removable, media arranged to be placed in contact with or close proximity to the semiconductor devices. In both cases it is contemplated to provide the memory in the form of an integrated circuit package and, in the latter case, to provide the magnetic material as a thin film on a releaseable carrier so that the memory data contents can be changed at will. Metallic screening may be desirable within or outside the package to protect the data stored in the magnetic material.

For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, in which: Figure 1 is a schematic view of an integrated circuit memory device; Figure 2 is a schematic diagram of a memory cell of the device of Fig. 1; Figures 3 and 4 show alternative forms of memory cell; and Figure 5 shows a modification of Fig. 3.

Figs. 1 and 2 illustrate schematically one form of integrated circuit memory device utilising integrated circuit technology together with the provision of magnetic material for non-volatile data storage. Preferably, the integrated circuit is formed as a package which is pin-compatible with existing semiconductor memory circuits. Thus, the integrated circuit 1 includes memory cells 2 (only some of which are shown in Fig. 1) address decoders 3 and 4, a data input 5, a data output 6 and a read/not-write control line 7. Details of the integrated circuit may in many other respects follow existing semiconductor memory techno- logy, the prime difference being in the structure of the memory cells one of which is diagrammatically shown in Fig. 2.

Referring now to Fig. 2, there is shown a block 9 representing an integrated semiconductor or transistor switch together with an area of magnetic material 10, formed by integrated circuit processes on the same substrate as the switch 9. The magnetic area 10 may be a thin or thick film of magnetic material, for example of 80% nickel and 20% iron. Formed on the same substrate are addressing conductors 11 and 12, there being associated with the addressing conductor 12 a control conductor 13 for determining in conjunction with conductor 12 whether or not read/addressing or write/addressing is to be accomplished. The substrate further carries a conductor 14 constituting a sense line. In this particular example the conductors 13 and 14 are shown as having been formed closely to overlie (or underlie) the magnetic area 10.

The area 10 could be a discreet portion of magnetic material or it in the alternative could be a zone of an overall layer of magnetic material common to a plurality of memory cells.

Fig. 2 is best explained further by describing write and read operations.

In order to write a digital "0", conductor 12 is brought high, conductor 11 is brought high and conductor 13 is brought low. The signal on conductor 11 renders the switch 9 conductive, causing a current to flow in the direction from conductor 12 to conductor 13 and closely adjacent to the magnetic area or zone 10. This magnetises the area 10 in a given direction representing a digital "0".

In order to write a digital "1", conductor 11 is again brought high to render the switch 9 conductive, whilst conductor 12 is brought low and 13 high in order to create a current in the opposite direction and thus magnetise the area 10 in the opposite direction.

In order to carry out a read operation, the operation described above for writing "0" is performed simultaneously with sensing the voltage in sensing line 14. If it is sensed that there is a voltage fluctuation in the line 14, then the magnetic area was in the "1" state, otherwise it contained the value "0".

The switch 9 is used as the basis for addressing and controlling the magnetic area 10, this avoiding the need to rely on half current writing methods.

One possible modification to the memory cell would be to integrate into the cell a layer of semiconductor material above or below the area 10 and formed of material suitable for utilising the Hall effect. The sense line 14 can then be used to pass a current through this additional semiconductor element in order to detect the direction of magnetism acting on the element by virtue of the magnetic field retained in the area 10. Other alternatives envisaged include providing integrated pre amplifier devices associated with individual sense lines 14 or groups of sense lines 14 rather than a single amplifier as shown at 15 in Fig. 1.Moreover existing memory tech niques may be additionally employed to achieve non-destructive read-out, e.g. by the use of twin magnetic zones in each area 10 or by techniques involving the use of magnetic material with preferential directions of mag netisation.

Fig. 3 shows an alternative form for the memory cell, this including an additional sem iconductor switch 16, other elements being given the same numerals as in Fig. 2 where appropriate. In order to write a digital "0" conductor 12 is brought high, 11 is brought high and 13 brought low, this causing both switches to conduct and to pass a current across the magnetic area or zone 10 in a predetermined direction. If it is required to write a digital "1", then the levels on conduc tors 12 and 13 are reversed in order to reverse the direction of current flow. This is an improvement on the memory cell of Fig. 2 in that it further isolates the area 10 from any inteference or cross-talk from conductor 13.

Fig. 4 shows yet another form that the memory cell may take, including yet further isolation and enabling a simplification in control circuitry to be achieved. In this modification an additional row addressing line 17 is provided, one or other of conductors 11 and 17 being brought high depending upon whether a "0" or "1" is to be written. This involves the provision of an additional semiconductor switch or transistor 18, together with diodes 19 and 20. In this case the line 13 is connected to ground, so that the control circuitry no longer has to determine the potential on that line.

Thus, to write a digital "0" lines 12 and 11 are brought high to render switch 9 conductive together with diode 20. In order to write a "1", conductors 12 and 17 are brought high to render transistor 18 conductive, together with diode 19. The diodes prevent current passing from the line 13 back into the memory cell.

This embodiment also shows the provision of a pre-amplifier 21 in the form of a semiconductor device having its control electrode 22 connected to the sensing line 14 which is itself connected to the ground line 13 via an integrated resistor 23. The amplifying path of transistor 21 is connected between conductor 12 and an output sense line 24.

Further details of how to interconnect such cells into a memory matrix will be found in the art of core memories, possibilities being exemplified by UK Patents No. 2103037, No.

2103038, No. 2106343 and No. 1357864.

Fig. 5 shows in plan and cross-section an alternative arrangement for use in the memory area 10 of Figs. 2 to 4. The area 10 is here shown as a square of magnetic material deposited over a write line 25 upon an insulating layer 26 formed on a semiconductor substrate. The area 27 indicated by dotted lines contains some sensing device e.g. based upon a magnetoresistive or Hall effect and relying if necessary on a change of magnetic field caused by a pulse on the write line 25. As an example, the sensing device may be in the form of an integrated depletion mode MOS FET transistor. The structure of the transistor is not shown as it may vary depending upon the technology chosen for implementation.

However, that portion of area 27 underlying the magnetic material 10 would constitute the base or gate area and connections to this transistor would be made by means including contacts 28 and 29 formed in windows in the insultating layer 26 and connected to source and drain (or collector and emitter) areas.

Claims (14)

1. A random access memory comprising a plurality of memory elements provided by respective magnetic zones of the memory, the memory also including, as an integrated circuit, semiconductor devices arranged to be selectively activated to allow the passage of current adjacent a selected one of said zones to create a magnetic field in that zone for the reading and/or writing of a data bit.

2. A memory according to claim 1, wherein said zones are discrete magnetic elements.

3. A memory according to claim 1, wherein said zones are respective areas of at least one layer of magnetic material.

4. A memory according to claim 1, 2 or 3, wherein the magnetic zones are part of the integrated circuit.

5. A memory according to claim 1, 2 or 3, wherein the magnetic zones are on a carrier placed adjacent to, but removable from, the integrated circuit.

6. A memory according to any one of the preceding claims, wherein the integrated circuit includes semiconductor address decoders.

7. A memory according to any one of the preceding claims, wherein for each memory element there are two addressing semiconductor devices between which there is a conductor for carrying said current adjacent the magnetic element, said devices having control electrodes by which they can be activated to pass said current.

8. A memory according to claim 7, wherein said control electrodes of the two devices are coupled together for the simultaneous application of a control signal.

9. A memory according to any one of claims 1 to 6, and wherein each memory element has two write conductors passing adjacent to the element, each conductor extending between twq semiconductor devices one of which has a control electrode to receive an addressing signal.

10. A memory according to claim 9, wherein the other of the two devices is a diode coupling said conductor to a further conductor to which all the diodes are connected.

11. A memory according to any one of the preceding claims and comprising at each memory element a Hall effect device for use in reading any magnetic field stored at the memory element.

12. A memory according to any one of claims 1 to 11 and comprising at each memory element a field effect device for use in reading the data conveyed by any magnetic field stored at the memory element.

13. A memory according to any one of the preceding claims, wherein the memory elements have respective read amplifier elements integrated in said integrated circuit.

14. A memory substantially as hereinbefore described with reference to Fig. 2, 3, 4 or 5 of the accompanying drawings.