GB2154820A - Photovoltaic relay - Google Patents

Abstract

A high voltage bidirectional output semiconductor field effect transistor (BOSFET) 24 is disclosed which is turned on from the electrical output of a photovoltaic stack 19 which is energized from an LED 21. The process for manufacture of the device is also disclosed. The BOSFET device consists of two lateral field effect transistors 30, 31 formed in an implanted N( - ) region (71) in a P( - ) substrate (70). A diode 35, PNP transistor 36 and resistor 37 are integrated into the same chip containing the lateral BOSFET device to form a solid state relay circuit having characteristics similar to a reed relay. A photovoltaic isolator 20 consists of a stack of semiconductor wafers (320) which are alloyed together by an aluminum silicon alloy foil (43). Each of the wafers consists of a P-type body having P + and N + diffusions on its opposite surfaces. The wafers are stacked with the same forward conduction polarity. Individual photoisolator stacks (345) are sliced from the completed stack to any desired dimension. Each individual stack is mounted with a light source (360), preferably an LED, which is arranged to illuminate the edge of each wafer within the stack. <IMAGE>

Description

SPECIFICATION Photovoltaic relay This invention relates to solid state relays and more specifically relates to a solid state relay employing a novel power MOSFET, a circuit for driving the MOSFET, and a photovoltaic generator for producing the energy for operating the device.

Reed relays are well known electromechanical relays in widespread use. Such relays have a limited lifetime, for example, of the order of about one million operations and are relatively large and expensive. Efforts have been made to replace reed relays by relays employing solid state components. These efforts to date, however, have not produced a unit which is generally competitive, in terms of characteristics or economics, with a reed relay type device.

Thus, commercially available solid state relays almost universally use thyristors (SCRs or triacs) as output devices. Thyristors, however, are poor analogs of an ideal electromechanical switch. For example, thyristors have a minimum 0.6 volt on-state voltage drop, must have polarity reversal to turn them off, require a cone-half cycle turn-off time, and have high holding currents and high reverse leakage currents. Thus, thyristor devices are generally unsatisfactory for applications such as general purpose instrument switching which continues to rely on reed switches. The use of antiparallel connected thyristors is also disclosed in Patent 4,296,331.

Solid state relays employing a MOSFET rather than thyristor form an excellent solid state analog of the ideal conduction/blocking characteristics of a pair of mechanical contacts. Bidirectional conduction MOSFETs can control either a-c or d-c circuits, thereby forming a truly universal contact.

Relays are also known wherein the input energy for switching the transistor is derived from a photovoltaic generator which can be illuminated by a suitable LED or other radiation source in order to produce an output current which causes the switching of the device. Such a relay is shown in United States Letters Patent No. 4,227,098.

When the main power switching device is a power MOSFET, the input current from the photovoltaic source must charge the gate capacitance of the device sufficiently in order to turn the device on. When using photovoltaic generators, commonly a stack of solar cell-type devices, such generators must operate into a high impedance to prevent the diversion of the cell output current away from the MOSFET gate capacitance. The need for a high impedance delays the discharge of the gate capacitance when the input radiation signal to the photo-generator is turned off and the photo-generator output voltage collapses.

Thus, in the circuit of Patent 4,227,098, the main power MOSFET remains on after the input signals terminates for the length of time necessary to discharge the gate capacitance of the power MOSFET into a high impedance circuit. The circuit of Patent 4,227,098 is also sensitive to false firing due to high dV/dt across the power MOSFET terminals since the high dV/dt will charge the drain-to-gate capacitance of the power MOSFET and turn on the relay without an input signal.

Circuits are known to cause more rapid discharge of this gate capacitance for high speed turn-off. Such circuits, however, employ a second photovoltaic source, as is shown in United States Letters Patent No.

4,390,790. The second photovoltaic source or array is used to sense the presence or absence of an input signal and turns on a depletion mode MOSFET when the input illumination is turned off with the turn-off of the input signal. The MOSFET gate capacitance can then discharge more quickly through the conducting depletion mode MOSFET for higher relay turn-off speed.

A photovoltaic isolator may serve as a voltage source which can turn on a power switching device such as a power metal oxide semiconductor field effect transistor (MOS- FET), as shown, for example, in United States Patent 4,227,098, dated October 7, 1980.

The photovoltaic generator which is used in such photovoltaic isolators must have a relatively high output so that immediately upon the energization of the LED, a sufficiently high output will be produced from the photovoltaic stack to provide the gate power needed to drive the gates of control devices such as MOSFETs or bipolar transistors, or the like.

Photovoltaic generators are known which consist of a dielectrically isolated group of photovoltaic generators spaced over the surface of a dielectric support and electrically connected in series with one another. A photovoltaic generator of this type is shown in above-mentioned Patent 4,227,098. Such devices are commercially available. Dielectrically isolated. laterally spaced and series-connected photogenerator cells have the disadvantage that only a small volume, which may be only about 1 mil deep, can be used for collection of generated minority carriers and low lifetime material is used. Also, the electrode system for connecting the devices in series blocks incident light. Consequently, the output current of such devices is limited. Moreover. the devices employ a relatively complex structure and are expensive to manufacture.

Photovoltaic generators have also been made of a stack of series-connected wafer elements which each have PN junctions therein arranged in the same forward conduction direction. These devices can be cut into small slabs which can be edge illuminated to produce an output voltage across terminals connected at the two ends of the stack. A device of this type is shown in U.S. Patent 3,422,527, issued January 21, 1969 to J.M.

Gault and assigned to the assignee of the present application.

An edge illuminated stack of cells is inherently superior to dielectric isolated cells since light can go as deep as desired into the slab and the carriers produced will still be collected even if they are formed, for example, 5 mils from the collecting junction. Moreover, with edge illuminated slabs, the electrical contacts between adjacent units are out of the light path.

In prior art edge illuminated arrangements used as photovoltaic generators, the output current power is limited. Thus, such devices have not been efficient enough to rapidly charge a MOSFET gate capacitance to reach a turn-on threshold voltage in a very short time.

Commonly, the individual wafers of such devices employ an N type body with a shallow P type diffusion to form the collection junction.

Also, relatively thick wafers have been used so that the final stack has a very large height which is difficult to illuminate evenly by a single LED located at the center of the stack.

Different aspects of the invention are set forth in the accompanying claims.

In accordance with a first aspect of the present invention, a novel high voltage bidirectional output switch field effect transistor (BOSFET) structure is provided which employs two laterally integrated field effect transistors having a common central source region. The device is preferably operated by the output of an opto-coupler or photovoltaic isolator circuit.

Two outer drain regions of the device are connected to a central source region through respective enhancement type channel regions which can be inverted to connect the two outer spaced drains to one another through a relatively low resistance conduction path between the two drain electrodes. For example, a resistance path lower than about 2 ohms can be formed. This resistance is generally compatible with most applications using reed relays.

The novel junction configuration employs reduced surface fields of novel configuration.

Thus, with the invention, two channel regions are symmetrically disposed between two depletion regions. A common source connection communicates between the separated drain regions. The channel regions are P regions disposed within an implanted N( -) region each formed atop a P( -) body. Control circuit components are integrated into the BOS FET chip. In one embodiment, a diode and a PNP transistor are formed in the N( -) layer, where the diode is formed in a P type well while the PNP transistor employs the N( -) region as its base region. The two main drain regions are isolated from each other and the N(~) region for the PNP transistor and diode by a deep P + isolation diffusion.

The voltage between the drain regions when the device is off can be of the order of 100 to 1,000 volts to make the relay compatible with general reed relay application. This relatively high voltage is possible since the high output voltage is blocked across the lateral N( -) drift region and never across the gate oxide, whether the relay is controlling a-c or is d-c voltage. Consequently, even though the device output voltage is high, an extremely thin gate oxide can be used to make the gate very sensitive, and so that the device can be turned on by relatively low input voltages with a relatively low current source. As a result, the device can be turned on by the output of an optocoupler or photovoltaic initiator of the type later disclosed.

Thus, the semiconductor switching device, or BOSFET, is a high voltage, relatively low on resistance device, which has an extremely sensitive gate turn-on characteristic.

Note that the device of the invention can be used in any general application and could, for example, serve as a direct replacement for existing thyristors or triacs. The device is also applicable for use as the power switching component of a solid state relay which has the other relay components integrated into the same chip with the power switching element.

A novel solid state relay circuit is also provided which permits the use of a single photovoltaic initiator output for driving the BOSFET into conduction with the circuit having relatively high input turn-on impedance, to limit the requirements of the size of the photovoltaic initiator structure, and a low input turn-off impedance to provide high speed turn-off time.

The novel circuit insures that the gate voltage always instantaneously follows a single photovoltaic generator output. There are two conditions which tend to make the power MOSFET gate voltage deviate from the intended photovoltaic generator output. These are the charge stored on the gate to source capacitance Ciss and the current which can flow under high dV/dt through the drain-togate capacitance CD~G, which falsely charges the gate. It has been recognized that when the power MOSFET gate is connected directly to the photovoltaic generator, it is impossible to distinguish whether a gate signal is properly present from an output of the photogenerator or as a result of the charging of one of the parasitic capacitances Ciss or CD#G.

In accordance with one aspect of the invention, a sensing impedance is connected between the photogenerator and power MOSFET gate which can be used to control auxiliary circuits to quickly eliminate false MOSFET gate voltages. In the preferred embodiment, the sensing impedance is a diode, although other components such as a zener diode, MOSFET, or resistor could be used. By using a separate sensing impedance, it becomes possible to control the auxiliary circuits without the need for a second photogenerator array or pile to enable rapid discharge of the capacitance C55 when the input signal is turned off.

In the preferred embodiment of the invention, the charging circuit from the photovoltaic source output to the gate-to-source circuit of the power MOSFET has a diode connected therein which permits current flow from the photovoltaic source into the gate capacitance and serves as the sensing impedance. A switching transistor circuit is connected in parallel with the gate capacitance Clss of the power MOSFET device and is controlled from an input control terminal connected to the positive output terminal of the photovoltaic source, so that the switching transistor is based on when the photovoltaic source output voltage begins to collapse. Consequently, the relay will switch on as soon as sufficient current is generated from the photovoltaic source to charge the gate capacitance of the power MOSFET to the necessary value.

When, however, the circuit is to be turned off, and when the output voltage of the photovoltaic source reduces below a given value, the switching transistor turns on to place a short circuit across both the gate capacitance of the power MOSFET and across the photovoltaic source, so that both the gate capacitance Clss and the output of the photovoltaic source is short-circuited by the switching transistor.

Therefore, the power MOSFET rapidly turns off.

A novel dynamic a-c clamping circuit is also provided which includes a further switching transistor connected across the gate-tosource electrodes of the power MOSFET. A resistance-capacitance differentiating circuit is also provided and is connected for turning on the second switching transistor to bypass the Miller current through the gate-to-drain parasitic capacitance CD G of the power MOSFET when the dV/dt exceeds a given value. Note that this a-c circuit is connected between the sensing impedance referred to above and the power MOSFET gate electrode.

Note that the novel solid state control circuit which is disclosed as integrated into a single chip with the BOSFET can also be used to drive conventional FET devices.

The novel solid state relay of the invention has many advantages over existing relays in the market, including the electromechanical reed relay. Thus, the novel circuit of the invention can switch either a-c or d-c voltages and has extremely small leakage current when in the off state, which is characteristic of MOSFET type devices. It also has extremely low thermal offset voltage and generates no electromagnetic interference radiation when closed. It is also perfectly resistive in the on state, having no minimum holding current or output voltage. It can thus accurately transmit analog signals. Moreover, it requires as little as 1-2 milliwatts of input power to remain in the "on" state. Furthermore, the device can turn on and off within a few microseconds, as contrasted to the milliseconds required to operate a reed relay or a conventional solid state relay.The load current capacity of the device of the invention is limited only by chip size and junction geometry and can be of the order of 500 to 1,000 milliamperes to satisfy the load current ratings of conventional reed relays. It also has extremely long operating life, in excess of a trillion operations. The overall device can be housed in any desired kind of package, for example a 16 pin DIP housing similar to that now used by reed relays and other conventional solid state relays.

A novel photovltaic stack is also provided which has an exceptionally high output voltage and current while employing relatively few wafers in the stack to make a relatively short height stack. In accordance with one aspect of the invention, a high resistivity P type body is used. A thin N + layer on the body then forms the collection junction in the body. By using a P type body having a thin N + layer to form the collection junction, minority carriers in the P type body are electrons. Such carriers have a higher mobility than holes which are the minority carriers in the conventional N type body.

Preferably, the body material has a high life-time and a resistivity greater than about 5 ohm centimeters, for example, 30 to 50 ohm centimeter material formed from float zone drawn crystal ingots. However, lower resistivity material of 1 to 5 ohm centimeter material which has been used in conventional P type solar cells can also be used. Use of a lower resistivity material was known to produce a higher output voltage but, in the applications of the present invention, it is possible to reduce output voltage in favour of the higher short circuit current obtained by using higher resistivity materials.

For a further feature of the invention, the individual semiconductor wafers are as thin as possible consistent with their being handled without excessive breakage. The novel process of the invention makes the use of such very thin wafers possible since wafer grinding, which applies stress to the stack, may be the last process step before alloying. In fact, the wafers are made thinner than the diffusion length of carriers which are produced in the wafer. This can be done since a novel P + layer is spaced atop the P( -) body to serve as a reflecting layer which reflects minority carriers already collected by the PN junction.

As another feature of the invention, an N + layer of extremely high conductivity is employed on one side of the P( -) body. The use of a very heavily doped N + layer permits the use of an aluminum of aluminum silicon eutectic foil for alloying the stack together without converting the N + layer to a P type region. The N + diffusion is preferably carried out with a phosphorus impurity. The phosphorus will act as a getter for metal ions within the wafer and thus further increases the lifetime of the material.

The reflection P + layer previously described, as well as the N + layer, are preferably formed by well controlled diffusion processes which are well known such as those employing predepositions with POCI3 and BN.

As pointed out above, the stack is connected together by the alloying of a thin aluminum or aluminum eutectic foil between adjacent semiconductor wafers. If desired, however, a metal impregnated epoxy or polyamide can be used to connect together the stack. This would permit the use of shallower junctions and thus an even shorter height stack.

End plates which may be of monocrystalline silicon wafers are also used for the stack to provide a sufficiently long "stand-off" distance to contain saw damage, without damaging a junction and to allow use of conductive epoxy to secure the stack ends to spaced leads without danger of shorting out a junction of an active wafer.

When wafers are processed as described above, their individual outputs are sufficiently high that a stack of less than about twenty devices, and preferably only about ten devices is needed to produce a suitable output current and voltage sufficiently high to rapidly turn on a power MOSFET.

The invention will be further described by way of example with reference to the accompanying drawings, in which: Figure 1 is a circuit diagram of a first embodiment of the novel circuit of the invention which may be integrated into a single chip.

Figure 2 shows the equivalent circuit diagram of the novel bidirectional output semiconductor field effect transistor shown in Fig.

1.

Figure 3 shows the characteristic output voltage as a function of time for the photovoltaic isolator circuit portion of Fig. 1.

Figure 4 shows the current transfer characteristic of the relay circuit of Fig. 1.

Figure 5 is a plan view of a single chip containing the output circuit of Fig. 1 and in particular shows the drain and source metallizing patterns.

Figure 6 is an enlarged view of the wafer surface and of the junctions emerging thereon in the circled region A of Fig. 5.

Figure 7 is an enlarged view of the junction pattern in the dotted enclosed region B of Fig.

5 and shows the PNP transistor and diode junction of the circuit of Fig. 1 integrated into the chip surface.

Figure 8 is a cross-sectional view of Fig. 6 taken across the section line 8-8 in Figs. 5 and 6 and shows the basic junction pattern used for the BOSFET device.

Figure 8a schematically illustrates the manner in which the gate oxide is terminated short of the area of curvature of the polysilicon gate.

Figure 9 is a cross-sectional view taken across the section line 9-9 in Fig. 7 and shows the junction pattern for the transistor and diode of Fig. 1.

Figure 10 is a top view of a portion of the periphery of the chip of Fig. 1 and illustrates the input resistor.

Figure 11 is a cross-sectional view of Fig.

10, taken across the section line 11 - 11 in Fig. 10.

Figure 12 is a plan view of a second embodiment of the BOSFET of the invention.

Figure 13 is a cross-sectional diagram of Fig. 12 taken across section line 13-13 in Fig. 12.

Figure 14 is a second embodiment of a circuit which can be integrated into the chip of Figs. 5, 6, 8, 12 and 13.

Figure 15 is a top view of a single wafer of monocrystalline silicon which is employed for the photogenerating stack of the present invention.

Figure 16 is a cross-sectional view of Fig. 1 taken across the section line 16-16 in Fig.

15.

Figure 1 7 shows the wafer of Fig. 16 after oxidizing its surface and after the formation of a photoresist mask on one surface.

Figure 18 shows the wafer of Fig. 17 after the removal of the oxide layer from one surface of the wafer.

Figure 19 shows the wafer of Fig. 18 after a P type diffusion into the unmasked surface of Fig. 18.

Figure 20 shows the wafer of Fig. 19 after a photoresist mask is applied to one surface and the oxide layers removed from the other surface.

Figure 21 shows the wafer of Fig. 20 after the formation of a very high concentration N + region into the exposed surface of the wafer of Fig. 20.

Figure 22 shows the wafer of Fig. 20 after all oxide is stripped from the wafer.

Figure 23 shows a stack of wafers, each identical to that of Fig. 22, with interposed aluminum eutectic foils and aluminum contacts on the opposite ends of the stack.

Figure 24 shows a single prior art slab or stack having the shape of a parallelepiped which has been cut from the stack of Fig. 23 after the stack has been alloyed together.

Figure 25 is a top view of the photovoltaic isolator of Fig. 24 contained in a plastic housing.

Figure 26 is a cross-sectional view of Fig.

25 taken across the section line 26-26 in Fig. 25.

Figure 27 is a cross-sectional view of the stack of Fig. 24, and shows the extent of saw damage after dicing.

Referring first to Fig. 1, there is shown therein one embodiment of a circuit which can be employed to produce a solid state relay employing the BOSFET and control circuit of the invention. A photoisolator or optocoupler is shown in an enclosed dotted line 20 in Fig. 1. Photovoltaic isolator 20 consists of an LED 21 connected to relay input terminals 22 and 23 and a stack of photovoltaic diodes 19 which produce an output current when illuminated by LED 21. LED 21 or modifications thereof can be excited by either an a-c or d-c input to terminals 22 or 23. In the embodiment shown, a d-c input source will be connected to the terminals 22 and 23 in order to turn the LED 21 on and off. By way of example, the input circuit can be arranged to apply about 10 milliamperes to the LED 21 in order to excite the LED.

The remainder of the circuit of Fig. 1 includes solid state relay components for turning on and off the novel BOSFET 24 which has output terminals 25 and 26. The output terminals 25 and 26 can be connected in either an a-c or a d-c circuit since device 24 has bidirectional conduction characteristics, although the device is a high voltage device.

Thus, the BOSFET device 24 is equivalent to the circuit shown in Fig. 2 of two seriesconnected vertical conduction high voltage MOSFETs 30 and 31 which are shown connected between terminals 25 and 26. Conventional MOSFETs 30 and 31 are turned on and off by a gate to substrate control voltage which is applied between terminals 32 and 33. The structure and process for manufacture of the BOSFET 24 will be later described in detail.

The control components of Fig. 1 for the BOSFET 24 include diode 35, a PNP transistor 36 and an input resistor 37. Resistor 37 has a very high impedance and can typically be a 5 megohm resistor.

The characteristics of the solid state circuit of Fig. 1 when implemented as later described are similar to those of conventional solid state relays and reed relays which are now in common use. By way of example, the circuit characteristics may be such that the circuit can withstand 400 volts peak between terminals 25 and 26 at a maximum load current of about 200 milliamperes. The on resistance between terminals 25 and 26 is about 25 ohms maximum. The device input capacitance is about 60 to 80 picofarads and the device output capacitance is about 40 picofarads.

The capacitance between the input and output circuits is about 2 picofarads. The turn-on time of the circuit with a 5 megohm resistor 37 is approximately 50 microseconds with 10 milliamps drive and its turn-off time is about 90 microseconds. Pickup sensitivity can be increased by increasing the input impedance 37 and the input impedance 37 can also be decreased to increase turn-off speed.

The characteristic of the photovoltaic isolator 20 is shown in Fig. 3 on an exaggerated scale. Thus, as shown in Fig. 3, in about 4 microseconds following the instant that LED 21 turns on, the output voltage of stack 19 rises to approximately 3 volts, when employ ing an input impedance of about 5 megohms.

The drive for the LED in producing the characteristic of Fig. 3 is about 10 milliamperes. The on time will be shortened by employing a higher input impedance 37 or increasing the LED drive. The output voltage of stack 19 will immediately begin to decay with the turn off of the LED 21. This decay would ordinarily take a relatively long time, as shown in dotted lines in Fig. 3, since the gate capacitance of BOSFET 24 slowly discharges in prior art circuits which do not employ the novel diode 35 and PNP transistor 36. With these components in place, however, the PNP transistor 36 will begin to conduct when the output voltage of the stack 19 drops about 0.6 volt less than the MOSFET gate voltage. The input impedance of the circuit is then reduced by the gain of the transistor 36.Thus, as shown in Fig. 3, the stack voltage and gate voltage of BOSFET 24 rapidly collapses to obtain relatively high speed turn-off even though a high input impedance 37 is used for rapid turn-on.

Note that the diode 35 forms a low impedance charging path to the gate circuit of BOSFET 24 to enable highspeed turn-on of the device with the full input impedance of resistor 37 in place. Diode 35 is in fact a sensing impedance which could be replaced by other impedances.

The circuit of Fig. 1 operates as follows: In order to turn on the relay, LED 21 is excited and a charging current flows from the stack 19. This charging current flows through diode 35 to charge the gate capacitance of BOSFET 24. When the threshold voltage of the BOSFET gate capacitance 24 is exceeded (about 1.0 volt), the novel BOSFET turns on and goes full-on at about 2 to 2.5 volts. A conduction path is then established between terminals 25 and 26. Because of the low current and voltage requirements for the BOS FET 24, a relatively small photoisolator stack 19 can turn on the BOSFET 24.

Note that very rapid response is obtained from the photovoltaic stack 19 since its current feeds into the high input impedance circuit defined by resistor 37. Under ordinary circumstances, this same high input impedance defeats rapid turn-off of the device since, in order to turn off the BOSFET, it is necessary to discharge the gate capacitance through the same impedance. In accordance with the invention, however, the very high performance PNP transistor 36, which has the high gain characteristics, for example, of a static induction transistor (SIT) produces a 20:1 improvement in turn-on speed. As will be later seen, the use of a PNP transistor is compatible with the construction of the BOS FET device 24. Note particularly that the transistor 36 is not used to clamp the photovoltaic isolator 20 but follows its output voltage.Once the output voltage of the stack 19 drops to about 0.6 volt below the gate voltage, transistor 36 turns on. The effective input impedance of the circuit is then the resistance of resistor 37 divided by the beta of transistor 36 which is about 400. Consequently, the effective input circuit becomes a relatively low impedance circuit which can relatively quickly discharge the gate capacitance of the BOSFET 24 to relatively quickly turn it off.

The current transfer characteristics of the circuit of Fig. 1 is shown in Fig. 4. In Fig. 4, when the gate voltage, which is the voltage of the positive output terminal of stack 19 minus the forward drop of diode 35, reaches about 1 volt, the BOSFET 24 begins to turn on.

Once approximately 2 volts is reached, the device is almost full on and the load current reached at that time might, for example, be 100 milliamperes. The actual voltage needed to switch BOSFET 24 from a blocking condition to a fully on condition is less than about 3 volts so that the device is operable with TTL circuits.

Figs. 5-11 show the novel BOSFET 24 in a single chip of silicon along with diode 35, transistor 36 and resistor 37. In one embodiment of the invention, and for the ratings which were previously stated for the overall relay, the chip has a thickness of about 15 mils and a length and width of 71 and 92 mils, respectively. Obviously, other sizes can be used.

The surface of the chip is shown in plan view in Fig. 5 which particularly shows the metallizing pattern for the source and drain electrodes of the BOSFET device 24. Obviously, the single chip shown in Fig. 5 will be one of a large number of chips which are simultaneously produced on a relatively large area wafer.

Referring to Figs. 5, 6 and 8, the BOSFET device 24 consists of two main drain electrodes 50 and 51, respectively, shown with cross-hatching for convenience. Enlarged pad regions 52 and 53 are employed to make electrical contact to the drains 50 and 51 by conventional wire bonding techniques.

Drains 50 and 51 will ultimately be connected to the terminals 25 and 26 of Fig. 1 and each consists of a plurality of spaced elongated fingers, such as drain fingers 54 and 55 which are shown in enlarged detail in Fig. 8. Note that the arrangement of Fig. 5 is exaggerated in detail and in the actual device, approximately fifteen fingers will be used for each drain region.

A plurality of elongated source contacts, including source contacts 56 and 57 are disposed laterally across the chip and are disposed symmetrically between spaced pairs of extending drain fingers. The individual source fingers are electrically connected to one another by a frame containing vertical central conductor 65 and surrounding border 66. Consequently, a current path will be defined, for example, from drain 50 to drain 51 and extends from parallel connected fingers 54 and 55, into the source finger 56, and then to the right along source finger 56 to the drain fingers 58 and 59. All drain and source metals may be aluminum. The bottom surface of the chip can have an electrode secured thereto which is connected to the source border 66. A substrate connection pad 60 is provided on the surface of the device of Fig.

5.

The novel interdigitation type pattern described above uniquely enables the use of a high voltage between the drains 50 and 51 without imposing a high voltage across the gate oxides which control the above current conduction path, as will be later described.

Note that parallel conduction path exist for each of the adjacent pairs of drain electrodes and source electrodes shown in Fig. 5. Also provided on the surface of the device of Fig. 5 is a gate pad 61 which enables an easy bonded connection to the gate circuit of the device, as will also be later described. Note further that the substrate pad 60 of Fig. 5 corresponds to the substrate terminal of BOS FET 24 in Fig. 1 which is connected to the negative output terminal of stack 19 while the gate pad 61 corresponds to the anode of diode 35 which is connected to the positive output terminal of stack 19.

As also shown in Fig. 5. a region of the chip area shown within the dotted line area B, and which will be later described, is reserved for the formation of diode 35 and transistor 36, as is schematically illustrated. The surface of the chip will also carry the resistor 37 around its outer periphery in a manner to be later described but not shown in Fig. 5.

The junction pattern which is used for the novel invention is shown in Figs. 6 and 8 in connection with the junction pattern of typical area A of Fig. 5. Note that this pattern will be employed over the full surface of the device of Fig. 5.

Referring now to Figs. 6 and 8, the body of the chip 70 is a lightly doped P( -) region which, as previously stated, has a thickness of about 15 mils and can, for example, have a resistivity of 30 ohm centimeters. The main P(~) region is not in series with the main current path of the device but it determines the breakdown voltage of the BOSFET. A lightly doped N type drift region 71 is then formed in the upper surface of the P( -) body region. The N(~) region 71, sometimes termed a depletion region or drift region, preferably has a depth of about 5 microns and maybe formed by conventional epitaxial growth techniques. Preferably, however, layer 71 is novelly formed by ion implantation.The N(~) drift region 71 must be correctly doped in order to obtain correct depletion in a lateral direction during operation of the device so that the field at the device surface will be equally distributed over the surface. Preferably the N( -) region 71 is formed by a phosphorus implantation, with a dose of about 1 x x 1012 ions per cm2. A subsequent drive for about 18 hours at about 1,200 C. follows the implantation in order to diffuse the phosphorus ions to the depth of about 5 microns, as previously described.

A A P + region 72 which includes strips underlying each of the source strips of Fig. 5 is then formed. The laterial sides of the strips such as strip 72 are preferably more lightly doped than the laterally interior section since these regions will define the channels of the MOSFET device to be formed as will be later described.

In forming the strips, such as strip 72 of Figs. 6 and 8, a field oxide is grown on the surface of region 71 and appropriate narrow strips are opened in the oxide by conventional masking, photolithography and etching. An ion implantation operation then takes place using, for example, boron ions at a relatively heavy dose, for example, 3 X 10'4 ions per cm2. A subsequent drive for about 100 minutes at 1,200 C. follows the implantation to diffuse the boron ions to a depth of 5 microns or greater.

Thereafter, a masking oxide is grown to about 5,000 Angstroms. A second mask is then applied to the oxide surface and windows are etched on the regions which are to receive a gate and N + source strips 82 and 83 to be later described. A gate oxide is then grown on the exposed silicon surface to a thickness of about 700 Angstroms. Polysilicon is next deposited over the full surface to a thickness of about 5,000 Angstroms.

A A third mask is then applied over the polysilicon surface and the desired polysilicon gate pattern is photolithographically formed on the surface and the polysilicon exposed by the mask is etched away to the gate oxide. The exposed gate oxide is also etched away and a relatively low ion dose, for example, 3 x 10'3 ions per cm2 is then applied to form the more lightly doped P type regions 72a and 72b on either side of the P + strip 72 and beneath the gate oxide. A subsequent drive for about 120 minutes at about 1,125 C follows the implantation to diffuse the lightly doped region to a depth of 22 to 3 microns and to grow a masking oxide of approximately 1,500 Angstroms.This masking oxide is used in the formation of the control circuit components, allowing a lightly doped P region to be diffused while preventing the later formation of an N + region in the same window. The use of lighter doped P type regions 72a and 72b will reduce the threshold voltage of the BOS FET, as will be described.

A fourth masking and photolithography operation is then employed to open strips in the field oxide, which strips are above drain regions 80 and 81. A fifth masking and photoli- thography operation is also employed to open strips in the 1,500 Angstrom masking oxide above source regions 82 and 83 and selected areas of the control circuit. N + regions 80, 81, 82 and 83 are then conventionally formed as by diffusion. Regions 80 and 81 are N + strips which underline drain contact fingers 54 and 55. In general, however, the N + regions 80 and 81 are parts of a digitated pattern having the general shape of the drain electrode 54 in Fig. 5. Obviously, a similar pattern underlying the drain electrode 51 is also formed at the same time. N + regions 82 and 83 of Fig. 8 are narrow strips which underlie the source finger 56.Thereafter, a protective reflowed oxide coating is applied to the device surface and a masking operation opens windows for the necessary metallization including source and drain contacts. Note that source contact finger 56 shorts the N + regions 82 and 83 to the center of P + region 72. Clearly, other identical strips underlie the other source strips and are formed within corresponding P type regions, such as the region 72. The N + strips 82 and 83 define channel regions 72a and 72b which can be inverted to form N type channels for an enhancement type MOSFET action.

Elongated polysilicon gates shown as polysilicon gates 90 and 91 in Fig. 8 overlie the channel regions 71a and 72b, respectively.

The oxide thickness beneath the active polysilicon gate region above the channels 72a and 72b is extremely thin and is preferably about 700 Angstroms, thereby to substantially reduce the threshold voltage of the device. The polysilicon gates 90 and 91 are appropriately connected to the gate pad 61 of Fig. 5 and are covered with respective layers 100 and 101 of Silox or a glassy insulation layer which insulates the conductive polysilicon gates 90 and 91 from the source metal strip 56.

It will be noted from the above that the novel process is a DMOS process in that the source and channel regions are self-aligned with the polysilicon gate. Indeed, the process is a triple diffused process if the initial N(~) region 71 is also included.

As shown in Fig. 8a, the polysilicon layer 91 encloses the ends of drain regions such as region 81. In accordance with the invention, the gate oxide above the channel and drain regions such as region 72b is terminated just prior to the point at which the polysilicon gate 91 begins its curvature. This prevents exposure of gate oxide to hot carriers in avalanche breakdown, which occurs preferentially in this region of junction curvature. Damage to the gate oxide is thereby avoided and the ruggedness of the device is increased.

There is also present a conventional field oxide layer 93 in Fig. 8 which extends across the entire surface of the device and which has a thickness, for example, of 1.2 microns.

Using conventional processing techniques, the oxide layers are appropriately opened and the drain electrodes including the drain fingers 54 and 55 and the source electrode strips 56, are deposited as shown. Note that a single metal sheet can be deposited over the surface of the device to make contact to chip surface regions exposed by windows in the masking oxide and the metal can then be masked and cut to the final desired pattern shown, for example, in Fig. 5 and in Fig. 8.

The resulting field effect transistor is a novel lateral bidirectonally conducting field effect transistor (BOSFET) in which relatively high voltage can be connected between drains 50 and 51. When a suitable low voltage, as from a low current source, is applied to the polysilicon gates 90 and 91, the underlying channels 72a and 72b over the full area of the chip of Fig. 5 will be inverted so that current will flow from drains 50 through the inverted channel regions to the source fingers such as source finger 56. The current will then flow outwardly from source finger 56 on the other half of the device again through the inverted underlying channels into the fingers of the drain 51 to establish a current conduction path between the two drain electrodes.

Note that the device is a high voltage device since there is only a very small voltage difference between the polysilicon gate 90-91 and the source finger such as finger 56 which are clamped to a substrate reference voltage.

Therefore, only a few volts will every appear across the thin oxide layer overlying channel regions 72a and 72b, even though a very high voltage appears between the drain electrodes 50 and 51.

Consequently, the novel device of the invention has general application as an a-c or d-c switching power MOSFET. The current rating of the device is, of course, limited only by the effective width of channels 72a and 72b and, in a device of the size described for Fig. 2 of about 71 x 92 mils, the current rating is about 200 milliamperes. The threshold voltage of the device is extremely low in view of the thin gate oxide and is about 1 volt with full turn-on occurring at between 2 and 2 volts. The on resistance of the device is also relatively low and, for example, is less than about 25 ohms.

The spacing between the drain fingers, such as the drainfingers 54 and 55, in the embodiment shown, is about 8 mils center-to-center.

The width of the P + region 72 may be about 1 mil. With an arrangement of this type, it was found that the lateral field stress between any drain region such as regions 81 or 80 to the P + region 72 is very well distributed along the surface of the wafer immediately beneath the field oxide 93. That is to say, the equipotential lines along the surface are evenly distributed. Consequently, local breakdown due to high localized stress at the surface is avoided.

The novel BOSFET structure described to this point is very well adapted to have the diode 35 and PNP transistor 36 integrated therein in the region B of Fig. 5. The junction pattern employed in the region "B" is shown in detail in Figs. 7 and 9. Referring to Figs. 7 and 9, the N( -) region 71 has an enlarged P + diffusion 110 formed therein at the same time that the P + diffusion 72 is made. Note in Fig. 7 that the P + diffusion 72 contains N + strips 82 and 83 which are identical to those which underlie the source strip 56 in Fig. 8 but that those of Fig. 7 underlie the smaller length source strips on either side of region B in Fig. 5. At the time the P type diffusons 72a and 72b are performed, P type diffusions 111 and 112 are also carried out within the N( -) frame exposed within the P + rectangular ring 110 of Fig. 7.An N + contact region 113 and N + region, 114 are also made at the time the N + regions 82 and 83 are formed.

The circuit and junction pattern defined in Fig. 7 is shown in Fig. 9. Thus, the diode 35 is defined by the PN junction formed between P region 111 and the N + region 114. The N + region 114 is electrically connected to the polysilicon gate lattice which is connected to the gate pad 61 in Fig. 5. The anode of diode 35 is electrically connected to the N + region 113 and is then connected to the positive terminal of the input circuit to the relay.

The PNP transistor 36, which is a very high gain transistor, is formed of the P regon 112, the N( -) body 71 and the P(~) body 70.

The collector electrode is electrically connected through the P + enclosing ring 110 which is connected to the P( -) body as shown. Region 110 is then electrically connected to the substrate electrode and to the negative terminal of the photostack input.

Note that the formation of the PNP transistor is ideally suited to the steps used for producing the BOSFET device and a very high gain transistor is inherently formed.

The resistor 37 of Fig. 1 can be implemented on the chip in any desired manner.

Preferably, as shown in Fig. 10, the resistor can encircle the outer periphery of the chip of Fig. 5 and can have a length, for example, from 100 to 200 mils to produce a resistor having a resistance from 1 to 5 megohms.

Resistor terminals are preferably formed under the gate pad 61 and in a P + peripheral region 130 which is formed with the formation of the P + regions 72.

Fig.10 schematically illustrates in dotted line 131 a plan view of an N( -) strip region 132 extending around the chip periphery and having its ends spaced by the P + region 130, as shown in Fig. 11. The stip 132 may have a width, for example, of 15 microns. It is provided with N + end pads 133 and 134 which are electrically connected to suitable terminals 135 and 136, respectively (Fig. 11) which are then connected to appropriate po tential nodes within the chip. Note that the N + regions 133 and 134 relative to the P + region 130 define an inherent zener diode 140 (Fig. 11) having a breakover voltage from 10 to 12 volts.

The novel BOSFET structure of the invention can be implemented in other manners.

Figs. 12 and 13 show a second embodiment of a junction pattern which could be used to implement the BOSFET. The junction pattern of Figs. 12 and 13 should be compared to that of Fig. 8 and similar numerals identify identical parts. The principal difference between the arrangement of Fig. 8 and that of Figs. 12 and 13 is that the drains D1 and D2 are fully interdigitated. The P + region 72 of Fig. 8 is formed of two individual laterally spaced sections 150 and 151 in Fig. 13 with a single N + region 152 disposed centrally between them and connected to the source strip 56. N + regions 160 and 161 are then formed in the P type regions 150 and 151 to define two channels in each of P regions 150 and 151 which cooperate with pairs of polysilicon gates 162-163 and 164-165, respectively (Figs. 12 and 13).Gates 162-163 and 164-165 are periodically connected to gate metal strips 170 and 171 respectively.

Fig. 14 shows a circuit which can be integrated into a BOSFET chip previously described, where the circuit has advantages over that of Fig. 1, in regard to increased turn-off speed and independence from unintended dV/dt turn-on. Components similar to those of Fig. 1 have been given similar identifying numerals in Fig. 14.

The high speed turn-off circuit in Fig. 14 consists of NPN transistor 200, P channel MOSFET 201 and resistor 202. These form a regenerative turn-off circuit which insures that the voltage on the inherent parasitic gate to substrate capacitance C,ss follows, and indeed, pulls down the voltage of stack 19 when LED 21 turns off. Once the stack voltage falls about 0.5 volt below the gate voltage of device 24, P channel MOSFET 201 turns on and C,ss discharges through MOSFET 200 and the base to emitter circuit of NPN transistor 200. This turns on transistor 200 to discharge stack 19 and to keep MOSFET 201 turned on during the discharge process. Note that components 35, 200, 201 and 202 are easily integrated into the BOSFET chip.

The switch-off speed of the switching circuit of Fig. 14 is equivalent to the switching speed of the circuit of Fig. 1 with resistor 37 equal to 470 kilohoms. The circuit of Fig. 14 does not require as low a value for the discharge resistor 37 and therefore does not load down the photovoltaic pile as much. This improves the pick-up sensitivity and turn-on speed of the circuit, as well as the turn-off speed.

Fig. 14 also provides a dynamic a-c clamping circuit for dV/dt suppression. Thus, the distributed drain-to-gate parasitic capacitance CD~G can permit a sufficiently high pulse current to flow under a large enough dV/dt between terminals 25 and 26 to turn on MOSFET 24 in the absence of an input signal at terminals 22 and 23. The suppression circuit includes resistor 210, capacitor 211 and NPN transistor 212, all of which can be integrated into the power MOSFET chip. The resistance-capacitance divider will act to turn on transistor 212 to ground the node between capacitors C,ss and CC G if the dV/dt across terminals 25 and 26 exceeds a given value.

In the circuit of Fig. 14, resistors 202 and 210 are each 1 megohm, and capacitor 211 is 20 picofarads.

Referring to Figs. 15 and 16, there is shown therein the starting wafer for making a photogenerating wafer which will be employed in a stack. The relative dimensions of the wafers of Figs. 15 and 16, as well as later figures, are exaggerated out of proportion for the sake of clarity. The wafer of Fig. 15 may be of high resistivity P type material and the wafer is as thin as possible while being sufficiently strong to resist breakage under careful handling. For example, the wafer of Figs. 15 and 16 is cut from an ingot formed by float zone crystal grown techniques and has a P type resistivity of approximately 50 ohm centi- meters. This is about the highest practical value which can be obtained, However, lower resistivities could be used such as those used for conventional P type solar cell material such as 1 to 5 ohm centimeters.The use of high resistivity material reduces the output voltage of each cell which is ultimately produced from the wafer, but a higher short circuit current will be available.

The wafer employed has a diameter of about 2 inches and has a thickness of about 77 mils which is the thinnest that can be handled in a commercial process without excessive breakage. Larger wafer diameters. for example 3 inches, could be used but the thickness of the larger wafers would have to be increased, for example, to 9 mils.

The top and bottom surfaces of the wafer 320 of Figs. 15 and 16 are oxidized by grown oxide layers 321 and 322 which have a thickness of about 0.4 micron each. A conventional photoresist mask layer 323 is then formed atop the oxide layer 322 in Fig.

17. The wafer is conventionally etched to remove the unmasked oxide layers 322 while leaving the oxide layer 321 intact, as shown in Fig. 18.

Thereafter, a boron containing carrier is deposited at least on the bottom unexposed surface of the wafer 320 in Fig. 18 and boron is then driven into the wafer to form the P + region 330 shown in Fig. 19. The drive used is a 10 hour drive at 1,250 C and until the boron diffuses to a depth of about 1 mil. The drive in Fig. 19 is carried out until a surface resistivity of about 50 ohms per square is reached. Note that the oxide layer 321 acts as a mask during the boron predeposition and drive processes. Also, during the boron drive, a layer of oxide 331 having a thickness of about 1 micron will grow on the bottom surface of the wafer in Fig. 19.

Thereafter, and as shown in Fig. 20, a photoresist layer 332 is applied over the surface of oxide layer 331 and the unmasked oxide layer 321 is removed from the upper surface of the wafer in Fig. 20.

Thereafter, an extremely heavy N + predeposition and drive using a POCI3 source is used to form an N + region 333 in the unmasked surface. To diffuse the N + region 333 into the upper surface of wafer 320, a phosphorus source material is predeposited on the wafer at 1,125or for two hours and until the sheet resistance measured is about 0.8 ohm per square. Thereafter, the impurity is driven for 10 hours at about 1,200 C. This drives the N + region 333 to a depth of about 1 mil. The drive is discontinued when the resistivity at the N + surface of the wafer is about 0.5 ohm per square. Note that this surface resistivity of 0.5 ohm per square is extremely high and is obtained by the presence of greater than about 1 x 1020 phosphorus ions per cubic centimeter at the wafer surface.Indeed, the phosphorus ion concentrations could be as high as 2 x 1020 ions per cc which is approximately the solid solubility limit.

This novel N + diffusion will cause an increase in the lifetime of the P( -) region 320 since the phosphorus ions will act as a getter for metal ions in the silicon body.

Moreover, the process for forming the extremely heavily doped N + region 333 is the last process step for the formation of the junction pattern and will permit the use of an aluminum foil or an aluminum eutectic as the means for alloying together a large number of wafers into a stack. That is, the aluminum will not invert the N + layers 333 to a P type conductivity. Thereafter, and as shown in Fig.

22, all oxides are stripped from the wafer of Fig. 21, as by the use of a 6:1 hydrogen fuoride oxide etch.

The next step in the process is the formation of the stack, wherein as shown in Fig.

23, ten wafers including wafers 340, 341 and 342 are stacked with 1 mil thick foils 343 between them. Different numbers of wafers can be stacked. Foils 343 are preferably aluminum silicon eutectic foils having 88% aluminum and 12% silicon by weight. Eight mil thick end plates 344 and 345 are stacked on the opposite ends of the stack and may be of pure aluminum. Note that if plates 344 and 345 are of aluminum silicon eutectic, the foils immediately adjacent plates 344 and 345 can be dispensed with. Plates 344 and 345 may also be of silicon.

The entire stack is then held under light pressure in any appropriate way and is placed in a suitable apparatus for alloying together the stack. For example, the stack can be placed in a belt furnace using a nitrogen gas purge. The furnace should be at a temperature which will produce an 800 C peak for about 5 minutes over a total travel time through the oven of about 45 minutes. Conventional alloying surfaces can also be used.

After the stack has been alloyed, the stack is diced into slabs of a desired dimension which slabs are formed by cutting through the stack in a direction parallel to its axis. Fig. 24 shows one slab formed from the stack of Fig.

23 and which is cut by any suitable conventional single or multiple blade saw. The slab of Fig. 24 has the typical dimensions of about 20 mils wide by 60 mils long. The slab height is defined by the total height of the ten silicon wafers and connecting foils defining the slab and is approximately 100 mils. Other width and length dimensions and other numbers of wafers per stack could be used. Thus, slab elements of 40 mils by 15 mils might also be used. Note particularly that the 100 mil height produced by the slab of ten wafers is small so that the distance from an illuminating LED which maybe 30 mils from the center of the slab is not very differentaly spaced from any wafer element of the slab.

A photovoltaic slab of Fig. 24 can now be assembled into a photovoltaic isolator as is shown in Figs. 25 and 26. Thus, in Figs. 25 and 26, there is shown a support base 350 which suitably supports the slab 351 of Fig.

24 with electrodes 352 and 353 extending from the top and bottom electrodes 345 and 344, respectively. A conventional LED 360, having electrodes 361 and 362 is preferably an infrared output LED, is then seated on support 350 and is generally centered on the slab but is spaced from the slab by a suffici ent distance, for example 30 mils, to produce the desired dielectric isolation (3,750 volts) between the LED electrodes and the stack electrodes. In Figs. 25 and 26, the housing height will be slightly greater than about 60 mils and the diameter will be slightly greater than about 60 mils and the diameter of the top of the housing will be about 125 mils.

The assembly is then covered with a tran sparent insulative silicone body 370 which is transparent to the LED radiation. The silicone body 370 is coated with a reflective coating 371. Preferably, the coating 371 consists of silicone of the same formulation as body 370, but contains a white reflective material, for example titanium dioxide powder, suspended therein. The use of silicone for suspending powder insures adherence of the coating 371 to the silicone body 370.

Fig. 27 shows a detail of the stack of Figs.

24, 25 and 26, and shows how the damage by the dicing saw is contoured by the end plates 344 and 345. In particular, the plates will have rough-beveled or roughened edges such as edges 401 and 402 in plate 344 and edges 403 and 404 in plate 345. Plates 344 and 345 are thick enough to receive all saw damage and the saw damage does not extend to the junctions in the wafers adjacent the end plates. Plates 344 and 345 also have sufficient thickness or "stand-off" to receive conductive epoxy masses 410 and 411, respectively, which may be used to cement the stack to the end edges of spaced lead frame elements or other electrodes 412 and 413, respectively, without danger of shorting across the active junctions adjacent the end plates.

Although the present invention has been described in connecton with a number of preferred embodiments thereof, many variations and modifications will now become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.

Claims (31)

1. A photovoltaically operated solid state relay circuit comprising: a photovoltaic isolator circuit comprised of an LED means having input energizing terminals, and a photovoltaic pile which is optically coupled to said LED means and is dielectrically isolated therefrom; said photovoltaic having positive and negative output terminals which have a voltage produced therebetween in response to illumination by said LED means; characterized in containing a bidirectional output semiconductor field effect transistor means having first and second output power terminals, a gate terminal and a substrate terminal; a resistor connected across said positive and negative output terminals; a diode having an anode connected to the positive terminal of said photovoltaic pile and a cathode connected to said gate terminal; and a high gain transistor; said high gain transistor having a base connected to said anode of said diode, an emitter connected to said cathode of said diode and a collector connected to said substrate terminal; whereby, the generation of an output from said photovoltaic pile produces sufficient power to turn on said field effect transistor means at high speed and, whereby, when the voltage output of said pile drops below a given value, said high gain transistor turns on to reduce the relay circuit input impedance.

2. A circuit as claimed in claim 1, wherein the bidirectional output semiconductor field effect transistor is capable of withstanding greater than about fifty volts between its output terminals and being switched into conduction in response to the application of a voltage greater than about one volt between said gate and substrate terminals and said resistor has a value greater than 1 00k ohms.

3. The circuit of claim 1 or 2, which is further characterized in that said high grain transistor is a PNP transistor.

4. The circuit of claim 3, which is further characterized in that said field effect transistor means, said diode, said PNP transistor and said resistor are integral components formed in a single chip of silicon.

5. The circuit of claims 1, 2, 3 or 4, which is further characterized in that said field effect transistor means is a metal oxide semiconductor field effect transistor device which has negligible leakage current when off and which has a conduction resistance between its said power terminals of less than about 25 ohms.

6. A bidirectional conduction insulated gate field effect transistor; said transistor comprising a high resistivity body of one of the conduction types; characterized in containing a shallow high resistivity implanted region of the other of the conductivity types formed by implantation and drive into one surface of said body; first and second laterally displaced drain regions of said other conductivity type formed in said implanted region; a central region of said one of the conductivity types formed in said implanted region and located centrally between and spaced from said drain regions; and extending completely through said implanted region; a source region means of said other conductivity type formed in the surface of said central region and defining channels means in said central region which can be inverted from said one conductivity type to said other conductivity type; insulated gate means disposed above the surface of said implanted region and aligned with said channel means, and a gate insulation layer disposed between said channel means and said gate means; first and second drain electrode means connected to said first and second drain regions, respectively; and source electrode means connected to said source region means and to said central region, said source electrode means being disposed adjacent said gate means and insulated therefrom, whereby current can flow bidirectionally between said drain electrode means and through said source electrode when said channel means is inverted by a voltage on said gate means.

7. The device of claim 6, which is further characterized in that said one conductivity type is the P type and wherein said other conductivity type is an N type.

8. The device of claim 6 or 7, which is further characterized in that said implanted region has a depth of about 5 microns.

9. The device of claim 6, 7, or 8, which is further characterized in that said gate insulation layer has a thickness of about 700 Angstroms.

10. The device of claim 6, 7, 8 or 9, which is further characterized in that said source means includes two spaced source regions which define first and second respective channels in said central regions.

11. The device of claim 10, wherein the lateral edges of the lower conductivity portion of said central region are defined by the same diffusion window as said source region means, and are thereby self-aligned to said source region means.

12. The device of any of the claims 6 to 11, which is further characterized in that said drain regions, said central region, and said source region means include parallel elongated strips spaced from one another.

13. The device of claim 12 which is further characterized in including third and forth drain regions disposed on opposite sides of said central region and axially displaced from said first and second drain regions, said central region and its said source region means have a first portion of their length extending from one end of said central region disposed between said first and second drain regions and a second portion of their length extending from the opposite end of their length disposed between said third and fourth drain regions; and third and forth chain electrode means connected to said third and fourth drain regions; said first and second drain electrode means connected to one another to form a first common power terminal; said third and fourth drain regions connected to one another to form a second common power terminal, whereby bidirectional current can flow between said first and second power terminals when said channel means is inverted.

14. The device of claim 13. which is further characterized in that said first and second drain regions are elements of a first digitated drain region having a plurality of fingers substantially identical in cross-section to said first and second drain regions and wherein said third and fourth drain regions are elements of a second digitated drain region having a plurality of fingers substantially identical to said third and fourth drain regions; and wherein a respective central region and source means and channel means is disposed between respective pairs of fingers of said first and second digitated drain regions.

15. The device of any of claims 6 to 14, which is further characterized in including a diode and a PNP transistor integrated with said body; said diode comprising a P type diode region formed within said implanted region and an N type region formed within said P type diode region; said PNP transistor comprising a P type transistor emitter region formed in said implanted region, the base regon of said PNP transistor consisting of said implanted region, and the collector region of said PNP transistor consisting of said P type body.

16. The device of claim 15 which is further characterized in including a resistor integrated into said body; said resistor consisting of an isolated high resistivity strip extending around at least a portion of the outer periphery of the surface of said body.

17. A bidirectional conduction insulated gate field effect transistor characterized in comprising: a high resistivity body of one of the conductivity types; a shallow high resistivity depletion layer of the other of the conductivity types on the top of said body; first and second colinear elongated drain regions of said other cond,uctivity type formed in the surface of said depletion layer, with their adjacent ends spaced from one another; an elongated central region of said one conductivity type formed in the surface of said depletion layer and extending parallel to and laterally spaced from said first and second drain regions and dividing one from the other; a source region means of said one conductivity type formed in the surface of said central region and extending coextensively therewith; an edge of said source region being spaced from an edge of said central region to define an elongated channel means which can be inverted from said other conductivity type of said one conductivity type; a gate insulation layer on the surface of said body and overlying said elongated channel means, and a gate electrode disposed atop said gate insulation layer; and first and second drain electrodes connected to said first and second drain regions, whereby current can flow bidirectionally between said first and second drain electrodes when said channel means is inverted.

18. The device of claim 17 which is further characterized in including an elongated source electrode connected to said source region means; said source electrode being disposed adjacent to but insulated from said gate electrode.

19. The device of claim 17, which is further characterized in that said first and second drain regions are elements of first and second digitated drain regions each having a plurality of parallel fingers identical in crosssection to said first and second regions, respectively; and wherein elongated central regions and source regions identical to said central region and said source region means are disposed between adjacent pairs of drain region fingers in each of said first and second digitated drain regions.

20. A photovoltaic isolator comprising, in combination: an LED radiation sorce; a photovoltaic stack having the form of a rectangular parallepiped and which has series-connected junctions extending to the vertical side of said stack; and a housing for containing said LED and said photovoltaic stack; said LED being spaced from said photovoltaic stack by greater than about 20 mils to obtain a desired dielectric isolation between said LED and said photovoltaic stack; said LED being positioned at the center of one vertical side of said stack and arranged to illuminate at least said one vertical side of said stack; said stack having a relatively short height, less than about 150 mils to improve uniformity in illumination of said at least one vertical side of said stack by said LED; said stack consisting of a vertical stack of a plurality of identical monocrystalline silicon chips; each of said chips comprising a thin body having flat first and second parallel surfaces; characterized in that each of said chips has a main body portion of P type conductivity material; each of said chips having a shallow N type diffusion extending into its said first surface to a uniform depth across substantially the full surface area of said first surface; each of said chips having a shallow P + layer of conductivity substantially higher than that of said P type body extending into its said second surface to a uniform depth across substantially the full surface area of said second surface; a plurality of high conductivity layers disposed between adjacent chips of said stack for mechanically and electrically connecting said stack together with the forward conduction directions of each of said chips being in the same direction; the edge of the junctions between said P type body and said N type layer of each of said chips being exposed along at least one portion of one surface of vertical sides of said stack to enable the edge illumination of said stack; and first and second electrodes on the opposite ends of said stack.

21. The device of claim 20, which is further characterized in that the thickness of each of said chips is less than the average diffusion length of minority carriers which are produced in said body in response to application of radiation to said vertical sides of said chip; said P + layer acting as a reflector to reflect minority change carriers towards the collection junction formed by said P type body and said N type layer.

22. A photovoltaic stack for use in connection with the control of semiconductor devices; said stack consisting of a vertical stack of a plurality of identical monocrystalline silicon chips; each of said chips comprising a thin body having flat first and second parallel surfaces; characterized in that each of said chips has a main body portion of high lifetime P type conductivity material; each of said chips having a shallow N + diffusion layer extending into its said first surface to a uniform depth across substantially the full surface area of said first surface; a plurality of high conductivity layers disposed between adjacent chips of said stack for mechanically and electrically connecting said stack together with the forward conduction directions of each of said chips being in the same direction; the edge of the junctions between said P type body and said N + layer of each of said chips being exposed along at least one portion of one surface of vertical sides of said stack to enable the edge illumination of said stack; and first and second electrodes on the opposite ends of said stack.

23. The device of claim 22, which is further characterized in that each of said chips has a shallow P + diffusion layer of conductivity substantially higher than that of said P type body extending into its said second surface to a uniform depth across substantially the full surface area of said second surface.

24. The device of claim 22 or 23, which is further characterized in that the thickness of each of said chips is less than the average diffusion length of minority carriers which are produced in said bodies in response to application of radiation to said vertical sides of said chips; said P + layer acting as a reflector to reflect minority change carriers toward the collection junction formed by said P type body and said N + layer.

25. The device of claim 22, 23 or 24, which is further characterized in that said N + layer has a conductivity defined by the presence of from about 1 X 1020 to 4 X 1020 impurity atoms per cubic centimeter at said first surface; whereby said N + layer will not be converted to the P conductivity type when alloyed to an aluminum foil.

26. The device of claim 22, 23, 24 or 25, which is further characterized in that said plurality of high conductivity layers consist of a foil having a thickness of about 1 mil and is of a material selected from the group consisting of aluminum, aluminum alloys and an aluminum silicon eutectic.

27. The device of any of claims 22 to 26, wherein said chips have a thickness less than about 9 mils and wherein said stack consists of less than about 15 chips.

28. The device of claim 27, which is further, characterized in that said N + layer is formed from a diffused phosphorus impurity; said phosphorus impurity acting as a getter to metal ions within said P type body. thereby to increase the lifetime of said P type body.

29. A switching circuit for rapidly switching on and rapidly switching off a power metal oxide semiconductor field effect transistor; said power transistor having drain, source and gate electrodes; said switching circuit including an input unidirectional voltage source having first and second terminals switchable between a high and low input voltage, a diode means and a switching transistor having first and second electrodes and a control electrode; characterized in that said first and second terminals of said voltage source, said diode means and said gate and source electrodes of said power transistor are connected in closed series relation with a polarity whereby current from said voltage source can flow through said diode means to charge the gate capacitance of said power transistor when said voltage source is switched to said high voltage; said first and second electrodes of said switching transistor connected to said gate and source electrodes, respectively, of said power transistor; said control electrode connected to said first terminal of said voltage source, whereby said switching transistor is switched on to define a discharge path across said gate capacitance when the voltage of said voltage source is reduced from said high voltage to said low voltage.

30. The relay of claim 29, which is further characterized in including a dynamic clamping circuit connected between said gate and source electrodes of said output transistor; said dynamic clamping circuit being operable to bypass the Miller current in the parasitic drain-to-gate capacitor of said output transistor when the dV/dt of a voltage between said drain and source electrodes exceeds a given value.

31. The relay of claim 30, which is further characterized in that said dynamic clamping circuit includes a series-connected resistor and capacitor and a transistor connected in parallel with said resistor and capacitor; said transistor having a control electrode connected to the node between said resistor and capacitor.