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GB2350931A - Forming vias in low-k dielectric materials using metallic masks - Google Patents

Forming vias in low-k dielectric materials using metallic masks Download PDF

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Publication number
GB2350931A
GB2350931A GB0015731A GB0015731A GB2350931A GB 2350931 A GB2350931 A GB 2350931A GB 0015731 A GB0015731 A GB 0015731A GB 0015731 A GB0015731 A GB 0015731A GB 2350931 A GB2350931 A GB 2350931A
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Prior art keywords
film
silicon oxide
oxide film
forming
metallic
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GB0015731A
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GB0015731D0 (en
GB2350931B (en
Inventor
Tatsuya Usami
Hidemitsu Aoki
Yasuaki Tsuchiya
Shinya Yamasaki
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NEC Corp
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NEC Corp
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    • H—ELECTRICITY
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
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    • H01L21/3105—After-treatment
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    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
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    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
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Abstract

A first HSQ insulating film 3 with a low dielectric constant (lower than that of a silicon oxide film) is formed on a semiconductor substrate. A metal film 5 is formed on a second insulating film 4. Then, the metal film is patterned to a prescribed pattern. An opening is formed in the first and second insulating films using the metal film as a mask.

Description

2350931 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING MULTILAYER
WIRING This invention relates to a method of manufacturing a semiconductor device having multilayer wiring, and, especially, to a method of manufacturing a semiconductor device in which the dielectric constant of an insulation film formed between wiring layers is reduced.
A development of semiconductor integrated circuits with a fine structure has been attained in recent years.
Such a development is particularly significant in the fields of semiconductor integrated circuits containing logical circuits with a multilayer wiring structure. As the interval between metal wiring layers is micro-sized, a wiring capacitance increases which causes a reduction in electric signal speed and deficiencies due to cr?sstalk occur. that is)a phenomenon in which some signals affect- other signals in terms of a noise. For this, studies for reducing the dielectric constant of an insulation film formed between wiring layers have been made.
For example, there is a description of an evaluation of the dielectric constant of Hydrogen
Silsesquioxane (HSQ) in 43rd Apply. Phys. Lett., Related Society Lecture Preprints, No. 2 issue, p654, (26a-N6 "Evaluation of Dielectric Constant of Hydrogen Silsesquioxane (ESQ)"). In this description of the preprints, the specific dielectric constant of an inorganic SOG (Spin on Glass) film formed by curing in a condition of reduced pressure is 2.7. However, when an 02 plasma process is performed, the specific dielectric constant increases up to 3.9. This is, as described in the description of the preprints, because an Si-OH bond is produced in the film in the 02 plasma process whereby a water content in the HSQ film is increased.
It is considered that the above semiconductor is manufactured according to a general process though a production process for the semiconductor device is not described in the above preprints. Here, a conventional process for manufacturing a semiconductor device with multilayer wiring will be explained. Figs. 1A to 1F are sectional views showing a customary method of manufacturing a semiconductor device in sequential order.
In a conventional method of producing a semiconductor device, as shown in Fig. 1A, a first silicon oxide film 101 with a thickness of about 500 nm is first formed on a silicon substrate (not shown). Next, a first aluminum-based metal wiring layer 102 is selectively formed on the first silicon oxide film 101. An HSQ film 103 with a thickness of about 400 rLm is then formed on the first silicon oxide film 101 as a low dielectric constant film by application and annealing.
3 - At this time, the upper surface of the f irst al]aminumbased metal wiring layer 102 is c.oated with the HSQ film 103. A second silicon oxide film 104 with a thickness of about 1400 nm is successively formed on the HSQ film 103.
Then, f or f ormation of a f lat surface, the thickness of the second silicon oxide film 104 is reduced to as thin as about 700 nm by chemically mechanical polishing (CMP). After that, a photoresist 105 is applied to the second silicon oxide film 104. The applied photoresist 105 is exposed and developed so that it has a prescribed pattern.
Next, as shown in Fig. 1B, the second silicon oxide film 104 and the HSQ film 103 are etched using a fluorocarbon-containing gas and utilizing the photoresist 105 as a mask. As a consequence, a contact hole 104a extending to the first aluminum-based metal wiring layer 102 is formed under an opening of the photoresist 105.
After that, an 02 plasma process is performed. At this time, the HSQ film 103 open to the contact hole 104a is exposed to the 02 plasma whereby an Si-OH bond is produced on the surface of the HSQ film 103 which is open to the contact hole 104a. Then, as shown Fig. 1C, the photoresist 105 is removed by a resist releasing solution. At this time, since the surface of the HSQ film 103 open to the contact hole 104a is exposed to the resist releasing solution, a moistened portion 106 with a water content higher than that of the remainder portions is formed on the surface.
Then, as shown in Fig. 1D, a titanium nitride film 4 107 is formed as a barrier metal film on the entire surface. A tungsten film 108 is formed on the titanium nitride film 107 by a blanket CVD method.. In this case, a void 109 is sometimes formed within the contact hole 5 104a.
As shown in Fig. 1E, the tungsten film 108 and the titanium nitride film 107 formed on the second silicon oxide film 104 are removed by a tungsten etch back method whereby the tungsten film 108 and the titanium nitride film 107 only formed within the contact hole 104a are left unremoved.
As shown in Fig. IF, a second aluminum-based metal wiring layer 110 is then formed on the entire surface.
It was confirmed that the semiconductor device produced in this conventional manner had high junction resistance and a connection failure had been produced in the contact hole 104a.
Next, a conventional method of manufacturing a semiconductor device provided with a channel-wiring layer 4 will be illustrated. Figs. 2A to 2F are sectional views showing a conventional method of manufacturing a semiconductor device in sequential order. First, a plurality of base layers (not shown) are formed on a silicon substrate (not shown) and a silicon nitride film 111 with a thickness of about 100 nm is formed on the top of the base layers as shown in Fig. 2A. Then, an HSQ film 11'2 with a thickness of about 500 rm is formed on the silicon nitride film Ill by application and annealing.
- A silicon oxide film 113 with a thickness of about 100rim is formed as a cap film on the HSQ film 112.
Next, as shown in Fig. 2B, a photoresist film 114 is applied to the silicon oxide film 113, Then, it is exposed and developed so that it has a prescribed pattern.
After that, as shown in Fig. 2C, the silicon oxide film 113 and the HSQ film 112 are etched using a fluorocarbon-containing gas and utilizing the photoresist 114 as a mask. As a conseguence, a channel 112a extending to the silicon nitride film 111 is formed under an opening of the photoresist 114.
Then, an 02 plasma process is performed. At this time, the surface of the HSQ film 112 open to the channel 112a is denatured and tends to be moistened. Then, as shown Fig. 2D, the photoresist 114 is removed by a resist releasing solution. At this time, since the surface of the HSQ film 112 open to the channel 112a is exposed to the resist releasing solution, a moistened portion 115 with a water content higher than that of the remainder portions is formed on the surface.
Then, as shown in Fig. 2E, a titanium film 116 with a thickness of about 50 nm is formed as a barrier metal film on the entire surface by a MOCVD method followed by a step of forming a copper film 117 with a thickness of about 500 nm on the entire surface by a CVD method.
As shown in Fig. 2F, the copper film 117 and the titanium film 116 formed on the silicon oxide film 113 are removed by CMP treatment whereby the copper film 117 and the titanium film 116 only formed within the channel 112a are left unremoved.
The capacitance between channel-wiring layers of the semiconductor device prepared in this manner was measured. As a result, the measured capacitance was as same as that of a semiconductor device produced utilizing a formation of a general plasma oxide film. It is considered that this is due to the 02 plasma process.
As a film with a low dielectric constant, a film other than the HSQ film is sometimes used. An instance of using a fluororesin film as the film of a low dielectric constant is described in Monthly Semiconductor World, Feb. (1997), p82-84, entitled "An improvement in etching characteristics for preparing a low dielectric constant due to a fluororesin film is achieved, but a problem of oxygen plasma resistance remains". In this prior art, a via hole is formed using a fluororesin film with a dielectric constant of 2.5 or less composed of a cyclic fluororesin and a siloxane polymer. Figs. 3A to
3D are sectional views showing a customary method of manufacturing a semiconductor device in sequential order. First, as shown in Fig. 3A, a first silicon oxide film 121 is formed on a silicon substrate (not shown). Then, a first aluminum-based metal wiring layer 122 is selectively formed on the first silicon oxide film 121. A liner film 123 composed of a silicon oxide film is formed on the entire surface. Next, a fluororesin film 124 is formed on the liner film 123, and a second silicon oxide film 125 is formed on the fluororesin film 124.
Then, a photoresist 126 is applied to the surface of the fluororesin film 124, followed by exposure and developing to carry out the patterning of the photoresist 126.
Next, as shown in Fig. 3B, the second silicon oxide film 125, the fluororesin film 124 and the liner firm 123 are etched using the photoresist 126 as a mask. As a consequence, a via hole 124a extending to the first aluminum-based metal wiring layer 122 is formed under an opening of the photoresist 126.
After that, an 02 plasma process is performed. At this time, the surface of the fluororesin film 124 open to the via holes 124a is exposed to the plasma. In addition, as shown in Fig. 3C, the photoresist 126 is also removed by a resist releasing solution. In this case, the side wall of the via hole 124a is shaped into a bow-like form by erosion.
Though no remainder steps following the above step are described, it is predicted that the following steps will be performed. As shown in Fig. 3D, a titanium nitride film 129 as a barrier metal film and a second aluminum-based metal wiring layer 127 as a plug are formed on the entire surface. However, a void 128 is probably formed within the second aluminum-based metal wiring layer 127 because of the erosion of the fluororesin film 124.
The reason why the side wall of the via hole 124a is shaped into a bore-like form by erosion is that the fluororesin film 124 is exposed to 02 plasma and then carbon in the film reacts with oxygen to produce C02 gas which causes decomposition of the fluororesin film 124.
As the foregoing shows, even if a film with a low dielectric constant is used, an only insufficient reduction in the dielectric constant can be attained. Also, a problem of formation of a void in a metal layer remains unsolved.
It is an object of at least the preferred embodiment of the present invention to provide a method of manufacturing a semiconductor device having multilayer wiring which can reduce the capacitance between wiring layers and prevent an increase in the junction resistance in an opening such as a contact hole.
According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device having multilayer wiring comprising a step of forming a first insulating film having a dielectric constant lower than that of a silicon oxide film on a semiconductor substrate. The method comprises a step of forming a -metallic film or a second insulating film on the first insulating film, a step of patterning the metallic film or the second insulation f ilm to be a prescribed form and a step of forming an opening in the first insulating film using the metallic film or the second insulating film as a mask. The second insulating film has degrees of moisture absorption and deformation in an oxygen plasma process and exposure to a resist releasing 9 solution equal to or less than those of a silicon oxide f ilm.
With the above, even if a photoresist is used f or patterning the metallic f ilm or second insulating f ilm, oxygen plasma process is performed and a resist releasing solution is applied to release the photoresist, the first insulating f ilm is not exposed to the oxygen plasma and the resist releasing solution at all. A rise in the dielectric constant caused by moisture absorption of the first insulating film is hence prevented and the capacitance between wiring layers can be efficiently reduced. The deformation of the first insulating film is also prevented.
Furthermore, no void is formed within the opening thereby preventing an increase in the junction resistance.
The present invention extends to a semiconductor device comprising:
a first insulating film disposed on a semiconductor substrate and having a dielectric constant lower than that of a silicon oxide film; and a second insulating film disposed on said first insulating film, said second insulating film having degrees of moisture absorption and deformation in an oxygen plasma process and exposure to a resist releasing solution equal to or less than those of a silicon oxide film.
The present invention also extends to a semiconductor device comprising:
an insulating film disposed on a semiconductor substrate and having a dielectric constant lower than that of a silicon oxide film; and a metallic film disposed on said insulating film.
Preferred features of the present invention will now be described, purely by way of example only, with reference 35 to the accompanying drawings, in which:- Figs. 1A to 1F are section views showing a conventional method of manufacturing a semiconductor device in sequential order; Figs. 2A to 2F are sectional views showing another conventional method of manufacturing a semiconductor device 5 in sequential order; Figs. 3A to 3D are sectional views showing another conventional method of manufacturing a semiconductor device in sequential order; Figs. 4A to 4F are sectional views showing a first embodiment of a method of manufacturing a semiconductor device in sequential order; Figs. 5A to 5F are sectional views showing another method of manufacturing a semiconductor device In sequential order; Figs. 6A to 6E are sectional views showing a second embodiment of a method of manufacturing a semiconductor device In sequential order; Figs. 7A to 7E are sectional vies showing another method of manufacturing a semiconductor device In sequential order; Figs. 8A to 8F are sectional views showing a third embodiment of a method of manufacturing a semiconductor device in sequential order; and Figs. 9A to 91 are sectional views showing another method of manufacturing a semiconductor device in sequential order.
Figs. 4A to 4F are sectional views showing a first embodiment of a method of manufacturing a semiconductor device in sequential order.
In this embodiment, as shown in Fig. 4A, a first silicon oxide film I with a thickness of, for example, about 500 nm is formed on a silicon substrate (not shown). A first aluminum-based metal wiring layer 2 is selectively formed on the first silicon oxide film 1. An HSQ film 3 having a thickness of, for example, about 400 nm. is formed on the first silicon oxide film I by application and annealing as a film whose dielectric constant is lower than that of a silicon oxide film. At this time, the upper surface of the first aluminum-based metal wiring layer 2 is coated with the HSQ f ilm 3. A second silicon oxide film 4 with a thickness of, for example, about 1,400 run is then formed on the HSQ film 3. Then, for formation of a flat surface, the thickness of the second silicon oxide film 4 is reduced to as thin as, for example, about 700 nm by CMP (chemically mechanical polishing). A tungsten silicide film 5 with a thickness of, for example, about 100 nm is then formed on the second silicon oxide film 4 by sputtering. After that, a photoresist 6 is applied to the tungsten silicide film 5. The applied photoresist 6 is exposed and developed so that it has a prescribed pattern.
Next, the tungsten silicide film 5 is etched by a chlorine-containing gas using the photoresist 6 as a mask as shown in Fig. 4B. This allows an opening 5a of the tungsten silicide film 5 to be formed under an opening of the photoresist 6. Then, an 02 plasma process is performed and the photoresist 6 is exposed to a resist releasing solution whereby it is removed.
After that, the second silicon oxide.film 4 and the HSQ film 3 are etched using fluorocarbon gas and using the tungsten silicide film 5 as a mask. In this case, volatile WF6 gas or SiF4 gas is produced, so the deposition of the tungsten silicide film 5 is restricted. As a consequence, as shown in Fig. 4C, a contact hole 4a extending to the first aluminum-based metal wiring layer 2 is formed under the opening 5a of the tungsten silicide film S.
Then, as shown in Fig. 4D, a titanium nitride film 7 with a thickness of, for example, about 50 nm is formed on the entire surface as a barrier metal film while the tungsten silicide film 5 is retained. A tungsten film 8 with a thickness of, for example, about 500 nm is successively formed on the titanium nitride film 7.
Next, as shown in Fig. 4E, the tungsten film 8, the titanium nitride film 7, and the tungsten silicide film 5 which are formed on the second silicon oxide film 4 are removed by metal CMP. Therefore, the tungsten film 8 and the titanium nitride film 7 formed only within the contact hole 4a are left unremoved.
As shown in Fig. 4F, a second aluminum-based metal wiring layer 9 is formed on the entire surface. After this, the same processes as above are repeated to complete the production of a semiconductor device having multilayer wiring.
In this embodiment, the HSQ film 3 which tends to increase in the water content by an 02 plasma process is not exposed when the 02 plasma process is carried out. Therefore, no void is produced within the contact hole 4a whereby any increase in the junction resistance is prevented and any increase in the dielectric constant of the HSQ film 3 caused by an increased water content can be avoided.
Next, another method or manufacturing a semiconductor device will be explained with reference to Figs. 5A to 5F, which are sectional views showing the method or manufacturing a semiconductor device in sequential order.
In this method,. as shown in Fig. 5A, a lower layer insulating film 11 is formed on a semiconductor substrate (not shown). An HSQ film 12 with a dielectric constant lower than that of a silicon oxide film is formed as an interlayer insulating film on the lower layer insulating film 11 by application and annealing. A silicon nitride film 13 with a thickness of, for example, about 100 nm and a silicon oxide film 14 with a thickness of, for example, about 400 nm are deposited in this order on the HSQ film 12. It is noted that the silicon nitride film has degrees of moisture absorption and deformation in an oxygen plasma process and exposure to a resist releasing solution equal to or less than those of a silicon oxide film. Then, a photoresist 15 is deposited on the silicon oxide film 14 and is subjected to photolithography in which a channel-wiring pattern is 14 - formed on the photoresist.
Next, as shown in Fig. 5B, the silicon oxide film 14 is etched by reactive ion etching (RIE) using C4F8 gas, CO gas and Ar gas and using the photoresist 15 as a mask.
S in this case, the selective ratio of the etching rates of the silicon nitride film 13 and silicon oxide film 14, that is, SiN: S'02 is designed to be 1: 20, whereby the silicon nitride film 13 functions as an etching stopper. As a consequence, a wiring channel 14a with a depth of about 400 nm is formed.
Next, an 02 plasma process is performed and, as shown in Fig. 5C, the photoresist 15 is removed using an organic solvent. At this time, the ESQ film 12 is protected by the silicon nitride film 13.
As shown in Fig. 5D, the silicon oxide film 14, the silicon nitride film 13, and the ESQ film 12 are etch backed at the same etching rates by RIE using CEF3 gas.
The silicon oxide film 14 is entirely removed and at the same time a channel 12a with a depth of, for example, about 400 run is formed in the ESQ film 12.
The etching for forming the channel 12a may be performed by the following method. First, the silicon oxide film 14 and the silicon nitride film 13 are etched at almost the same etching rates until the silicon nitride film 13 is penetrated through. Then, the silicon oxide film 14 is etched at a etching rate greater than that of the silicon nitride film 13. In this case, since the HSQ f ilm 12 is etched at the same rate as that of the silicon oxide film 14, the HSQ film 12 is etched making use of the already patterned silicon nitride film 13 as a hard mask. When not an HSQ film but a layer insulating film having a high selective ratio against the silicon nitride film 14 is formed as a film with a low dielectric constant, the silicon nitride film 14 is formed into a film with such a thickness that the film can be thoroughly removed with the formation of a pattern on the silicon nitride film 13. Such measures enable it possible to perform more accurate patterning of the silicon nitride film 13 and HSQ film 12 by RIE.
Next, as shown Fig. SE, a titanium film 16 with a thickness of, for example, 20 nm is deposited as a barrier metal film on the entire surface by sputtering.
In succession, an aluminum film 17 with a thickness of, for example, 800 nm is deposited as a wiring metal film on the titanium film 16 by sputtering.
Then, as shown in Fig. 5F, the aluminum film 17 and the titanium film 16 formed on the silicon nitride film 13 are removed by chemically mechanical polishing (CMP) while leaving these films 16, 17 unremoved only within the channel 12a.
In this method, since the HSQ film 12, which tends to increase in the water content by the 02 plasma process, is not also exposed in the 02 plasma process, a rise in the dielectric constant with an increase in water content is prevented.
Incidentally, in this method, the silicon - 16 nitride film 13 is used as an insulating film which has degrees of moisture absorption and deformation in an oxygen plasma process and exposure to a resist releasing solution equal to or less than those of a silicon oxide film. It is particularly preferable that the silicon nitride film be a plasma silicon nitride film. A plasma silicon oxide film or a plasma silicon oxynitride film may be used as such an insulating film.
Next, a second embodiment of the method will be explained. Figs. 6A to 6E are sectional views showing a method of manufacturing a semiconductor device in sequential order.
In this embodiment, as shown in Fig. 6A, a first silicon oxide film 21 with a thickness of, for example, O.1pn is formed on a semiconductor substrate (not shown). An HSQ film 2 2 having a thickness of, for example, 0.41Am and a dielectric constant lower than that of a silicon oxide film is formed on the first silicon oxide film 21 by application and annealing. A second silicon oxide film 23 with a thickness of, for example, 0.05pm is deposited on the HSQ film 22. Furthermore, a W (tungsten) film 24 with a thickness of, for example, 0.051Lm is deposited on the second silicon oxide film 23. In succession, a photoresist 25 is applied to the tungsten film 24 and is subjected to photolithography in which a channel-wiring pattern is formed on the photoresist.
Next, as shown in Fig. 6B, the tungsten film 24 is patterned by dry etching using the photoresist 25 as a mask. After that, the photoresist 25 is released by ashing treatment of 02 plasma and treatment using an organic alkali solution. At this time, the dry etching residue is also removed. In'this releasing treatment,, the surface of the HSQ film 22 is not damaged because it is coated with the second silicon oxide film 23.
AS shown in Fig. 6C, the second silicon oxide film 23 and the HSQ film 22 are etched in an oxide film dry etching condition using the tungsten film 24 as a mask until the first silicon oxide film 21 is exposed. This allows a channel 22a for a damascene method to be formed. Here, the damascene method comprises a step of forming an insulating film formed with a hole or a channel in a prescribed area and a step of installing wiring layer in the hole or the channel.
Next, as shown in Fig. 6D, a TiN film 26 with a thickness of, for example, 0.05pm is formed on the entire surface as a barrier metal film. In succession, a copper film 27 is deposited on the TiN film 26 as a metal wiring film.
As shown in Fig. 6E, the copper film 27, TiN film 26 and tungsten film 24 on the second silicon oxide film 23 are removed by CMP whereby the copper film 27 and TiN 26 formed only within the channel 22a are left unremoved.
Also, in this embodiment, since the HSQ film 22, which tends to increase in the water content by the 02 plasma process, is not also exposed in the 02 plasma 18 - process, a rise in the dielectric constant with an increase in water content is prevented.
Incidentally, as a method for burying the copper film 27 and TiN film 26 a CVD method, sputtering method, and plating method utilizing a sputtering or CVD method for seeding and the like are exemplified. Among these methods, a CVD method having high coating characteristics and burial characteristics is most desirable. In the case of using a sputtering method, it is necessary to reflow at a high temperature.
Also, a silicon nitride film may be adopted as the base film instead of the first silicon oxide film 21. In this case, the etching is performed in the dry etching condition of high selectivity between a silicon oxide, film and a silicon nitride film thereby terminating the etching just before it reaches the base film in a highly controlled condition.
As the second silicon oxide film 23, a plasma silicon oxide film which has reduced water content therein and which is formed using high density plasma, e.g. an ECR method, is preferred.
Furthermore, given as examples of the exposure for patterning of the photoresist 25 are exposure to light, e.g. I-line or G-line, exposure to excimer laser, e.g.
KrF, ArF, exposure to EB (Electron Beam), and exposure to X-ray.
A TiN film or a titanium film may be formed instead of the tungsten film 24.
19 - Next, another method of manufacturing a semiconductor device will be explained. Though the WSi film is used in the first embodiment and the tungsten film in the second embodiment as the mask for forming the contact hole or the chan'nel in the HSQ film, a TiN film may be used as the mask. It is noted that almost no etching deposit is produced when a WSi film or a tungsten film is used, but some etching deposits tend to be produced when the TiN film is used. This method has an object of avoiding such a drawback. Figs. 7A to 7E are sectional views showing a method of manufacturing a semiconductor device in sequential order.
In this method, as shown in Fig. 7A, a first silicon oxide film 31 is formed on a semiconductor substrate (not shown). An HSQ film 32 with a dielectric constant lower than that of a silicon oxide film is formed on the first silicon oxide film 31 by application and annealing. A second silicon oxide film 33 is deposited on the HSQ film 32. Furthermore, a TiN film 34 is deposited on the second silicon oxide film 33 and in succession a third silicon oxide film 38 with a thickness of, for example, 0.05pm is formed on the TiN film 34. In this case, the film thickness of the third silicon oxide film 38 is preferably designed to be the sum of those of the second silicon oxide film 33 and HSQ film 32. A photoresist 35 is applied to the third silicon oxide film 38 and is subjected to photolithography in which a channel-wiring pattern is formed on the photoresist by patterning.
Next, as shown in Fig. 7B, the third silicon oxide film 38 is patterned using a fluorine-type etching gas and using the photoresist 35 as a mask. Furthermore, the TIN film 34 is patterned using a chlorine-type etching gas and using the photoresist 35 as a mask. After that, the photoresist 35 is released by an 02 plasma process and so on. At this time, the surface of the HSQ film 32 is not damaged because it is coated with the second silicon oxide film 33.
As shown in Fig. 7C, the third silicon oxide film 38 is removed by a fluorine-containing etching gas. At the same time, the second silicon oxide film 33 and the HSQ film 32 are etched to the extent the first silicon oxide film 31 is exposed. A channel 32a for a damascene method is thus formed. In this method, the TiN film 34 is used as the mask when theHSQ film 32 is etched.
However, no deposit is produced by the dry etching because the TiN film 34 is not directly etched.
The subsequent production steps are the same as in the second embodiment. Specifically, as shown in Fig. 7D, a TiN film 36 and in succession a copper film 37 are deposited on the entire surface.
As shown in Fig. 7E, the copper film 37, TiN film 36, and TiN film 34 on the second silicon oxide film 33 are then removed by CMP whereby the copper film 37 and TiN film 36 formed only within the channel 32a are left - 21 unremoved. A damascene wiring is thus completed.
Next, a third embodiment of the method will be explained. In this embodiment, one wiring layer is formed by a single damascene method and then other one or-more wiring layers are formed by a dual damascene method. Figs. 8A to 8F are sectional views showing a method of manufacturing a semiconductor device in sequential"order according to the third embodiment.
In this embodiment, as shown in Fig. SA, a first silicon oxide film 41, an HSQ film 42, a second silicon oxide film 43, a TiN film 46, and a copper film 47 are formed on a semiconductor substrate (not shown) in the same manner as in the second embodiment.
Next, as shown in Fig. 8B, an interlayer HSQ film 49 with a thickness of, for example, 1.2pn and a dielectric constant lower than that of a silicon oxide film is formed on the entire surface by application and annealing. A third silicon oxide film 50 with a thickness of, for example, 0.05tm and in succession a tungsten film 51 with a thickness of, for example, 0.05pm are deposited on the interlayer HSQ film 49. A first photoresist 52 is applied to the tungsten film 51 and a pattern for a plug hole with a diameter of, for example, 0.3tm is formed in the first photoresist 52. Next, the tungsten film 51 is patterned using the patterned first photoresist 52 as a mask. The first photoresist 52 is then released and removed by an 02 plasma process and so on. The third silicon oxide film 50 and the interlayer HSQ film 49 are dry etched using the tungsten film 51 as a mask to the extent that the interlayer HSQ film 49 is etched to a depth of 0.7pm, whereby a plug hole 49a is 5 formed.
As shown in Fig. 8C, a second photoresist 53 inwhich a wiring pattern with a width of, for example, 0.6pm is formed above the plug hole 49a and its vicinity is formed on the tungsten film 51.
Next, as shown in Fig. 8D, the tungsten film 51 is patterned using a chlorine containing etching gas and using the second photoresist 53 as a mask. The third silicon oxide film 50 and the interlayer HSQ film 49 are subsequently dry-etched using, as a mask, the tungsten film 51 with an enlarged opening until the interlayer HSQ film 49 is etched to a depth of 0.5pm. At this time, the plug hole 49a which has been already formed is more deepened and extends to the copper film 47. The second photoresist 53 is then removed by an 02 plasma process and so on.
As shown Fig. 8E, a TiN film 54 is formed as a barrier metal film on the entire surface and a copper film 55 which will be a metal wiring film is formed on the TIN film 54.
As shown in Fig. 8F, the copper film 55, the TiN film 54 and the tungsten film 51 on the third silicon oxide film 50 are removed by CMP, whereby dual damascene wiring structure is completed.
In this embodiment, though the lower wiring layer is the copper-wiring layer, it may be an aluminum-wiring layer. In such a case, easy fine processing is attained and an aluminum film can be patterned by-dry etching. An application of the interlayer HSQ film after the aluminum-wiring layer as the lower layer is processed therefore brings about a flat surface. Particularly, this eliminates the CMP step.
Next, another method of manufacturing a semiconductor device will be explained. Figs. 9A to 91 are sectional views showing a method of manufacturing a semiconductor device in sequential order according to this method.
I' In this method, as shown in Fig. 9A, a first silicon oxide film 61, an HSQ film 62, a second silicon oxide film 63, a TiN film 66 and a copper film 67 are formed on a semiconductor substrate (not shown) in the same manner as in the second embodiment.
Next, as shown in Fig. 9B, an HSQ film with a dielectric constant lower than that of a silicon oxide film is applied and annealed and this steps are repeated several times, whereby an interlayer HSQ film 69 with a thickness of, for example, 1.2pm is formed on the entire surface. A third silicon oxide film 70 with a thickness of, for example, 0.05pn is then deposited on the interlayer HSQ film 69. A TiN film 71 with a thickness of, for example, 0- 05Lm is further deposited on the third silicon oxide film 70. In succession, a fourth silicon oxide film 76 with a thickness of, for example, 0.05pm is - 24 deposited on the TiN film 71. In this case. the film thickness of the fourth silicon oxide film 76 is preferably designed to be the sum of those of the third silicon oxide film 70 and the interlayer HSQ film 69.
After that, a first photoresist 77 is applied to the surface of the fourth silicon oxide film 76 and a pattern for a plug hole with a diameter of, for example. 0.3pin is formed in the first photoresist 77. Then, the fourth silicon oxide film 76 is patterned using the patterned first photoresist 77 as a mask to the extent that the fourth silicon oxide film 76 is etched to a depth of 0.7pm. A pore 76a is thus formed. The first photoresist 77 is then released and removed by an 02 plasma process and so on.
AS shown in Fig. 9C. a second photoresist 78 in which a wiring pattern with a width of, for example, 0Agm is formed above the pore 76a and its vicinity is formed on the fourth silicon oxide film 76. Next, as shown in Fig. 9D. the fourth silicon oxide film 76 is patterned using a fluorine containing etching gas and using the second photoresist 78 as a mask. At this time, the pore 76a which has been already formed is more deepened and extends to the TiN film 71. Further, the TiN film 71 is dry-etched using a chlorine containing gas and using, as a mask, the fourth silicon oxide film 76 with an enlarged opening. The second photoresist 78 is then removed by an 02 plasma process and so on.
AS shown Fig. 9E, the third silicon oxide film 70 and the interlayer HSQ f ilm. 69 are subsequently dryetched using a fluorine-containing gas and using, as a mask, the patterned TiN film 71 until the interlayer HSQ film 69 is etched to a depth of 0.7pm. Thus a plug hole 5 69a is formed.
As shown in Fig. 9F, the TiN film 71 is patterned by etching using a chlorine containing gas and using the fourth silicon oxide film 76 as a mask.
Then, as shown in Fig. 9G, the third silicon oxide film 70 and the interlayer HSQ film 69 are etched using a fluorine containing gas until the layer HSQ film 69 is etched to a depth of 0. 5pm. At this time, the fourth silicon oxide film 76 is removed and, at the same time, a channel with a reverse convex shape which extends to the copper film 67 is transferred to the interlayer HSQ film 69, whereby the plug hole 69a is deepened.
Next, as shown in Fig. 9H, a TiN film 74 is formed as a barrier metal film on the entire surface and a copper film 75 which will be a metal wiring film is formed on the TiN film 74.
As Fig. 91 shows, the copper film 75, the TiN film 74 and the TiN film 71 formed on the third silicon oxide film 70 are removed by CMP. A dual damascene wiring structure is completed.
The foregoing embodiments all use an HSQ film as a film with a dielectric constant lower than that of a silicon oxide film. Besides the above film, a porous film with a terminal bond group of Si-H or Si-CH3, an organic film such as an organic SOG film, a fluororesin film, an amorphous carbon fluoride film and a polyimide film, and the like may be used.
A metal film for masking may be formed directly on 5 a film with a low dielectric constant.
There are no limitations to metal materials for wiring layers or to burying metal materials and any effect of the present invention does not depend on these materials. When a copper film is used, a TiN film is deposited as a base layer for the copper film, the copper film is filmed by sputtering, CVD, or plating, and then the copper film and TiN film disposed in a prescribed area are removed.
In the case where an aluminum-type film such as an aluminum film, an Al-Cu alloy film or an Al-Si-Cu alloy film is used, a titanium film is desirably used as a barrier film.
Furthermore, examples of the metal film used as a mask include a WSi film, a tungsten film, a titanium film, a TiN film and an aluminum film and the like.
A method for removing these metals is not limited to CMP, but an etchback method may be used.
27 Each feature disclosed in this specification (which term includes the claims) and/or shown in the drawings may be incorporated in the invention independently of other disclosed and/or illustrated features.
The text of the abstract filed herewith is repeated below as part of the specification.
A first insulating film with a dielectric constant lower than that of a silicon oxide film is formed on a semiconductor substrate. Next, a metal film is formed on the first insulating film. Then, the metal film is patterned to a prescribed pattern. An opening is formed in the first insulating film using the metal film as a mask.
28

Claims (12)

_CLAIMS
1. A method of manufacturing a semiconductor device having multilayer wiring, comprising the steps of:
forming on a semiconductor substrate an insulating film having a dielectric constant lower than that of a silicon oxide film; forming a metallic film on said insulating film; patterning said metallic film to a prescribed form; and forming an opening in said insulating film using said metallic film as a mask.
2. A method according to Claim 1 wherein said insulating film is formed of insulating material selected from the group consisting of Hydrogen Silsesquioxane, organic spinon glass, fluororesin, amorphous carbon fluoride, and polyimide.
3. A method according to Claim 1 wherein said insulating film is formed of a porous film having a terminal bond group of Si-H or Si-CH3.
4. A method according to any preceding claim, wherein said metallic film is formed of material selected from the group consisting of tungsten silicide, tungsten, titanium, titanium nitride, and aluminum.
5. A method according to any preceding claim, further comprising the steps of: forming a silicon oxide film on said insulating film between said step of forming said insulating film and said step of forming said metallic film; and patterning said silicon oxide film using said metallic film as a mask between said step of patterning said metallic film and said step of forming said opening in said insulating film.
29
6. A method according to any preceding claim, further comprising a step of burying a conductive film in said 5 opening -
7. A method according to Claim 6, wherein said step of burying said conductive film comprises the steps of:
forming a metallic barrier film on the side wall and the bottom of said opening; and forming a metallic wiring film on said barrier film.
8. A method according to Claim 7, wherein said barrier film is a TiN film.
9. A method according to Claim 7 or 8, wherein said wiring film is formed of material selected from the group consisting of copper, aluminum, and aluminum alloy.
10. A method according to Claim 6 wherein said step of burying said conductive film comprises the steps of: forming a conductive film on the entire surface of the device; and removing said metallic film and a portion of said conductive film to leave only said conductive film within said opening.
11. A semiconductor device comprising:
an insulating film disposed on a semiconductor substrate and having a dielectric constant lower than that of a silicon oxide film; and a metallic film disposed on said insulating film.
12. A method of manufacturing a semiconductor device substantially as herein described with reference to Figures 4A, to 4F, 6A to 6E, or BA to 8F of the accompanying drawings.
GB0015731A 1997-06-27 1998-06-25 Method of manufacturing semiconductor device having multilayer wiring Expired - Fee Related GB2350931B (en)

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Application Number Priority Date Filing Date Title
JP17205697A JP3390329B2 (en) 1997-06-27 1997-06-27 Semiconductor device and manufacturing method thereof
GB9813799A GB2326765B (en) 1997-06-27 1998-06-25 Method of manufacturing semiconductor device having multilayer wiring

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Citations (7)

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US4357203A (en) * 1981-12-30 1982-11-02 Rca Corporation Plasma etching of polyimide
GB2137808A (en) * 1983-04-06 1984-10-10 Plessey Co Plc Integrated circuit processing method
US5442237A (en) * 1991-10-21 1995-08-15 Motorola Inc. Semiconductor device having a low permittivity dielectric
EP0680084A1 (en) * 1994-04-28 1995-11-02 Texas Instruments Incorporated Self-aligned via using low permittivity dielectric
EP0822586A2 (en) * 1996-07-30 1998-02-04 Texas Instruments Inc. Improvements in or relating to integrated circuits
EP0834916A2 (en) * 1996-10-07 1998-04-08 Motorola, Inc. Method for manufacturing a semiconductor structure comprising regions formed with low dielectric constant material

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3846166A (en) * 1971-09-25 1974-11-05 Hitachi Ltd Method of producing multilayer wiring structure of integrated circuit
US4357203A (en) * 1981-12-30 1982-11-02 Rca Corporation Plasma etching of polyimide
GB2137808A (en) * 1983-04-06 1984-10-10 Plessey Co Plc Integrated circuit processing method
US5442237A (en) * 1991-10-21 1995-08-15 Motorola Inc. Semiconductor device having a low permittivity dielectric
EP0680084A1 (en) * 1994-04-28 1995-11-02 Texas Instruments Incorporated Self-aligned via using low permittivity dielectric
EP0822586A2 (en) * 1996-07-30 1998-02-04 Texas Instruments Inc. Improvements in or relating to integrated circuits
EP0834916A2 (en) * 1996-10-07 1998-04-08 Motorola, Inc. Method for manufacturing a semiconductor structure comprising regions formed with low dielectric constant material

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