GB2316519A

GB2316519A - Selectively called wireless receiver

Info

Publication number: GB2316519A
Application number: GB9717565A
Authority: GB
Inventors: Tomoshi Sone
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 1996-08-21
Filing date: 1997-08-19
Publication date: 1998-02-25
Anticipated expiration: 2017-08-19
Also published as: GB9717565D0; HK1009035A1; AU3518997A; JPH1066125A; CN1175864A; AU718997B2; GB2316519B

Abstract

A selectively called wireless receiver includes a wireless unit 2 for demodulating a received wireless signal and a control unit 1 for allowing a message to be displayed and allowing an alarm sound to be generated based on the signal demodulated by the wireless unit. The control unit 1 has a integrated circuit and an external memory 11. The integrated circuit includes a CPU 100, a decoder 101, an internal memory 102 and a transfer gate 106. The decoder 101, internal memory 102 and transfer gate 106 are connected mutually by an internal address/data bus S. The external memory 11 is connected to the transfer gate 106 in the integrated circuit 10 by an external address/data bus T. The transfer gate 106 is opened only when the external memory 11 is accessed, thus reducing noise.

Description

SELECTIVELY CALLED WIRELESS RECEIVER BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a selectively called wireless receiver. More specifically, the present invention directed to a technique for connecting a CPU and an external memory by an address/data bus line in a control unit of such a receiver.

2. Description of the Related Art Fig. 1 is a block diagram showing a construction of a main section of a conventional selectively called wireless receiver and a circuit diagram in a control unit 5. The conventional selectively called wireless receiver includes the control unit 5 and a wireless unit 6. The control unit 5 is constructed by an integrated circuit 30 and an external memory 31 composed of an external ROM 32 and an external RAM 33. The integrated circuit 30 includes a CPU 300, a decoder 301, and an internal memory 302 composed of an internal ROM 303 and an internal RAM 304.

Each of the internal ROM 303 and internal RAM 304 which form the internal memory 302 in the integrated circuit 30 has a capacity capable of storing data to realize the basic functions which are necessary to process received information. An address/data bus X for connecting the internal memory 302 and decoder 301 is connected the shortest length so as not to exert an influence to various characteristics of the selectively called wireless receiver.

On the other hand, each of the external ROM 32 and external RAM 33 which form the external memory 31 has a capacity capable of storing data to realize other functions necessary in the selectively called wireless receiver and data to realize additional functions.

The address/data bus X is led out from the integrated circuit 30 and connected to the external memory 31. Information is transmitted and received through the address/data bus X between the decoder 301 and any one of the devices among the internal ROM 303, internal RAM 304, external ROM 32, and external RAM 33 selected by selection signals g, h, j, and k. The selection signals g, h, j, and k are supplied from the decoder 301. The decoder generates these selection signals g, h, j, and k in accordance with information from the CPU 300.

In the conventional selectively called wireless receiver constructed as mentioned above, when the data to be processed is transferred to the internal memory 302 through the address/data bus X during the reception of the information, the data is also transmitted to the outside of the integrated circuit 30 through the address/data bus X. As a result, the signal corresponding to the data transmitted to the outside of the integrated circuit 30 becomes a noise-generating source.

Therefore, some inconveniences such that the noise-generating source exerts an adverse influence to the wireless unit 6 and remarkably deteriorates various characteristics of the wireless unit 6 have been occurred often.

To solve the above conventional problems, according to "Individual selectively called receiver" disclosed in the Japanese Laid Open Patent Disclosure (JP-A-Heisei03-244223), a line which is at risk of becoming a noise generating source is connected to be as short as possible. Thus, the influence that is exerted on a peripheral circuit by high frequency noises derived from the noise-generating source are reduced. However, since there is also a limitation when wiring the line as short as possible, the influence by the high frequency noises is not always eliminated.

According to "Selectively called wireless receiver" disclosed in the Japanese Laid Open Patent Disclosure (JP-A-Heisei 04-045620), a resistor is serially inserted in a potentially noise-generating line. Thus, high frequency noise currents are attenuated. However, space is limited in a selectively called wireless receiver, and since an area to install the resistor onto a circuit board is necessary, the arrangement is difficult to miniaturize and costs rise.

SUMMARY OF THE INVENTION It is, therefore, an object of at least the preferred embodiments of the present invention to provide a selectively called wireless receiver in which deterioration of the performance characteristics of the receiver unit is reduced and the receiver has excellent reliability and production rate.

According to a first aspect of the present invention, there is provided a selectively called wireless receiver comprising: a wireless unit for demodulating a received wireless signal; and a control unit for allowing a message to be displayed and allowing an alarm sound to be generated based on the signal demodulated by the wireless unit, wherein the control unit includes a processing unit formed as an integrated circuit, internal storage means which is provided in the integrated circuit and is connected to the processing unit via an internal bus, switching means connected to the processing unit by the internal bus and controlled by the processing unit, and external storage means which is provided externally of the integrated circuit and is connected to the switching means via an external bus.

The selectively called wireless receiver, may be arranged by further comprising: control means for controlling a opening and closing of the switching means, and wherein the control means makes the switching means close only when the processing unit accesses to the external storage means to thereby connect the internal bus and the external bus.

A selectively called wireless receiver, according to a preferred embodiment of the present invention, is featured by comprising: a wireless unit for demodulating a received wireless signal; and a control unit for allowing a message to be displayed and allowing an alarm sound to be generated based on the signal demodulated by the wireless unit, wherein the control unit includes a processing unit formed as an integrated circuit, internal storage means which is provided in the integrated circuit and is connected to the processing unit via an internal bus, switching means connected to the processing unit by the internal bus, external storage means which is provided on an outside of the integrated circuit and is connected to the switching means via an external bus, and selection signal producing means for producing a selection signal to select either one of the internal storage means and the external storage means in accordance with a signal from the processing unit, and the switching means is closed when the internal storage means is selected by the selection signal from the selection signal producing means and is opened when the external storage means is selected.

In the selectively called wireless receiver according to the first and second aspect of the present invention, it is preferable that the switching means is formed in the integrated circuit. It is also desirable that the switching means comprises transfer gates for width of the internal bus.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a conventional selectively called wireless receiver; Fig. 2 is a block diagram showing a construction of a selectively called wireless receiver according to an embodiment of the present invention; and Fig. 3 is a timing chart for explaining the operation of the embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will now be described hereinbelow by way of example only with reference to the drawings.

Fig. 2 is a block diagram showing a construction of a selectively called wireless receiver according to an embodiment of the present invention and a circuit diagram in a control unit 1. The selectively called wireless receiver comprises a control unit 1, a wireless unit 2, a loudspeaker 3, and an LCD (Liquid Crystal Display) 4. The control unit-l is further made up of an integrated circuit 10, an external memory 11 comprising an external ROM 12 and an external RAM 13, and an amplifier 14. The integrated circuit 10 includes a CPU 10-0, a decoder 101, an internal memory 102 comprising an internal ROM 103 and an internal RAM 104, an OR circuit 105, a transfer gate (TG) 106, and an LCD driver 107.

The control unit 1 controls the whole selectively called wireless receiver. The wireless unit 2 amplifies a wireless signal received by an antenna (not shown) , and then demodulates the amplified wireless signal. The demodulated signal derived from the wireless unit 2 is supplied to the decoder 101 in the control unit 1. The loudspeaker 3 generates an alarm sound based on a signal derived from the amplifier 14 in the control unit 1. The LCD 4 displays received information based on a signal derived from the LCD driver 107 in the control unit 1.

The decoder 101 is connected to the CPU 100 through a bus R. The LCD driver 107 is connected to the CPU 100 through a bus Q. The CPU 100 executes processes to realize various functions as a selectively called wireless receiver. The decoder 101 informs the CPU 100 about a fact that this selectively called wireless receiver itself was called. The decoder also-decodes the demodulated signal derived from the wireless unit 2 and outputs the decoded signal to an address/data bus S. Further, the decoder 101 supplies a ringing signal to the amplifier 14, thereby the loudspeaker 3 is driven. Furthermore, the decoder 101 generates selection signals a, b, c, and d based on the information from the CPU 100 and then supplies the selection signals a, b, c, and d to the internal ROM 103, the internal RAM 104, the external ROM 12, and the external RAM 13, respectively. The selection signals c and d are also supplied to the OR circuit 105.

The address/data bus S corresponds to an internal bus of the present invention. An input/output terminal on one side of the transfer gate 106 and the internal memory 102 (internal ROM 103 and internal RAM 104) are also connected to the address/data bus S in addition to the abovedescribed decoder 101. The address/data bus S is connected via the shortest path so as not to exert an influence to various characteristics of the selectively called wireless receiver. The transfer gate 106 is composed of a switching element which is on/off controlled by a signal from the OR circuit 105. The external memory 11 (external ROM 12 and external RAM 13) and an input/output terminal 120 on the integrated circuit 10 are connected by an address/data bus T.

The input/output terminal 120 is connected to the input/output terminal on the other side of the transfer gate 106. The address/data bus T corresponds to the external bus of the present invention. The address/data bus T is electrically connected to the address/data bus S in the integrated circuit 10 through the transfer gate 106.

The internal ROM 103 and internal RAM 104 in the integrated circuit 10 are the same as the internal ROM 303 and internal RAM 304 in the conventional selectively called wireless receiver, respectively. The external ROM 12 and external RAM 13 are the same as the external ROM 32 and external RAM 33 in the conventional selectively called wireless receiver, respectively.

In the device (any one of the internal ROM 103, internal RAM 104, external ROM 12, and external RAM 13) the transmission and reception of information to/from the decoder 101 is determined by the selection signals a, b, c, and d which are outputted from the decoder 101.

Referring now to Fig. 3, information that is supplied to the address/data buses S and T in accordance with the states of the above-described selection signals a, b, c, and d will be explained Since the selection signals a, b, c, and d are set to the high ("H") logic level, namely, are made active, each device of the internal ROM 103, internal RAM 104, external ROM 12, and external RAM 13 recognizes that the device itself was selected and executes the input/output process of the information.

The information "e" which is necessary for each device of the internal ROM 103, internal RAM 104, external ROM 12, and external RAM 13 is supplied to the address/data bus S.

When the selection signal c or d is set to the "H" level, namely, is made active, the transfer gate 106 is opened by the signal from the OR circuit 105. Thus, the address/data bus T and address/data bus S are electrically connected.

Therefore, the information "e" supplied to the address/data bus S is transmitted as information "f" to the address/data bus T. The external memory 11 is, consequently, connected to the decoder 101.

On the other hand, when the selection signal c and d is set to the low ("L") logic level, namely, is made non-active, the transfer gate 106 is closed by the signal from the OR circuit 105.

Thus, the address/data bus T and address/data bus S are electrically disconnected. Therefore, no signal is supplied to the address/data bus T.

As mentioned above, in the selectively called wireless receiver according to the embodiment of the present invention, the transfer gate 106 is provided in the integrated circuit 10, which controls the flow of the signals between the address/data bus S in the integrated circuit 10 and the address/data bus T led out to the outside of the integrated circuit 30. Then, when the external ROM12 and external RAM13 are not accessed, the interval of both the buses is electrically shut off by the transfer gate 106.

In accordance with the selectively called wireless receiver with employment of the abovedescribed arrangement, because the number of peripheral parts is not increased, noise reduction can be realized without limitation on installation.

Also, the reliability and productivity can be improved.

As described above, the internal bus of the integrated circuit and the external bus can be disconnected by the switching means and when the processes are completed only in the integrated circuit, the internal bus and external bus are disconnected by the switching means. Thus, since the internal bus is perfectly closed in the integrated circuit in terms of a circuit, various characteristics of the wireless unit are not deteriorated. Since the switching means is formed in the integrated circuit, the number of peripheral parts is not increased. Consequently, the reliability and production rate can be improved.

Each feature disclosed in this specification (which term includes the claims) and/or shown in the drawings may be incorporated in the invention independently of other disclosed and/or illustrated features.

The text of the abstract filed herewith is hereby repeated as part of the specification.

A selectively called wireless receiver includes a wireless unit 2 for demodulating a received wireless signal and a control unit 1 for allowing a message to be displayed and allowing an alarm sound to be generated based on the signal demodulated by the wireless unit. the control unit 1 has an integrated circuit and an external memory 11. The integrated circuit includes a CPU 100, a decoder 101, an internal memory 102 and a transfer gate 106. The decoder 101, internal memory 102 and transfer gate 106 are connected mutually by an internal address/data bus S. The external memory 11 is connected to the transfer gate 106 in the integrated circuit 10 by an external address/data bus T. The transfer gate 106 is opened only when the external memory 11 is accessed.

Claims

What is claimed is:

1. A selectively called wireless receiver comprising: a wireless unit for demodulating a received wireless signal; and a control unit for allowing a message to be displayed and allowing an alarm sound to be generated based on the signal demodulated by said wireless unit, wherein said control unit includes a processing unit formed in an integrated circuit, internal storage means which is provided in said integrated circuit and is connected to said processing unit via an internal bus, switching means connected to said processing unit by said internal bus and controlled by said processing means, and external storage means which is provided on externally of said integrated circuit and is connected to said switching means via an external bus.

2. The selectively called wireless receiver according to Claim 1, further comprising: control means for controlling opening and closing of said switching means, wherein said control means makes said switching means close only when said processing unit requires access to said external storage means, thereby connecting said internal bus and said external bus.

3. The selectively called wireless receiver according to Claim 1, further comprising selection signal producing means for producing selection signals to select either one of said internal storage means and said external storage means in accordance with a signal from said processing unit, and wherein said switching means is closed when said internal storage means is selected by the selection signals from said selection signal producing means and is opened when said external storage means is selected.

4. The selectively called wireless receiver according to any preceding claim, wherein said switching means is formed in said integrated circuit.

5. The selectively called wireless receiver according to any preceding claim, wherein said switching means comprises transfer gates for width of said internal bus.

6. A selective calling wireless receiver substantially as herein described with reference to the accompanying drawings.