GB2335101A

GB2335101A - Tunable MOS linear transconductance amplifier usable in cascade and with triple-tail or quadri-tail cell

Info

Publication number: GB2335101A
Application number: GB9905154A
Authority: GB
Inventors: Katsuji Kimura
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 1998-03-05
Filing date: 1999-03-05
Publication date: 1999-09-08
Also published as: JPH11251848A; GB9905154D0

Abstract

A MOS linear transconductance amplifier is provided, which has superior transconductance linearity within the whole input voltage range and that is readily formed on LSIs. This amplifier is comprised of (a) a MOS differential pair formed by first and second MOSFETs whose sources are coupled together; an input voltage being applied across gates of the first and second MOSFETs; (b) a constant current source/sink for driving the MOS differential pair; the constant current source/sink being connected to the coupled sources of the first and second MOSFETs; (c) a third MOSFET connected to a drain of the first MOSFET; the third MOSFET serving as a load of the first MOSFET; (d) a fourth MOSFET connected to a drain of the second MOSFET; the fourth MOSFET serving as a load of the second MOSFET; (e) gates of the third and fourth MOSFETs being commonly applied with a constant voltage; and (f) a differential output voltage proportional to the input voltage being derived from, the drains of the first and second MOSFETs. Some of the amplifiers may be cascade-connected, thereby forming a multi-stage amplifier, in which the amplification or attenuation rate can be optionally adjusted by changing the number of the cascading stages. A triple-tail or quadritail cell may be further cascade-connected to the MOS differential pair.

Description

2335101 9 e TUN"LE MOS LINEAR TWWSCONDUCTANCE AMPLIFIER

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a linear transconductance amplifier comprised of Metal-Oxide Semiconductor Field-Effect Transistors (MOSFETs) and more particularly, to a MOS linear tran s conductance amplifier having superior transconductance linearity within the whole operating input voltage range, which is suitable to semiconductor Large-Scale Integrated circuits (L!Is).

2. Description of the Prior Art

Fig. 1 shows a conventional MOS linear t rans conductance amplifier, which was disclosed in the paper entitled "Current 15 Additional Type CMOS OW, the 1994 spring meeting of THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS (IEICE), written by Kenj i Toyota, Akira Hyogo, and Keitaro Sekine, March 1994 (lecture No. A-36).

In Fig.. 1, the conventional amplifier is comprised of a MOS differential pair formed by two n-channel MOSFETs M101 and M102 whose sources are coupled together, and a quadritail cell formed by four n- channel MOSFETs M105, M106, M107, and M108 whose sources are coupled together. The coupled sources of the MOSFETs M101 and M102 are connected through a constant current sink 102 (current value: lss) to a supply voltage line supplied with a power 1 supply voltage of V55. The MOS dif f erential pair is driven by the constant current Iss.

The MOSFETs M101 and M102 have a same ratio (W/L) of the gate width W to the gate length L, which Is Kd times as large as that of a unit MOSPET, where Kd is a cbnstant equal to or greater than unity (i.e., Kd k 1).. Gates of the MOSFETs M101 and M102 constitute an input terminal pair, across which an Input voltage Vi. is applied.

An n-channel MOSFET M103 serves as a load of the MOSFET M101. The MOSFET M103 has a sodrce connected to a drain of the MOSrET M101, a drain connected to a supply voltage line applied with a power supply voltage of VD1), and a gate applied with a dc constant voltage or bias voltage Vs. The voltage Vs is generated by a constant voltage source 110.. An nchannel MOSFET M104 serves as a load of the MOSFET M102. The MOSFET M104 has a source connected to a drain of the M05FET M102, a drain connected to the supply voltage line Of VDD, and a gate applied with the same dc, constant voltage or bias voltage Vs as that of the MOSF.ET M103.

The MOSFETs M103 and M104 have asame ratio (W/L) of the gate width W to the gate length L, which is K, times as large as that of a unit MOSFET, where K,. is a constant equal to or greater than unity K1t 1).

Thesources of the fourn-channelMOSFETsMI05, M106, M107, 1 and M108 constituting the quadritail cell are connected to the supply voltage line of V55 through a constant current sink 104 (current value: ctlss) The quadritail cell is driven by the constant current ctIss generated by the constant current sink 104, 1 where cc is a constant. The constant current cxI$5 may be termed the tail current for the-quadritail cell.

Gates of the MOSFETs M105 and M108 are connected to the drains of the MOSFETs M101 and M102, respectively. The gate of the MOSFET M105 is applied with a f irst output voltage V01 generated at the drain of the MOSFET M101. The gate of the MOSFET M106 is applied with a second output voltage V02 generated at the drain of the MOSFET M102. The difference (V01 - V02) between the first and second output voltages VOI and V02 (i.e., the differential output voltage of the MOS differential pair) is used as an input voltage of the-quadritail cell.

The MOSFETs M105 and M108 have a same ratio (W/L), which is Yc. times as large as that of a unit MOSFET, where K, is a constant equal to or greater than unity (i.e., K, 2: 1). The MOSFETs M106 and M107 have a same ratio (W/L), which is K$ times as large as that of a unit MOSFET,' where K. is a constant equal to or greater than unity (i.e., K, k 1).

An n-channel MOSFET M109 and a constant current sink 103 (current value: Iss/2) constitUte a control voltage generator circuit for generating a dc constant voltage (i.e., a control voltage Vc) to be applied to the quadritail cell. The MOSFET M109 has a source connected to one terminal of the constant current sink 103, a drain connected to the supply voltage line Of VDD, and a gate applied with the bias voltage VB f rom the constant voltage source 110.

The control voltage vc Is equal to the source voltage of the M10SFET M109. In other words, the control voltage vc is generated at the source of the MOSFET M109. The gates of the MOSFETs M106 and M107 of the quadritail cell, which are commonly connected to the source of the MOSFET M109, are applied with the control voltage Vc.

in the above-described paper, it is disclosed that the conventional MOS linear transconductance amplifier of Fig. 1 has the above-described circuit configuration and that each of two output currents (1d#a + 1q) and (1d,2 + 1q) is proportional to the applied input voltage Vi,,. Howekier, no relationship of the input voltage V:L,, with the first and second output voltages V01 and V02 is disclosed. Therefore, the operation principle of the conventional amplifier of Fig. 1 cannot be known from the paper. As a result, the reason why each of the two output currents (ICM.1 + I.) and (Idm2 + Iq) is proportional to the input voltage V,,,, in other words, the operation principle of the conventional amplifier is unable to be understood.

i The inventor of the present invention, K. Kimura, analyzed the operation principal of the conventional MOS linear transconductance amplifier of Fig. 1 and confirmed that this amplifier was actually capable of linear operation.

Additionally, it was found that the circuit configuration of Fig.

corresponded to one case where ilf the MOSFETs M105, M106, M107, and M108 have the same ratio (W/L) equal to that of the unit MOSFET (i.e., K. = K., = 1), the MOSFETs M101 and M102 have the same ratio (W/L) twice as large as that of the unit MOSFET (i.e., Kd - 2), the MOSFETS M103, M104, and M100 have the same ratio (W/L) four times as large as that of the unit MOSFET (i.e., K, 4), and the constant current tziss of the constant current sink 104 is equal to half the constant current Iss of the constant current sink 102 (i.e., 1/2).

As a consequence, it can be said that the set of values of the circuit parameters in the circuit configuration of Fig. 1 is one of the countless possible sets of values of the circuit parameters.

With the conventional MOS linear transconductance 20 amplifier of Fig. 1, as explained abo7e', the ratios (W/L) of the MOSFETs M101, M102, M103, M104, M105, M106, M107, M108, and M109 need to be set to be equal to, or twice or four times as large as that of the unit MOSFET and at the same time, the current values of the constant current sinks 103 and 104 need to be set to be -5- half as large as that of the constant current sink 102. Thus, if the conventional MOS linear. tzansconductance amplifier of Fig. 1 is reali zed on LS1s, a problem of the chip area increase and the characteristic or performance fluctuation" of the circuit 5 tends to occur.

Also, a MOS linear trans conductance amplifier Is an essential function block in analog signal processing. Recently, there has been the increasing strong need that the transconductance value of the MOS linear transconductance lo amplifier is changeable or tunable.

SUMMARY OF THE 1NYENTION

Accordingly, an object of the present invention to provide a MOS linear t rans conductance amplif ier that has superior trans conductance linearity within the whole operating input voltage range and that is suitable to LS1s.

Another object of the present Invention to provide a MOS linear transconductance amplifier that is suitable to LSIs.

Still another object of the present invention to provide a MOS linear trans conductance amplifier capable of tuning of the t rans conductance value without changing the circuit parameter values.

The above objects together with others not specifically mentioned will become clear to those skilled Ln the art from the following description.

A MOS linear transconductance amplifier according to a first aspect of the present invdntion is comprised of (a) a MOS differential pair formed by first and secondMOSFETs whose sources are coupled together; an input voltage being applied across gates of the first and second MOSFETs; (b) a constant current source/sink for driving the MOS.differential pair; the constant current source/sink being connected to the coupled sources of the first and second MOSFETs; (c) a third MOSFET connected to a drain of the first MOSFET; the third MOSFET serving as a load of the first MOSFET; (d) a fourth MOSFET connected to a drain of the second MOSFET; the fourth MOSFET serving as a load of the second MOSPET; (e) gates of the third and fourth MOSFETs being commonly applied with a constant voltage; and (f) a differential output voltage proportional to the input voltage being derived from the drains of the first and second MOSFETs.

With the MOS linear t ransconductance amplifier according to the f irst aspect of the present invention, the MOS differential pair formed by the first and second MOSFETs is driven by the constant current and at the same time, the input voltage is applied across the gates of the f irst and second MOSFETs. Theref ore, each of the drain currents of the f irst and second MOSFETs has a square-law characteristic with respect to the input voltage.

j On the other hand, since the third and fourth MOSFETs are respectively provided as the loads of the first and second MOSFETs, the drain currents of the' kirst., and second MOSFETs are respectively converted to the first and second output voltages 5 which are generated at the dralns of the first and second MOSFETs. At this current-te-voltage conversion, the first and second output voltages thus generated are square-root- compressed with respect to the input voltage due to the square-law characteristic of the third and fourth MOSPETs. Because the gates of the third and f ourth MOSFETs are commonly applied with the constant voltage, the square-root-compression for the first and second output voltages is carried out in the same manner.

Accordingly, the difference Cetiween the first and second output voltages of the MOS differential pair (i.e., the differential output voltage of the MOS differential pair) is proportional to the input voltage. In other words, the differential output voltage of the MOS differential pair (i.e., (the differential output veltage of the MOS linear trans conductance amplifier) has a linear characteristic with respect to the input voltage.

The superior linearity of the dif f exential output voltage of the MOS linear transcondvctance amplifier according to the first aspect is seen within the whole range of the operating input voltage, i.e., the whole operating input voltage range. This is 0 1 because the square-law characteristic of a MOSFET is utilized in the amplifier according to the first aspect.

In a preferred embodiment of the amplifier according to the first aspect, a ratio (W/L) if a gate width W to a gate length L of each of the first and second MOSFETs is K, times as large as that of a unit MOSFET, where K,, is a constant equal to or greater than unity. A ratio (W/L) of a gate width W to a gate length 1 of each of the third and fourth. MOSFETs is K2 times as large as that of the unit MOSFET, where K2 is a constant equal to or greater than unity- in this embodiment, there is an additional advantage that an amplifier or attenuator can be readily realized by changing the values of the constants K, and/or K2, and that the amplification or attenuation rate of the amplifier or attenuator can be optionally determined.

A MOS linear transconductance amplifier according to a second aspect of the present invention is comprised of (a) first to n-th MOS differential pairs; eaclk of which is formed by two MOSFETs whose sources are coupled together, where n is an integer equal to or greater than two; (b) first to n-th constant current sources/sinks for driving the f irst to n-th MOS differential pairs, respectively; (c) first to n-th pairs of load MOSFETs serving as loads of the first to n-th MOS differential pairs, respectively; (d) an input voltage being applied across gates of the two MOSFETs -g- t f orming the f irst MOS dif f erential pair; (e) f irst to (n-1) -th differential voltages being applied to the second to n-th MOS differential pairs, respectively; each of the first to (n-l) th differential voltages being applied across gates of the two MOSFETs forming a corresponding one of the second to n-th MOS differential pairs; (f) a constant voltage being commonly applied to the gates of the two MOSFETs forming each of the first to n-th pairs of load MOSFETs; and (g) a differential output voltage proportional to the input voltage being derived from drains of 10 the two MOSFETs forming the n-th M05'differential pair.

The MOS linear transconductance amplifier according to the second aspect of the present invention has n amplifier stages cascade-connected, each of the amplifier stages has a same configuration as that of the MOS linear transconductance amplifier according to the f irst;aspect of the present invention. Therefore, because of the same reason as shown in the above explanation about the MOS linear trans conductance amplifier according to the first aspect, the differential dutput voltage of the MOS linear transconductance amplifier according to the second aspect has a linear characteristic with respect to the input voltage within the whole operating input voltage range.

With the MOS linear trans conductance amplifier according to the second aspect, there is an additional advantage that the amplification or attenuation rate can be optionally adjusted by 1 - changing the value of n, because this amplifier comprises the cascade- connected n amplifier stages.

In a preferred embodiment of the amplifier according to the second aspect, the constant voltages commonly applied to the gatesof the MOSFETs forming the first to n-th pairs of loadMOSFETs are equal to one another.

In this embodiment, there is an additional advantage that the circuit configuration is simplified.

In another 'preferred of the amplifier according to the second aspect, a ratio (WIL) of a gate width W to a gate length L of each of the MOSFETs forming the first to n-th MOS differential pairs is K, times as large as that of a unit MOSFET, where K, is a constant equal to or greater than unity; and a ratio (W/L) of a gate width W to a gate length L of each of the first to n-th pairs of load MOSFETs is X2 times as large as that of the unit MOSFET, where K2 is a constant equal to or greater than unity.

In this embodiment, there is an additional advantage that an amplifier or attenuator can be rebdily realized by changing the values of the constants K, and/or K2, and that the amplification or attenuation rate of the amplifier or attenuator can be optionally set.

A MOS linear trans conductance amplifier according to a third aspect of the present invention is comprised of (a) a MOS different i a I pair formed by first and second MOSFETs whose sources are coupled together; an input voltage being applied across gates of the first and second MOSFETs; a hrst output voltage being generated at a drain of the first MOSFET; a second output voltage being generated at a drain of the second MOSFET; (b) a first constant current source/sink for driving the MOS differential pair; the first constant current source/sink being connected to the coupled sources of the f i,rst' and second MOSPETs; (c) a third MOSFET connected to a drain of the first MOSFET; the third MOSFET serving as a load of the f irst M05FET; (d) a f ourth MOSFET connected to a drain of the second MOSFET; the fourth MOSFET serving as a load of the secondMOSFET; (e) a triple-tail cell formedby fifth, sixth, and seventh MOSFETs whose sources are coupled together; the triple-tail cell being driven. by a second constant current source/sink; (f) a first constant voltage being commonly applied to gates of the third and fourth MOSFETs; (g) the first output voltage of the MOS differential pair being applied to a gate of the fifth MOSFET, and the second output voltage of the MOS differential pair being applied to a gate of the sixth MOSFET, (h) a second constant voltage being applied to a gate of the seventh MOSFET; and (i) a differential output current proportional to the input voltage being derived fromthe drains of the fifth and sixth MOSFETs.

The MOS linear trans conductance amplifier according to the third aspect of the present Invention has a configuration obtained by cascadeconnecting a MOS triple-tail cell to the.MOS linear trans conductance amplifier according to the first aspect.

Therefore, the differential output voltage of the MOS differential pair (i.'.e.-, the.difference between the first and second output voltages of the MOS differential pair) having a linear characteristic with respect to the input voltage is applied across the gates of the f ifth and sixth MOSFETs in the triple-tail cell (i.e., across the input terminal pair of the triple-tail cell). At the same time, the second constant voltage is applied to the gate of the seven;th MOSFET of the MOS triple-tail cell (i. e.

to the control terminal of the MOS triple-tail cell).

Accordingly, the current f lowing through the drain of the seventh MOSFET increaes proportional to the square of the input voltage and at the sarie time,' the cur'rents f lowing through the coupled drains of the fifth and sixth MOSFETs decreases proportional to the square of the input voltage.

Thus, the MOS linear transconductance amplifier according to the third aspect of the present invention is equivalent to the known adaptively-biased MOS differential pair.

J This means that the differential output current, which. is derived from the drains of th f if th and sixth MOSFETs, is proportional to the input voltage., In other words, the differential output -1.3- . 1 current of the amplifier according to the third aspect is proportional to the input voltag?, i.e., the differential output current of this amplif ier has a linear characteristic with respect to the input voltage.

The superior linearity of the differential output voltage of the MOS linear transconductance amplifier according to the third aspect'is seen within the whole range of the operating input voltage, i.e., the whole operating input voltage range. This is because the operating input voltage range of the MOS differential.

pair is in accordance with that of the MOS triple-tail cell.

In a preferred embodiment of the amplifier according to the third aspect, a ratio (W/1) of a gate width W to a gate length L of each of the f irst and second MOSFETs is K, times as large as that of a unit MOSFET, where K, is a constant equal to or greater than unity; and a ratio (W/L) of a gate width W to a gate length L of each of the third and fourth MOSFETs is, K2 times as large as that of the unit MOSFET, where K2 is a constant equal to or greater than unity.

In this embodiment, there is an additional advantage that 20 an amplifier or attenuator can be readily realized by changing the values of the constants K, and/or K2, and that the amplification J or attenuation rate of the amplifier or attenuator can be optionally set.

1 ' I- j In another preferred embodiment of the amplifier according to the third aspect, a ratio (W/L) of a gate width W to a gate length L of the seventh MOSFET is twice as large as that of the fifth and sixth MOSFETs.

In still another preferred embodiment of the amplifier according to the third aspect, eighth and ninth MOSFETs serving respectively as loads of the; fifth and sixth MOSMETs are additionally provided. The eighth and ninth MOSFETs are connected to the drains of -the fifth and sixth MOSFETs, respectively. A third constant voltage is commonly applied to gates of the eighth and ninth MOSFETs, and the dif f erential output current proportional to the input voltage is converted to a differential output voltage by the eighth and ninth MOSFETs.

In this embodiment, there is an additional advantage that the differential output voltage proportional to the input voltage can be derived instead of the differential output current.

In a further preferred embodiment of the amplifier according to the third aspect, a current value of the second constant current source/sink is changeable, and the trans conductance value of the amplifier is tunable by changing the current value of the second constant current source/sink.

j In this embodiment, there is an additional advantage a tunable MOS linear transconductance amplifier can be realized. A MOS linear. transcohdilctancp" amplifier according to a fourth aspect of the present invention is comprised of (a) a MOS 5 differential pair f c rmed by first and secondMO5FETs whose sources are coupled together; an input voltage being applied across gates of the first and second MOSrETs; a first output voltage being generated at a drain of the first M05FET; a second output voltage being generated at a drain of the second MOSFET; (b) a first 10 constant current sourcelsink for driving the MOS differential pair... the first constant current source/sink being connected to the coupled sources of the first and second MOSPETs; (c) a third MOSPET connected to a drain of the f irbt MOSFET; the third MOSFET serving as a load of the first MOS FET; (d) a f ourth MOSFET connected to a drain of the second MOSFET; the f ourth MOSFET serving as a load of the second MOSPET; (e) a quadritail cell formed by f if th, sixth, seventh, and eighth MOSFETs whose sources are coupled together; the quadritail cell being driven by a second constant current sourcelsink; (ú) a first constant voltage being commonly applied to gates of the third and fourth MOSFETs; (g) the first output voltage of the MOS differential pair being applied to a gate of the fifth MOSFET, and the second output voltage of the MOS dif f erential pair being applied to a gate of the sixth MOSFET; (h) a second constant voltage being commonly applied to gates of the seventh and eighth MOSFETs4 and (i) a differential output current p roportional to the Input voltage being derived from the drains of the fifth and sixth MOSFETs.

The NOS linear transconductance amplifier according to the fourth aspect of the present invention has a configuration obtained by replacing the NOS tribi e-tail cell with a NOS quadritail cell in the MOS linear trans conductance amplifier according to the third aspect.

It is known that the MOS quadritail cell has a same operation as that of the MOS triple-tail cell used in the MOS linear transconductance amplifier according to the third aspect if the drains of the seventh and eighth MOSFETs of the quadritail cell are coupled together, or if the drains of the seventh and eighth MOSFETs of the quadritail cell are respectively connected to the drains of the f if th and sixth M05FETs. Theref ore, because of the same reason as that shown in the M05 linear transconductance amplifier according to the third aspect, the differential output current derived from the drains of the fifth and sixth MOSFETs is proportional to the input voltage, in other words, the differential output current has a linear characteristic with respect to the input voltage. 4' Also, because of the same reason as above, the superior linearity of the differential output current of the MOS linear trans conductance amplifier according to the fourth aspect is seen within the whole range of the operating input voltage, i.e., the whole operating input voltage range.

In a pref erred embodiment of the amplif ler according to the fourth aspect, a ratio (WIL) of a gate width W to a gate length L of each of the first and second M05FETs is K, times as large as that of a unit M05FET, where K, is a constant equal to or greater than unity; and wherein a ratio (W/L). of a gate width W to a gate length L of each of the third and fourth MOSFETs is K2 times as large as that of the unit MOSFET, where K2 is a constant equal 10 to or greater than unity.

In this embodiment, there is an additional advantage that an amplifier or attenuator can be readily reali2ed by changing the values of the constants K, andlor K2, and that the amplification or attenuation rate of the amplifier or attenuator can be 15 optionally set.

In another preferred embodiment of the amplifier 1 according to the fourth aspect, ratids (WIL) of a gate width W to a gate length L of the seventh and eighth MOSFETs are equal to that of the fifth and sixth MOSFETs. 20 In this embodiment, there is an additional advantage that the circuit configuration is simplified. In still another prefenred embodiment of the amplifier according to the fourth aspect, ninth and tenth MOSFETs serving respectively as loads of the fifth and sixth MOSFETs are 9 4! 1,- 1 additionally provided. The ninth and tenth MOSFETs are connected to drains of the fifth and sixth.MOSFETs, respectively. A third constant voltage is commonly applied to gates of the ninth and tenth MOSFETs, and the differential output current proportional to the input voltage is converted to a dif f erential output voltage by the ninth and tenth MOSFETs.

In a further preferred embodiment of the amplifier according to the fourth aspect, the drains of the seventh and eighth MOSFETs are coupled togeter, or the drains of the seventh and eighth M05FETs are respectively connected to the drains of the fifth and sixth MOSFETs.

In this embodiment, since the MOS quadritail cell is equivalent to the MOS triple"tail cell in these two cases, the MOS quadritail cell can be used instead of the MOS triple-tail cell. There is an additional advantage that that the chip area can be decreased because the f if th to eighth MOSFETs constituting the MOS quadritail cell can be realized by the use of a unit MOSFET with a minim= chip area.

In a still further preferred embodiment of the amplifier' according to the fourth aspect, a current value of the second constant current sourcelsink is changeable, and the trans conductance value of the-amplifier is tunable by changing the current value of the second constant current source/sink.

In this embodiment, there is an additional advantage that a tunable MOS linear transconductance amplifier can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred features of the present Invention will now.be described, by way of example only, with reference to the accompanying drawings, in which:-.

Fig. 1 is a circuit diagram showing a conventional MOS linear transconductance amplifier.

Fig. 2 is a circuit diagram showing a MOS linear transconduct ance amplifier according to a first embodiment of the present invention.

Fig. 3 is a diagram showing the calculated output voltage characteristics of the MOS linear trans conductance amplifier according to the first embodiment of Fig. 2 with respect to the input voltage.

Fig.' 4 is a diagram showing 'the measured output voltage_ and differential output voltage characteristics of the MOS linear trans conductance amplifier according to the first embodiment of Fig. 2 with respect to the input voltage, where K2 = K, = 1.

Fig. 5 is a circuit diagram showing a MOS linear trans conductance amplifier accQrding to a second embodiment of the present invention. Fig. 6 is a circuit diagram showing a MOS triple- tail cell used in a MOS linear transconductance amplifier according to a third embodiment of the present invention. 5 Fig. 7 is a circuit diagram showing the MOS linear trans conductance amplifier according to the third embodiment of the present invention, in which the MOS triple-tail cell of Fig. 6 is used. Fig. 8 is a circuit diagram showing a MOS linear trans conductance amplifier' aCc6rding to a fourth embodiment of the present invention. Fig. 9 is a diagram showing the drain current characteristics of the

MOSFETs constituting the MOS quadritail cell in the MOS linear transconductance amplifier according to the fourth embodiment of Fig. 8 with respect to the input voltage.

Fig. 10 is a circuit diagram showing a MOS linear transconductance amplifier according to a fifth embodiment of the present invention.

Fig. 11 is a circuit diagram showing a MOS linear trans conductance amp;l ier 1 ac;rdingt to c sixth embodiment of the present invention.

Fig. 12 is a diagram showing the output current characteristic of the MOS linear trans conductance amplifier according to the first embodiment of Fig. 2 with respect to the - IN 1 - input voltage.

Fig., 13 is, -A di 1 ag'rafn shq-wing the output current characteristic of the MOS linear transconductance amplifier according to the Sixth embodiment of Fig. 11 with respect to the. input voltage.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will be described in detail below while referring to the drawings 10 attached.

FIRST EMBODIMENT A MOS linear'transconductan'e"amplifier according to a first embodiment of the present invention has the circuit configuration shown In Fig. 2.

As shown in Fig. 2, this amplifier is equipped with a MOS dif f erential pair 1 f ormed by two n-channel MOSFETs M1 and M2 whose sources are coupled to-gether, and two n-channel MOSFETs M3 and M4 serving respectively as loads of the NO5FETs M1 and M2. Sources of the MOSFETs M1 and M2 forming the MOS differential pair 1 are connected to the ground through a constant current sink 2 sinking a constant current Iss. -The MOS differential pair 1 is driven by the constant current ISS. Gates of the MOSFETs M1 and M2 constitute an input terminal pair of the MOS linear trans conductance amplifier according to the first embodiment, J across which an input_voltage V, isipplied.

The MOSFETs M1 and M2 have the same ratio (W/L) of the gate width W to the gate length L, which is K, times as large as that of a unit MOSFET, where K, is a constant equal to or greater 5 than unity (i - e., K, a: 1).

The MOSFET M3, which serves as the load of the MOSFET M1, has a source connected to a drain of the MOSFET MI, a drain connected to a supply voltage line applied with a power supply voltage VDD, and a gate applied with a constant dc voltage, i.e., a bias voltage VjB. Similarly, the MOSFET M4, which serves as the load of the MOSFET M2, has a source connected to a drain of the MOSFET M2, a drain connected to the supply voltage line applied with the power supply voltage VDD, and a gate applied with the same constant dc voltage, i.e., the same bias voltage VB.

The MOSFETs M3 and M4 have the same ratio (WIL) of the gate width W to the gate length 1, which is K2 times as large as that of a unit MOSFET, where K2 is a constant equal to or greater than unity (i.e., K2 k 1) Next, the operation principle of the MOS linear transconductance arnplif ier, according. to.the first embodiment is explained below.

Supposing that the channel-length modulation and the body effect can be ignored, and that a drain current ID of a MOSFET operating in the saturation region has a square-law -23- 1; is 1 j, characteristic with respect to its gate-to-source voltage the drain current ID is given by the following well-known expressions or equations (1a) and (1b) K (VG.9 - V T,ff (VGS k VTH (1a) ID m 0 NS 5 VTH) (1b) In the equations (1a) aind (1b), K is a ratio of the gate-width to gate- length ratio (WIL) with respect to the ratio (W/L) of a unit MOSFET, and % and 0 are the threshold voltage and the transconductance parameter thereof, respectively. The transconductance parameter is defined as J6=iu- c where g is the effective mobility of a carrier and Cox is the gate-oxide capacitance per unit area.

The effective mobility g varies dependent on the absolute temperature T according to the following equation (2).

3 T P " 9300 (.300) (2) The transconductaricepgrametier A varies dependent on the t ' absolute temperature T according to the following equation (3), 1. 0 1 1 3 F300 (3) In the equations (2) and (3), the suffix "30C denotes the values of [a, 0, and T at 300 K (= 27 OC) Supposing that all the MOSFETs M1 to M4 are matched in characteristic, drain currents ID, and 1DZ of the MOSFETs M1 and M2, which are two output curren'ts of..,the MOS differential pair 1, are expressed in the following equations (4a) and (4b), 10 respectively.

(4a) 1D1 = + K, i6Vi 1 Vil;5 2 11z rK, 7V" FK, V21 1 Vi 1;9 (4b) 11)2 = K, #Vi i 2 {,W - FK10 As seen from the equations (4a) and (4b), the operating input voltage range of.the.,MOS.differen'tial.pair 1 is given as Vi The drain currents ID, and ID2 of the MOSFETs M2 and M2, which are expressed by the equations (4a) and (4b), are respectively square -root -compressed by the M05FETs M3 and M4 and -25- at the same time, they are converted to first and second output voltages Vol"and V02,' respectively. when a differential output voltage of the MOS differential pair 1 is defined as AV, the voltage AV is given by the following equation (5) using a constant A.

VOI - V02 A (IDI -,D2 (5) Here, the following identity (6) is utilized b ra+.72 x a 2 2 - Ca - J2 x Ca b J2 x 2 (6) where a and b are constants, and x is a variable.

Then, the constant a and b and the variable x in the identity (6) are set as follows';'.

1 X Vi k, j61 (-7) Then, the left-hand side of the identity (6) is equal to 20 one obtained by substituting the above equations (4a) and (4b) into the above equation (5). At this time, the right-hand side of the identity (6) is equal to V, JK_ -1 Therefore, the following equation (8) is established.

A V A A J-, IS 9 V, vi J1 SO ..A As seen from the equation (8), the differential output voltage AV of the MOS differential pair 1 (i.e., the'difference between the square root of the drain current ID, and the square root of the drain current ID2) is proportional to the input voltage Vi.

Additionally, when the differential output current of the MOS differential pair 1 is defined as AID, the current AID is expressed by using the drain currents ID5 and IDe as -'D - D] - 1D2 = (IDI -,02)(IDI + 'D2 172 -K, 0 Vi I t JK15 - (9) 1 vi 1:9 FI-;;- K, fl i' Accordingly, it is seen that the differential output j ' current AID of the MOS dif f erential pair 1 comprises a linear term given by the following expression (10) and a nonlinear term given by the following expression (11).

JID -,D2 KIP Vi fj- -I- DI +l- 02 _ KI V i RK, fli (10) 1 V, 1:9 'j (11) K, fl) Here, a common source voltage at the coupled sources of the MOSFETs MI and M2 of the NOS dif f erential pair 1 is defined as Vs,. Then, the common source voltage Vs, is given by the following'ecluation - 12) V31 = VCM) - Vny - (12) where Vcmi is the common-mode volCage of the input voltage V:L which is applied dif f erentially across the gates of the MOSFETs MI and m2.

As seen from the equation (12) the common source voltage vs, is a function of the input valtage,,Vi..' Therefore, the common source voltage Vs, varies dependent on the input voltage Vi. Also, the third term 1 (21 V2) K in the equation (12) is equal to (112)1" of the term 21 V2 KT in the expression (11).

As a result, it is seen thatthe nonilinear-term (11) of the differential output current All) of the MOS differential pair 1 is generated due to the change or fluctuation of the common source voltage Vsl. This means that if the common source voltage Vs, of the differential pair 1 Is fixed at a constant value, the 10 differential pair 1 can be opetated linearly.

On the other hand, the first and second output voltages V01 and % of the differential pair 1 including the MOSFETs M3 and M4 as their loads, which are respectively generated at the drains of the MOSFETs M1 and.M2., are. expressed in the following 15 equations (13a) and (13b), respectively.

'o 1 - VB Vrq - 1.0 ( 1 vi (13a) FK2 V02 - VB VIY I D V, (13b) J2 F Therefore, the differential output voltage AV of the MOS differential pair 1 is given by the following equation (14). j, ISS (14) AV' V01 - V02 F'2 The - f ollowinT f act - is' seen. from. thie equation (14) Specif lcally, if the ratio K2 of the gate-width to the gate-length ratios (WIL) of the MOSFETs M3 and M4 serving as the loads Is io greater than the ratio K, of the gate-width to the gate-length ratios (WIL) of the MOSFETs M1 and M2 of the differential pair 1 (i.e., K2 > KJ, the MOS differential pair 1 serves as an opposite-phase linear attenuator. If the ratio K2 of the MOSFETs M3 and M4 serving as the lo ads is equal to or less than the ratio K, of the MOSFETs M1 and M2 of the dif f erential pair 1 (i. e Kz K,), the MOS dif f erential pair 1 serves as an opposite-phase linear amplifier. Further, the sup4ilor linearity of the MOS differential pair 1 is seen within the whole operating input voltage range of 1 vi 1:! -- I.5 J1 fl As seen f rom the equation (14), the dif f erential output voltage V of the MOS differential pair 1 having the MOSFETs M3 j, and M4 as the loads is proportional to the input voltage vi. In other words, the MOS differential pali 1 having the MOSFETs M3 and M4 as the loads serves as a linear attenuator or linear amplifier with respect to the input voltage V,. Also, if the value of. (K2/K1) 'is set as a'small value, a high gain will be realized.

Additionally, when the common-mode voltage of the output voltages Voi and % is defined as Vcmz, the voltage VcK2 is expressed from the above equations (11), (12), (13a), and (13b) in the 10 following equation (15).

VCM2 m V01 + V02. 2 j " IDI- 1 JID F"2 2 2 2 V' K V2 - VB - VTH - - S I' --LF- r K10 2 K2 K vcl VT1r - V!',) 7j) - VS - VrH V, K,,6) K2 It is seen from the equation (15) that the common-mode voltage Vaa of the output voltages V01 and V02 of the differential i" pair 1 is given by using the common-source voltage % which is expressed by the above equation (12).

Fig - 3 shows the calculated output voltage characteristic w, 1.. i-3LiIF j 1 1 A (i.e., the input-output characteristic) of the MOS differential pair 1. In Fig. 3, the curves 31 and 32 denote the first and second output voltages Vol a ' nd Vo2, espectiv"'ely, the curve 33 denotes the common- mode voltage Vcw2 of the first and second output 5 voltages Voi and V02, the curve 34 denotes the voltage [-Vol + 2 Ws VT0 I, and the curve 35 denotes the voltage [V02 - Vol + Vs Vriil. As seen from the curve 35, the differential output voltage &V of the MOS differential pair 1 is proportional to the input voltage V,.

Fig. 4 shows the measured output voltage characteristic (i.e., the input-output characteristic) of the MOS differential pair 1, where K2 - K1 1 -. In this measurement, an n-channel MOSFET array (type: gPA572T) was used. The threshold voltage VTH of the MOSFETs in this MOSFET array was approximately 1.5 V, and the trans conductance parameter P thereof was greater by approximately two f igures than that of the popular MOSFETs. that have been fabricated by the Complementary MOS (CMOS) processes and used in popular. Therefore, the power supply voltage VDD and the tail current Iss needed to be as large as. possible in order to expand the input voltage range. As a result, the. power supply voltage VDD was set as 5. 0 V and the tail current Iss was set as 10. 5 mA.

In Fig. 4, the curves. 41 'and 4. denote the f irst and second output voltages Vol and V02 of the MOS differential pair 1, respectively, the curve 43 denotes the differential output voltage AV (= V01 - V02) thereof, and the curve 44 denotes the dif f erential output voltage -AV (= % - Vol) thereof. As seen from Fig. 4, the differential output voltage AV of the MOS dif f erential pair 1 Is proportional to the input voltage Vi within the wide input voltage range.

SECORD EMBODIMENT Fig. 5 shows a M05 linear trans conductance amplifier according to a secon,d...embadine'nt of the present invention.

As seen from Fig. 5, this amplifier is equipped with a first MOS differential pair 2A formed by two n-channel MOSFETs M1A and M2A whose sources axe coupled together, a second MOS differential pair 1B formed by two n-channel MOSFETs M1B and M2B whose sources are coupled together, and a third MOS differential pair 1C formed by two n-channel MOSFETs M1C and M2C whose sources are coupled together. Each of these three MOS differential pairs 1A, 1B, and 1C has the same configuration as that of the MOS differential pair 1 used in the first embodiment. These NOS differential pairs 1A, 1B,' and' IC a.vg.connected in cascade.

Sources of the MOSFETs M1A and M2A forming the first MOS_ differential pair 1A are connected to the ground through a constant current sink 2A sinking a constant current Iss. Thefirst MOS differential pair 1A is driven by the constant current Iss.

1 1 4' Gates of the MOSFETs M1A and M2A constitute an Input terminal pair of the MOS linear transconductance amplifier according to the second embodiment, across which an input voltage V, is applied.

The MOSFETs M1A and M2A have the same gate-width to gate-length 'ratio (W:/L), w'hic;his Kl'i'tirdes. as large as that of a unit MOSPET.

An n-channel MOSFET M3A, which serves as a load of the MOSFET M1A, has a source connected to a drain of the MOSFET MIA, a drain connected to a supply voltage line applied with a power supply voltage VDD, and a gate applied with a constant dc voltage, i.e., a bias voltage VD. An n-channel M05FET M4A, which serves as a load of the MOSFET M2A,'has a source connected to a drain of the MOSFET M2A, a drain connected to the supply voltage line applied with the power supply voltage VOD, and a gate applied with the same constant dc voltage, i.c.,'.he same bias voltage Va.

The MOSFETs M3A and M4A have the same gate-width to gate-length ratio (W/L), which is K2 times as large as that of a unit MOSFET.

Similarly, sources of the M05FEts MIB and M2B f orming the second MOS diffezential pair IB are connected. to the ground through a constant current sink 2B sinking a constant current 15s. The second MOS differential pair IB is driven by the constant current 155. Gates of the MOSFETs M1B and M2B are connected to the drains of the MOSFETs MIA and M2A of the first differential 4' pair IA, respectively. The gates of the M05FETs MIB and M2B are applied with two output voltages V01.x and Vo2x of the first differential pair 1A generated at the drains of the MOSFET5 M1A,and N2A, respectively- The MOSFETs M1B and M23 have the same gate-width to gate-length ratio (W/L), which is K, times as large as that of a unit MOSFET.

An n-channel MOSFET M3B, which serves as a load of the MOSFET MIB, has a source connected to a drain of the MOSFET M1B, a drain connected to the supply voltage line of VpD, and a gate applied with the same bias voltage Vg. An n-channel MOSFET M4B, which serves as a load of the MOSFET M2B, has a source connected to a drain of the MOSFET M2B, a drain connected to the supply voltage line of V1)0, and a gate applied with the same bias voltage is vs.

The MOSFETs M3B and M4B have the same gate-width to gate-length ratio (W/L), which is K2 times as large as that of a unit MOSFET.

Sources of the MOSFETs MIC and M2C forming the third MOS differential pair IC are connected to the ground through a constant current sink 2C sinking a constant current 15s. The third MOS differential pair IC Is driven by the constant current Iss. Gates of the. MOSFETs., MIC and,,M2.C are..connected to the drains of the MOSFETs M1C and M2C of the second differential pair 1B, J respectively. The gates of the MOSFETs M1C and M2r- are Applied with two output voltages VolB and V02B Of the second differential pair IB generated at the drains of the MOSPETs M1R and M2B, respectively.

i The MOSFETs M1C and M2C have the same gate-width to gate-length ratio (W/L), which is K, times as large as that of a unit MOSFET.

An n-channel MOSFET M3C, which serves as a load of the MOSFET MIC, has a source connected to a drain of the MOSFET M1C, a drain connected to the supply voltage line applied of VDD, and a gate applied with the same bias voltage VD. An n-channel MOSFET M4C, which serves as a load of the MOSFET M2C, has a source connected to a drain of the MOSFET M2C, a drain connected to the supply voltage line of Vvi), and a gate applied with the same bias voltage VB..

The MOSFiTs M3C and M4C have the same gate-width to gate-length ratio (W/L), which is K2 times as large as that of a unit MOSFET.

A differential output voltage AVc) of the MOS linear trans conductance amplifier according to the second embodiment is equal to the difference between two output voltages Volc and Vo2c generated respectively at the drains of the M05FETs MIC and M2C, i.e., AVO = V01C - V02C. This output voltage AVo is derived from the drains of the M05FETs MIC and M2C. The drains of the MOSFETs -36- M1C and M2C constitute an output terminal pair of the amplifier according to the second embodiment.

As explained above, the MOS linear trans conductance amplifier according to the second embodiment of Fig. 5 has three 5 amplifier stages (i.e., the first to third NOS differential pairs IA, IB, and 1C) cascade- connected. Each of the three amplifier stages or the first to third MO differential pairs 1A, 1B, and IC has a same configuration as that of the MOS linear transconductance amplifier according to the first aspect of Fig.

2.

Therefore, because of the same reason as shown in the MOS linear trans conductance ampliú-ier' according to the first embodiment, the differential output voltage &Vc) of the MOS linear transconductance amplifier according to the second embodiment has a linear characteristic with respect to the input voltage within the whole operating input volt.age range.

Moreover, because the amplifier according to the second embodiment comprises the three cascade-connected MOS differential pairs IA, IB, and 1C, there is an additional advantage that the amplification or attenuation rate can be increased compared with the amplifier according to the first aspect. There is an additional advantage that if the number of the cascaded MOS di f f erential pairs 1A, IB, and IC, or the cascaded amplifier stages is changed, the amplification or attenuation 0 1 rate can be optionally adjusted.

THIRD EMBODIMENT Fig - 6 shows a MOS triple-tail cell 3, which is used for a MOS linear transconductance amplifier according to a third embodiment of the present invention. As shown in Fig. 1, the MOS linear transconductance amplifier according to the third embodiment has a configuration obtained by combining the triple-tail cell 3 shown in Fig. 6 and the MOS differential pair i.e., the MOS linear trans conductance amplifier according to the first embodiment of Fig. 2.

As shown in Fig. 6, the MOS triple-tail cell 3 is comprised of three nchannel MOSFETs M5, M. and M7 whose sources are coupled together. The sources of the MOSFETs MS, M6, and M7 are commonly connected to the ground through a constant current sink 4 (current value.. Io). This triple-tail cell 3 is driven by the constant current 10 generated by the sink 4.

The MOSFETs M5 and M6 have the same gate-width to gate-length ratio (W/L), which is equal to that of a unit MOSFET. The MOSFET M7 has a gate-width to gate-length ratio (WIL) which is K3 times as large as that of a unit MOSFET, where K3 is a constant equal to or greater than unity (i.e., K3 k 1) A gate of the MOSFET MS is applied with the first output voltage Voi of the MOS differential pair 1 (i.e., the MOS linear transconductance amplifier according to the first embodiment of j Fig. 2) generated at the drain of the M05FET MI. At the same time as this, a gate of the MOSFET M6 is applied with the second output voltage V02 of the MOS differential par 1 generated at the drain of the MOSFET M2. Thus, the difference AV between the first and second output voltages Vol and V02 (i.e., AV - V01 - V02), or the differential output voltage of the MOS differential pair 1 is applied to the triple-tail cell 3 as its input voltage.

A drain of the MOSFET W7 are connected to the supply voltage line Of VDD. A gate of the MCSFET M7 is applied with a constant dc voltage, i-e., a control voltage Vc. The control voltage Vc is generated by a control voltage generator circuit formed by an n- channel M05FET MS and a constant current sink 5, as shown in Fig. 7. The MOSFET M8 ha; a source connected to the ground through the constant current sink 5, a drain connected to the supply voltage line of VD1D, and a gate applied with the bias voltage VB. 'The drains of the MOSTETs M5 and M6 constitute an output terminal pair of the triple-tait cell 3, from which two output currents 1 and Iare derived, respectively. 20 Next, the operation principle of the MOS triple-tail cell 3 is explained below. The dif f erential output current Al (= 1 - 1-) of the MOS tripletail cell 3 is disclosed in the Japanese Non-Examined Patent Publication No. 8-84037 published in March 1996, which corresponds to the US Patent No. 5, 521, 542 issued to the inventor, K. Kimura, on May 28, 1996. This Publication describes that the dif f erential output current AI of the MOS triple-tail cell 3 is expressed as the following equation (16) using drain currents 11)s and ID6 of the MOSFETs M5 and 146. '1 61 IDS Or, -2K3,6AVVc'+2,6AV (K+2)LD- (AV)2 2K3VC%2 8 2 K3 + 2 fK3 W+ 2 + 4)L01 - 4K c (K3 0 3 VC1 2 1 AV 1;5 Mim F4;7, 2 0 1 Y K3 +4 (16) In the expression (16). Vel is a control voltage defined as VC - YCH2 + VC' (16a) Here, the following facts (1) and (ii) are taken into consideration.

(i) The differential output voltage &V (= V01 - V02) Of the m0S differential pair 1 (i.e., the MOS linear transconductance amplifier according to the first embodiment of Fig. 2), which is applied across the gates of the MOSFETs M5 and M6, has a linear t 1 characteristic with respect to the input voltage V1 applied to the differential pair 1.

(ii) Each of the drain currents IDS and ID6 Of the MOSFETs MS and M6 of the triple-tail cell 3 has a square-law characteristic 5 with respect to its Input voltage AV (- V01 - V02).

As a result, it is seen that the differential output current Ar (= I - 1) of the triple-tall cell 3, which is given by the above equation (16), needs to have a linear characteristic with respect to its input voltage AV. In other words, the 10 differential output current AI needs to be proportional to the Input voltage AV. Thus, the following relationship AI-cAV needs to be established, where c is a constant.

j Accordingly, the coefficient of AV in the numerator of the equation (16) is equal to the constant c; i.e., the following equation (17) needs to be established.

K3 VC 1 + (K3., 2) -10 - K3 +2 (A V) 2 2 K3 VC p 2 - c (17) when the equation (17) is established, i.e.,the differential output current AI of the triple-tail cell 3 is proportional to the input voltage Av, the differential output current AI is given by the followin-g equation.

AI= ( 2c,p AV (18) At this time, the control voltage Vc' is derived from the equation (17) as shown in the following equation (19).

K3 C + K, (K3 + # K3 (K3 + 2) 2 (A V)2. 2K3 C2 2 K3 (K3 + 2) VC = (19) The control voltage Vc used in Figs. 6 and 7 is readily obtained by using the equations (19) and (16a).

For example, when the constant c satisfies the following relationship (20), 2)2 10 c =(K,+2 4 ' 8 (20) the control voltage Vc' needs to be set so as to satisfy the following relationship (21).

J + kK3 2 K3 (21) As described above, when the control voltage Vc' is set to satisfy the above relati onhip ',(19), in other words,' the control voltage VC is set to satisfy the above relationship (19) and the equation (16a), the differential output current AI of the triple-tail cell 3 has a linear characteristic with respect to its input voltage AV. In this case, the differential output current AI is given by the abore equation (18).

Fig. 7 shows the circuit configuration of the MOS linear transconductance amplifier according to the third embodiment, which comprises the MOS dif f erential pair 1 f ormed by the MOSFETS M1 and M2 and their load MOSFETs M3 and M4 (i.e., the MOS linear transconductance amplifier according to the first embodiment in Fig. 2), and the MOS triple-tail cell 3 shown in Fig. 6. The MOS triple-tail cell 3 is cascade -connected to the MOS differential pair 1. Therefore, the gate voltages of the MOSPETs M5, M6, and M7 of the triple-tail cell 3 are equal to Vol, %, and VC (- Vac + vcl), respectively.

If the gate voltage Vc VCM2 + VC') of the MOSFET M7 is set as constant, the configuration of the bias circuit or control voltage generator circuit- for generating the control voltage VC 9 ' can be simplified. This simplified bias circuit can be realized under the following condition.

Specifically, the common-mode voltage V= of the first and second output voltages V01 and Vc)2 is given by the above equation (15), and the control voltage Vc' satisfies the above equation (19). Therefore, the gate voltage Ve (= Vcw2 + Vc') of the MOSFET m7 is expressed by the following equation (22).

VY VC - VCM 2 + VC'= VS - VrY K1 F 2 K2 K, F7 = constant -K3c+ K3(K3+#10 0 KI K3 j r,- 2 k^3+ 2 (A V)2 - 2K3 C2 2 K2 K3 (K3 + 2) j (22) As described above, to produce an output current with a linear characteristic in the MOS linear transconductance amplifier according to the third embodiment of Fig. 7, the coefficients of all the terms containing the Input voltage AV in the equation (22) need to be zero. In other words, the equation (22) needs to be simplified to the following equation (23).

VC - VCM2 + VC' = V,9 - V7-H - constant (23) The necessary condition to satisfy the equation (23) is that the following relationships (24a) and (24b) are established.

j K3 =2 w c 2 K2 J6 8 1 ' (24a) (24b) As a result, when the values of the currents 10 and Iss, and other parameters are set to satisfy the relationships (24a) and (24b), the above equation (23) is established and at the same time, the gate voltage Vc (= Vcm2 + Vc') of the MOSFET M7 is kept constant. Thus, the configuration of the bias circuit for generating the control voltage Vc can be simplified, as shown in Fig. 7. in this case, the control voltage Vc satisfies the above equation (19) in the configuration of Fig. 7 and accordingly, the differential output current AI.of the triple-tail cell 3 has a linear characteristic with respect to the input voltage AV, as expressed in the above equation (18).

Also, as already explained above, the input voltageAV to the MOS triple-tail cell 3, which is equal to the dif f erential 1 output voltage AV of the MOS differential pair 1 with their load MoSFETs, M3 and M4 in Fig. 2, is proportional to the input voltage Vi to the MOS linear transco'ndudtance,- amplifier according to the third embodiment.

Thus, it is confirmed that the MOS linear transconductance amplifier according to the third embodiment of rig. 7 outputs the differential output current AI with a linear characteristic with respect to..the input voltage Vj..

Additionally, in this case, the triple-tail cell 3 is 1 c) operated as an adaptively-biased differential pair disclosed in the Japanese Won-Examined Patent Publication No. 6-152275 published in May 1994, which corresponds to the US Patent No. 5,381,113 issued to the inventor, Kmra, on January 10, 1995.

Next, the operating input voltage range of the MOS linear transconductance amplifier according to the third embodiment of Fig. 7 is explained below.

When the differential output current AI has a linear characteristic with respect to td input voltage Vi, in other wards, the triple-tail cell 3 is operated as an adaptively-biased differential pair, the drain currents los, Im6, and 107 of the MOSEETs MS, M6, and M7 are expressed by the following equations (25a), (25b), and (25c)-, respeCtively, where K, - 1 and K3 - 2.

V F- Io2 4 2 ID6 = -1- AV + 4( F-flA) ID7 10 V) 2 2 { 1,4 V 1;5 FI-A fl) AV rlo As clearly seen from the equations (25a) and (25b), each of the output currents I and I- of the triple-tail cell 3 is proportional to the input voltage AV and therefore, it is seen that each of the output currents I" and I- has an ideal square-law characteristic with respect tothe input voltage AV within the operating input voltage range of AV shown in the equations (25a) and (25b) The linear input voltage range of the triple-tail cell 3 of Fig. 6 can be equal to the operating input voltage range of the MOS differential pair 1 of Fig. 2 under some condition. This condition is obtained in the following way.

First, unless all the M05FETs M5, M6,and M7 of the triple-tail cell 3 are pinched off, the output voltages V01 and of the MOS differential pair 1 and the control voltage Vc are expressed as the following equations (26a), (26b), (26c), -4.7- f ' respectively.

=V DI 0 1 V02 = V& - Vrif 1JD2 J2 VC= VB - vrg 2J6 1 1 ' (2 6a) (2 6b) (26c) The equations (26a) and (26b) are the sarne as the above equations (13a) and (13b), respectively.

When ID1 = Iss and ID2 = 0, the equations (2 6a), (2 6b), (2 6c) are changed to the following fquations (27a), (27b), (27c), respectively.

VO I = VB 7,7jf FK2 V02 - VB - V711 (27a) 1 ' V,: - V, - V,,, - F"-V (27b) (27c) Here, the comnon-source.-voltage of the MOSFETs MS, M6, and M7 is defined as Vs2. Then, the following equation (28) is -48- established in the equation (2.5a) for the drain current IDS.

IDS A(,dv P(V01 - V52 - VTH (28) 4 By substituting the equation (27a) into the equation (28) j the following equation (29) is obtained- AV= 2(V,-2V, I ,, - V12 0 1..

(29) Similarly, the following equation (30) is established in the equation (25b) for the drain current ID6. ' - A(AV + L ID6= 0)2 L 4 r; _ V P (V02 V52 7_1y)2 (30) By substituting the equation (27b) into the equation (30) the following equation (31) is obtained.

1 " FL; + AV= 2(VB - 2VrH - VS2) 1 J (31) Subtraction of the equation (29) from the equation (31) results in the equation (32).

K2 0 ' (32) The equation (32) shows the maximum value of the dif f erential input voltage,&V applied to the MOS triple-tail cell 3 of Fig.

On the other hand, the minimum value of the di f f erential input voltage AV is obtained when ID2 = Iss and IDI - 0, which is expressed as follows.

A J7 = ' 55 - FK2 fl 1 ".

(33) Accordingly, from the equations (32) and (33), the range of the differential input voltage j&V is given by the following expression (34).

1 AV 1:5 JI2-15J6 1 ' -so- (34) Moreover. from the relationship between the drain current J In.7 and the common source voltage V52 and the equations (25c) and (27c), the following equation (35) is obtained for the drain current ID7, where K, 1 and K3 m 2.

1D7 2 2fl(VC_ V32 - VZW)" 2V FTS7_) 2 P ( 6 - 2Vw -V52 - 2.K2p) (35) By substituting the above equations (31) and (32) into the equation (35) and solved, the following equation (36) is obtained.

= 2 ISS 1. X2 i. ' (36) As a consequence, when the values of the constant currents lo and Iss of the constant current sinks 2 and 4 and the ratio K2 of the gate-width to the gate-length ratio (W/L) of the MOSFETs m3 and M4 with respect to the unit MOSFET are set to satisfy the above equation (36), the input voltage range of the MOS 20 triple-tail cell 3 is equal to the operating input voltage range j 1 i of the MOS differential pair 1. Accordingly, the MOS linear transconductance amplifier according to the third embodiment of Fig. 7 has an ideal linear characteristic within its whole the operating input voltage range. 5 In this case, the MOS riple-tail cell 3 of Fig. 6 is operated as the adaptively-biased differential pair having the maximum linear input voltage range. The simplest circuit configuration of the triple-tail cell 3 of Fig. 6 is given under the condition that K, = Kp = 1, K3 - 2, and Iss m ID/2, as shown in Fig. 7. In this case, the constant c is given by the following expression (37).

c=2 FL; V (37) is The constant c given by the expression (31) satisfies the above equation (19). The control voltages vc and vcl are given by the following equations (38a) and (38b), respectively.

1 --- VC - VCM2 + MC'=;B - V711 - 1 FL; 2 + (AV)2) VC 2 j ' (38a) (38b) FOURTH EMBODIMENT Fig. 8 shows a mos linear t"r'ansconductance amplifier according to a fourth embodiment of the present invention, which corresponds to one obtained by replacing the triple-tail cell 3 in the amplifier according to the third embodiment of Fig. 7 with a quadritail. cell 31. Therefore, explanation about the same configuration is omitted here ty attaching the same reference symbols as those in Fig. 7 to the same elements in Fig. 8 for the sake of simplification.

Since the MOSFET M7 of the triple-tail cell 3 of Fig. 6 has the ratio (WIL) which is,twic.e as large as that of a unit MOSFET (i.e., K3 - 2), the MOSFET M7 can be divided into two unit MOSFETs M7A and M7E whose sources, drains, and gates are coupled together.

Therefore, the triple-tail cell 3 of Fig. 6 can be changed to the quadritail cell'31 as shown in Fig. 8.

The quadritail cell 31 formed by the four M05FETs MS, M6, M7A, and M7B is equivalent in operation to the triple-tail cell 3 of Fig. 6, so the operation of the MOS linear trans conductance amplifier according to the fourth embodiment is the same as that of the MOS linear transconductance amplifier according to the third embodiment of Fi. 7. 9 Fig. 9 shows the characteristics of the drain currents ID5o ID6.. I07A# and ID7& of the MOSFETs M5, M6, M7A, and M7B forming 5.

1 1-5 j the MOS quadritail cell 31 in the MOS linear trans conductance amplifier according to the fourth embodiment of Fig. 8.

It is seen from Fig. 9 that each of the drain currents ID5, ID6, ID.7A, and ID78 has a square-law characteristic, as shown by the curves 51, 52., an"d 53... Also,. 1t is seen that the sum of the dra in current s ID.7,h and ID.?B, i. e., GED7A + ID7b), has a square- law characteristic f rom the curve 54, that the sum of the drain currents los and ID7A,:I.e., (ID5 + ID7,X), has a linear characteristic f rom the curve 5 5, and that the sum of the drain currents 11)6 and ID7B, i.e (ID6 + IMB), has a linear characteristic from the curve 56.

FIFTH EMBODIMENT Fig. 10 shows a MOS-linear transconductance amplifier according to a fifth embodiment of the present invention, which 15. corresponds to one obtained by adding'.two n-channel MOSFETs M8 and M9 as the load of the MOSFETs M5 and M6 to the MOS linear trans conductance amplifier according to the fourth embodiment of Fig. 8. In this embodiment, the differential output current AI in the amplifier according to the fourth embodiment of Fig. 8 is converted to a differential output voltage AVO.

The differential output voltage Avo is given as AVO = V03 - V04, where V03 and % are the drain voltages of the MOSrETs M5 and M6, respectively.

In the circuit configuration of Fig. 10, the combination of two n-channel MOSFETs M10A and M10B and a constant current sink 5A (current value: Ic) constitutes the control voltage generator 5 circuit for generating the control voltage Vc for the MOSFET M7. The MOSFETs M10A and M10B have sources commonly connected to the ground through the constant current sink SA, drains commonly connected to the supply voltage linel 0, f VDD, and gates commonly applied with the same bias voltage VB as that of the MOSFET9 M3, M4, MS, and M9.

SIXTH EMBODIMENT Fig- 11 shows a MOS linear transconductance amplifier according to A sixth ernbodiment.,of the present invention, which corresponds to one obtained by connecting respectively the drains of the MOSFETS M7A and M7B of the quadritail cell 3' to the drains of the MOSFETs MS and MG in the MOS linear t rans conductance amplifier according to the fourth embodiment of Fig. 8, and by adding two resistors 6 and 7 having the same resistance RL as the loads of the MOSFETs M5 and M6 thereto. This quadritail cell is referred as Y' below.

In the sixth'embodiment, the differential output current AI in the amplifier according to the fourth embodiment of Fig.

j, 8 is converted to a differential output voltage AVo.

AS seen from the curves 55 and 56 in Fig. 9, the sum (ID5 1 i 1 + 101A) of the drain currents IDs and ID-;>, as a linear characteristic, and the sum (1D6 + ID7B) of the drain currents ID6 and ID-IB also has a linear characteristic. Therefore, the differential output current AI is given as -1 (IDS - 1D7 A (AID6 - A7D7 B J_ which means that the differential output current 41 has a linear characteristic within the wide input voltage range in the sixth embodiment.

As a consequence, the differential output voltage AVO in the sixth embodiment, which is obtained by conversion of the differential output current AI using the resistors 6 and 7, has a linear characteristic within the wide input voltage range.

The drain currents IDS, IDS, Ii).7A, and ID71B Of the MOSFETs MS, M6, M7A, and M7B constituting the quadritall cell Y' are expressed by the following equations (39a), (39b), and (39c), respectivelY.

4 iv;s.

1.06 (AV + AV5 (3 9b) 4 FL;_) 4 is j ' 1D7 A '-- 1D7 8 " 1 {I"-0(,6v)2}( 1 AV 1;S L0_) 4 FP 1.1.

(39c) Thus, the effective tail current for the MOSFETs M5 and M6 forming the differential pair of the quadritail cell 311 is given by the following equation (40).

IDS -1- J16 - 1 {I, +# (AV) 2 dvl S 7 0 (40) 18) The simplest circuit configuration of the quadritail cell 31' of Fig- 11 is given under the condition that K, - K2 - 1, K3 2, and Iss IQ12. In this case, th 'constant c is given by the following expression (41).

c=2 iL; 1V (41) The constant c given by the expression (41) satisfies the above equation (19). The control voltages Vc and Y are given by the following equations (42a) and (43b), respectively.

; 0 11.

1 L_ VC = VCM 2 +VC'= V'- V79 2 F; VC 0 2 (- F-, A6 + Ffl- ('A V (42a) (4 2b) The differential output current,&1'of the quadritail cell 311 of Fig. 11 is given by the following equation (43).

A I - 'M - 1D6 - - -pi-o vi 4; ' ( 1 vi 1:-5 ri-0 - 0) The operating input voltage range is as follows.

(43) 1 vi j.:c- FL; (44) The operating input voltage range shown by the equation (44) is equal to the operating input voltage range of the MOS differential pair 1 having the load MOSFETs'M3 and M4 shown In Fig. 2.

The transconductance is obtained by differentiating the equation (43) by the input voltage Vi as follows.

1 1 1 1 1; 0 1 1 d (A I) F 0 d Vi 10 V, (45) Figs. 12 and 13 show the calculated transfer 5 characteristics of the MOS differential pair 1 of Fig. 2 and the MOS linear trans conductance amplifier according to the sixth embodiment of Fig. 11,.respeptively.' in Fig. 12, the curves 71 and 72 denote the change of the drain currents ID, and ID2 in the MOS linear transconductance amplifier according to the first embodiment of Fig. 2, respectively. It is seen from Fig. 12 that each of the drain currents Itn and ID2 has a square-law characteristic in the first embodiment.

In Fig. 13, the curves 81 and 82 denote the change of the two output currents (ID6 + ID7B) and (IDS 4- 1DIA) in the MOS linear trans conductance amplifier according to the sixth embodiment of Fig. 11, respectively.. 'It is. s4 en frIP-T Fig. 12 that each of the output currents (ID6 + ID7JB) and (ID5 + lg),7A) has a linear characteristic in the sixth embodiment.

If Ki = 1, K2 - 4, K3 m 2, and Iss = 210, the circuit configuration in Fig. 11 is in accordance with the conventional MOS linear t rans conductance amplifier shown in Fig. 1 proposed 1V by Toyota, et al.. In this case, the calculated transfer characteristic is equal to that shown in Fig. 13.

The quadritail cell 311 shoin'in Fig. 11 is equivalent in operation to the adaptively-biased differential pair. Therefore, the transconductance of the quadritail cell 311 is proportional to the square root of the bias current and at the same time, the linear input voltage range thereof is proportional to the square root of the bias"current.

While the preferred forms of the present invention have been described, it is to be understood that modifications will be apparent to those skilled in the art without departing from the scope of the invention.'. The scope of the invention, therefore, is to be determined solely by the following claims.

Each feature disclosed in this specification (which term includes the claims) and/or shown in the drawings may be incorporated in the invention independently of other disclosed and/or illustrated features.

Statements in this specification of the,objects of the invention" relate to preferred embodiments of the invention, but not necessarily to all embodiments of the invention falling within the claims.

The description of the invention with reference to the drawings is by way of example only.

The text of the abstract filed herewith is repeated here as part of the specification.

A MOS linear transconductance amplifier is provided, which has superior transconductance linearity within the whole input voltage range and that is readily formed on L5Is. This amplifier is comprised of (a) a MOS differential pair formed by first and second MOSFETs whose sources are coupled together; an input voltage being applied across gates of the first and second MOSFETs; (b) a constant current source/sink for driving the MOS differential pair; the constant current source/sink being connected to the coupled sources of the first and second MOSFETS; (c) a third MOSFET connected to a drain of the f irst MOSFET; the third MOSFET serving as a load of the f irst MOSFET; (d) a f ourth MOSFET connected to a drain of the second MOSFET; the f ourth MOSFET serving as a load of the second MOSFET; (e) gates of the third and fourth MOSFETs being commonly applied with a constant voltage; and (f) a differential output voltage proportional to the input voltage being derived from the drains of the first and second MOSFETs. Some of -the amplifiers may be cascadeconnected, thereby forming a multi-stage amplifier, in which the amplification or attenuation rate can be optionally adjusted by changing the number of the cascading stages. A triple-tail or quadritail cell may be further cascade -connected to the MOS differential pair.

i 1

Claims

1 CLAIMS-:

1. A MOS linear transconductance amplifier comprising: (a) a MOS differential pair'forme.d. by first and second MOSFETs whose sources are coupled together; an input voltage being applied across gates of said first and second MOSFETs: (b) a constant current sourcelsink for driving said MOS differential pair; said constant current sourcelsink being connected to said coupled sources of said first and second MOSFETs; (c) a third MOSFET connected to a drain of said first MOSFET; said third MOSFET serving as a load of said first MOSFET; (d) a fourth MOSFET Corihebted.'o."a drain of said second MOSFET; said f ourth MOSFET serving as a load of said second MOSFET; (e) gates of said third and fourth MOSFETs, being commonly applied with a constant voltag.; and 0 (f a differential output voltage proportional to said input voltage being derived from said drains of said first and second MOSFETs.

2. The amplifier as claimed in clain 1, wherein a ratio (W/L) of a gate width W to a gate length L of each of said first and second MOSFETs is K, times as large as that of a unit MOSM, where K, is a constant equal to or greater than unity; and wherein a ratio (W/L) of a gate width W to a gate length L of each of said third and fourth MOSPETs is X2 times as large as that of stid unit'tOSFET, where Kl' is' a.constant equal to or greater than unity.

3. A MOS linear transconductance anplifier comprising:

(a) first to n-th MOS differential pairs, each of which is formed by two MOSFETs whose souzces are coupled together, where n is an integer equal to or greater than two; (b) first to n-th constant current sources/sinks for driving 15 said first to n-th MOS differential pairs, respectively; (c) first to n-th pairs of load M05FETs serving as loads of said first to n-th MOS differential'pairs, respectively; (d) an input voltage being applied across gates of said two MOSFETs forming said first MOS differential pair; (e) f irst.to (n-1) -th dif ferential voltages being applied to said second to n-th MOS differential paixs, respectively; each of said first to -(n-1)-th differential voltages being applied across gates of said' two MOSFETs forming a corresponding one of said second to n-th MOS differential pairs; 1 ' (f) a constant voltage being commonly applied to said gates of said two MOSFETs forming each of said first to n-th pairs of load MOSFETs; and (g) a differential output voltage proportional to said input voltage being derived f rom draing of said two MOSFETs f orming said n-th MOS differential pair.

4. The amplifier as claimed in claim 3, wherein said constant voltages respectively gpplied. to said gates of said MOSFETs forming said first to n-th pairs of load MOSFETs are equal to one another.

5. The amplifier as claimed in claim 3, wherein a ratio, (W/L) of a gate width W to a gate length L of each of said MOSFETs forming said first to n-th MOS differential pairs is K, times as large as that of a unit MOSFET, where K, is a constant equal to or greater than unity; and wherein a ratio (W/L) of a gate width W to a gate length L of each of said first to n-th pairs of load MOSFETs is K2 times as large as that of said unit MOSFET, where K2 is a constant equal to or greater than unity.

6. A MOS linear transconductance amplifier comprising:

(a) a MOS differential pair formed by first and second MOSPETs whose sources are coupled together; an input voltage being applied across gates of said first and second MOSFETs; a first output voltage being generated at a drain of said first MOSFET; a second output voltage being generated at a drain of said second MOSFET; (b) a first constant current sourcelsink for driving said MOS differential pair; said first constant current source/sink being connected to said cou pled sourcet of sai d first and second MOSFETs; (c) a third MOSFET connected to a drain of said first MOSFET; said third MOSFET serving as a load of said first MOSFET; (d) a fourth MOSFET connected to a drain of said second MOSFET; said fourth MOSFET serving as a load of said second MOSFET; (e) a triple-tail cell formed by fifth, sixth, and seventh MOSFETs whose sources are coupled together; said triple-tail cell being driven by a second constant current source/sink;, (f) a first constant voltage being commonly applied to gates of said third and fourth MOSFETs; -66 (g) said first output voltage of said MOS differential pair being applied to a gate of said f if th MOSFET, and said second output voltage of said MOS differential pair being applied to a gate of said sixth MOSFET, and (h) a second constant v'oltae being applied to a gate of said seventh MOSFET; and (i) a differential output current proportional to said input voltage being derived from said drains of said fifth and sixth MOSFETs.

j '

7. The amplifier as claimed in claim 6, wherein a ratio (WIL) of a gate width W to a gate length L of each of said first and second MOSFETs is K, times as large as that of a unit MOSFET, where K, is a constant equal to or greater than unity; and wherein aratio (WL), of a ate width W to a gate length L of each of said third and fourth MOSFETs is K2 times as large as that of said unit MOSFET, where K2 is a constant equal to or greater than unity.

8. The amplifier as claimed in,.claim 6, wherein a ratio (W/L) of a gate width W to a gate length L of said seventh MOSFET is twice as large as that of said fifth and sixth MOSFETs.

1

9. The amplifier as claimed in claim 6, further comprising eighth and ninth MOSFETs serving as loads of said f if th and sixth MOSFETs, respectively; said eighth and ninth MOSFETs being connected to drains s of said fifth and sixth MOSFETs, respectively; wherein a third constant voltage is commonly applied to gates of said eighth and ninth MOSFETs, and said differential output current proportional to said input voltage is converted to a dif f erential output voltage by said eighth and ninth MOSFETs.

10. The amplifier as claimed in claim 6, wherein a current value of said second constant current source/sink is changeable, and the trans conductance value of;,said amplifier is tunable by changing said current value of said second constant current sourcelsink.

11. A MOS linear transconductance amplifier comprising: (a) a MOS dif f erential pair f ormed by f irst and second MOSFETs whose sources are coupled together;20 an input voltage being applied across gates of said first and second.MOSFETs; a first output voltage being generated at a drain of said first MOSFET; a second output voltage being generated at a drain of said second MOSFET; (b) a first constant current source/sink for driving said MOS differential pair; said first constant current sourcelsink being connected to said coupled sources of saidfirst and second MOSFETs; (c) a third MOSFET connected to a drain of said f ixst MOSFET; said third MOSFET serving as a load of said first MOSFET; (d) a fourth MOSFET connected to a drain of said second MOSFET; said fourth MOSFET serving as a load of said second MOSFET; (e) a quadritall cell formed by fifth, sixth, seventh, and eighth MOSrETs whose sources are coupled together; said quadritail cell being driven by a second constant current source/sink; (f) - a first constant voltage being commonly applied to gates of said third and fourth MOSFETs; (g) said first output voltage of said MOS differential pair being applied to a gate of said f if th MOSET, and said second output voltage of said MOS differential pair being applied to a gate of said sixth MOSFET; (h) a second constant voltage being commonly applied to gates of said seventh and eighth MOSFETs; and 4, (i) a differential output current proportional to said input voltage being derived from said drains of said fifth and sixth MOSFETs.

12. The amplifier as claimed in claim 11, wherein a ratio (WIL) of"a gate width W to a gate length L 6f each of said first and second MOSFETs is KI times as large as that of a unit MOSFET, where K, is a constant equal to or greater than unity; and wherein a ratio (WIL) of a gate width W to a gate length L of each of said third and fourth MOSFETs is K2 times as large as that of said unit MOSFET, where K2 is a constant equal to or greater than unity.

13. The amplifier as claimed in claim 11, wherein a ratio (WIL) of a gate width W to a gate length L of said seventh and eighth MOSFETs is equal to that of said fifth and sixth MOSFETs.

- i

14. The amplifier as claimed in claim 11, further comprising ninth and tenth MOSFETs serving as loads of said fifth and sixth M05FETs, respectively; said ninth and tenth MOSPETs being connected to drains of said fifth and sixth MOSPETs, respectively; wherein a third constant volt. ae is--- commonly applied to gates of said ninth and tenth MOSFETs, and said differential output current proportional to said input voltage is converted j, to a dif f erential output voltage by said ninth and tenth MOSFETs.

15. The amplifier as claimed in claim 11, wherein said drains 5 - of said seventh and eighth MOSFETs are coupled together.

16. The amplifier as claimed in claim 11, wherein said drains of said seventh and eighth MOSFETs 'are connected to said drains of said fifth and sixth MOSFETs, respectively.

17. The amplifier as claimed in plaim 11, wherein a current value of said second constant current sourcelsink is changeable, and the transconductance value of said amplifier' is tunable by changing said current value of said second constant -current 15 sourcelsink.

. W. -71- 1 1

18. A - method of operating a MOS linear transconductance amplifier comprising a MOS differential pair formed by first and second MOSFETS whose sources are coupled together, a constant current source/sink for driving said MOS differential pair and connected to the coupled source of the first and second MOSFETs, a third MOSFET connected to a drain of the first MOSFET, and a fourth MOSFET connected to a drain of the second MOSFET, said method comprising the steps of:

applying an input voltage across gates of the first and second MOSFETs; applying a constant voltage commonly to gates of the third and fourth MOSFETs; and deriving a differential output voltage proportional to the input voltage from the drains of the first and second MOSFETs.

19. A method of operating a MOS linear transconductance amplifier comprising first to n-th MOS differential pair each of which is formed by two MOSFETs whose sources are coupled together, where n is an integer greater than 1, first to n-th constant current sources/sinks for driving said MOS differential pairs, and first to n-th pairs of load MOSFETs serving as respective loads for the first to n-th MOS differential pairs, said method comprising the steps of: applying an input voltage across gates of the two MOSFETs forming the first MOS differential pair; applying first to (n-1)-th differential voltages respectively to the second to n-th MOS differential pairs, each of said differential voltages being applied across gates of the -72- two MOSFETs forming the respective MOS differential pair; applying a constant voltage commonly to gates of the two MOSFETs forming each of the first to n-th pairs of load MOSFETs; and deriving a differential output voltage proportional to the input voltage from drains of the two MOSFETs forming the n-th MOS differential pair.

20. A method of operating a MOS linear transconductance amplifier comprising a MOS differential pair formed by first and second MOSFETs whose sources are coupled together, a first constant current source/sink for driving said MOS differential pair and connected to the coupled sources of the first and second MOSFETs, a third MOSFET connected to a drain of the first MOSFET, a fourth MOSFET connected to a drain of the second MOSFET, a triple-tail cell formed by f if th, sixth and seventh MOSPETs whose sources are coupled together, and a second constant current source/sink for driving the triple-tail cell, said method comprising the steps of: applying an input voltage across gates of the first and second MOSFETs to-generate a first output voltage at a drain of the first MOSFET and a second output voltage at a drain of the second MOSFET; applying a first constant voltage commonly to gates of the third and fourth MOSFETs; applying the first output voltage to a gate of the fifth MOSFET and the second output voltage to a gate of the sixth MOSFET; applying a second constant voltage to a gate of the seventh -73- MOSFET; and deriving a differential output current proportional to the input voltage from the drains of the fifth and sixth MOSFETs.

21. A method of operating a MOS linear transconductance amplifier comprising a MOS differential pair formed by first and second MOSFETs whose sources are coupled together, a first constant current source/sink for driving said MOS differential pair and connected to the coupled source of the first and second MOSFETs, a third MOSFET connected to a drain of the first MOSFET, a f ourth MOSFET connected to a drain of the second MOSFET, a quadritail cell formed by fifth, sixth, seventh and eighth MOSFETs, whose sources are coupled together, and a second constant current source/sink for driving the quadritail cell, said method comprising the steps of: applying an input voltage across gates of the first and second MOSFETs to generate a first output voltage at a drain of the first MOSFET and a second output voltage at a drain of the second MOSFET; applying a first constant voltage commonly to gates of the third and fourth M05FETs; applying the first output voltage to a gate of the fifth MOSFET and the second output voltage to a gate of the sixth MOSFET; applying a second constant voltage commonly to gates of the seventh and eighth MOSFETs; and deriving a differential output current proportional to the input voltage from the drains of the fifth and sixth MOSFETs. -74-

22. A MOS linear transconductance amplifier or a method of operating a MOS linear transconductance amplifier substantially or herein described with reference to any of Figures 2, 5, 6, 8, 10 and 11 of the accompanying drawings.