GB2462897A

GB2462897A - Debugging a hardware device comprising combinatorial logic

Info

Publication number: GB2462897A
Application number: GB0909104A
Authority: GB
Inventors: Joerg Walter; Lothar Felten; Volker Urban; Christopher Smith
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 2008-09-02
Filing date: 2009-05-28
Publication date: 2010-03-03
Also published as: GB0909104D0

Abstract

A method of debugging a hardware data processing device 10 having at least one state holding element and at least one logic unit with at least one combinatorial logic element, comprises extracting S10 a state of the device preferably by connecting the state holding elements of the device together to form at least one scan chain, the values of which are read out in a chip dump data file. The extracted state is transformed S20 into facilities and/or signal names used by a simulation model. Bits of the chip dump data file may be clustered in values corresponding with elements of the simulation model. The mapped facilities and/or signal names are loaded S30 into a simulator including the simulation model preferably by mapping them into a model initialisation file. The simulation model is run, preferably to evaluate S50 at least one logic unit without updating the state holding elements to generate an all event trace 30 which is just one cycle long and shows a transient value reconstruction. Alternatively, running the simulator model may comprise applying a clock signal and inputting external stimuli to generate an all event trace corresponding with the number of simulation cycles.

Description

DESCRIPTION

METHOD. COMPUTER PROGRAM PRODUCT AND DATA PROCESSING

PROGRAM FOR PROCESSING AN ERROR IN A DATA PROCESSING DEVICE

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates in general to verification and analyzing tools for hardware designs and in particular to a method of processing an error in a data processing device, wherein the data processing device comprises at least one state holding element and at least one logic unit with at least one combinatorial logic element. Still more particularly, the present invention relates to a data processing program and a computer program product for processing an error in a data processing device.

Description of the Related Art

Despite all verification efforts, very often bugs and/or errors are found in real hardware devices during bring up process, or even worse, in the field. Debugging these bugs and/or errors can be very tedious and time consuming because of the reduced debugging capabilities available in the hardware device. White the state of state holding elements like storage elements, latches, registers, etc. can be retrieved by scan chains, it is not possible to determine the value of signals between latch boundaries, i.e. in combinatorial logic units. In order to determine the value of combinatorial signals, state of the art methodology is to manually re-implement the hardware cone-of-influence in a scripting language like Rexx or PERL Given the size and depth of such cones, this process is difficult, time consuming and error prone. Some problems even require calculation of multiple signal cones. However, bugs and/or errors found in real hardware usually are corner cases which cannot be easily reproduced in simulation, so a verification setup would not necessarily produce results quicker.

In the IEEE-Paper "EDA in IBM: Past, Present, and Future" by John Darringer et al, IEEE Transaction on Computer aided Design of Integrated Circuits and Systems, Vol. 19, No. 12, December 2000, methods to dump the contents of scan cells to a tester for later detailed analysis are described.

Additional the US-Patent 6,832,342 B2 describes a method and apparatus for processing an error in a multiprocessor data processing system. An error is detected within the data processing system and a chip causing the error is identified within a plurality of chips to form an identified chip-Data is collected from the identified chip and hardware associated with the identified chip.

Summary of the Invention

The technical problem underlying the invention is to provide a method of processing an error in a data processing device and to provide a data processing program and a computer program product to perform the method of processing an error in a data processing device, which are able to provide a fast and automated way for signal reconstruction to process an error in a data processing device.

The invention solves this problem by providing a method of processing an error in a data processing device having the features of claim 1, a data processing program for performing a method of processing an error in a data processing device having the features of claim 17, and a computer program product causing a computer to perform a method of processing an error in a data processing device having the features of claim 18. Advantageous embodiments of the invention are mentioned in the sub claims.

Accordingly, in an embodiment of the present invention a method of processing an error in a data processing device comprising at least one state holding element and at least one logic unit with at least one combinatorial logic element comprises extracting a state of the data processing device, transforming the extracted state of the data processing device into facilities and/or signal names used by a simulation model (22), loading the transformed state of the data processing device into a simulator including the simulation model, and running the simulation model using the simulator generating output data which can be analyzed to debug the error in the data processing device.

In further embodiments of the present invention, extracting a state of the data processing device comprises connecting the state holding elements of the data processing device together to form at least one scan chain, wherein values of the at least one scan chain are read out in a chip dump data file.

In exemplary embodiments of the present invention, the extracted state of the data processing device comprises all readable state information of the at least one scan chain and/or arrays and/or registers.

In frirther embodiments of the present invention, transforming of the extracted state of the data processing device in facilities and/or signal names used by a simulation model comprises reading in and parsing the chip dump data file, descrambling and rearranging of bits of the chip dump data file to bring the bits in sequence and in correct order.

In frirther embodiments of the present invention, the method of processing an error in a data processing device comprises frirther clustering the bit values of the chip dump data file in values corresponding with elements of the simulation model.

In fUrther embodiments of the present invention, the method of processing an error in a data processing device comprises transforming names of the clustered bit values of the chip dump data file into names used by the simulation model.

In fUrther embodiments of the present invention, the method of processing an error in a data processing device comprises mapping facilities and/or signal names of the simulation model to the names derived from the chip dump data file.

In exemplary embodiments of the present invention, the method of processing an error in a data processing device comprises storing the mapped facilities and/or signal names into a model initialization file.

In fUrther embodiments of the present invention, the loading of the transformed state of the data processing device into a simulator including the simulation model comprises inputting of the model initialization file to initialize the simulation model wherein the simulator assigns the values of the model initialization file to facilities in the simulation model.

In fUrther embodiments of the present invention, running the simulation model using the simulator comprises evaluating the at least one logic unit without updating the state holding elements to generate an all event trace which is just one cycle tong.

In further embodiments of the present invention, the all event trace contains all values for all signals in the simulation model including combinatorial logic signal values of the at least one logic unit and shows a transient value reconstruction.

In alternative embodiments of the present invention, running the simulation model using the simulator comprises applying a clock signal and inputting extern stimuli to run at least one simulation cycle of the simulation model to generate an all event trace corresponding with the number of simulation cycles.

In further embodiments of the present invention, the all event trace contains all values for all signals in the simulation model including combinatorial logic signal values of the at least one logic unit corresponding with the at least one simulation cycle and represents a history leading to the error state.

In further embodiments of the present invention, the generated output data is displayed on a viewing device to be analyzed to debug the error in the data processing device.

In further embodiments of the present invention, the simulator is configured as VHDL-Simulator and the simulation model is based on VHDL.

In another embodiment of the present invention, a data processing program for execution in a data processing system comprising sofiware code portions for performing a method of processing an error in a data processing device when the program is run on the data processing system.

In just another embodiment of the present invention, a computer program product stored on a computer-usable medium comprises computer-readable program means for causing a computer to perform the method of processing an error in a data processing device when the program is run on the computer.

All in all, embodiments of the invention disclosed herein provide a manageable, automated way to efficiently trace back and analyze signal values between latch boundaries. Additional the effort required to set up the transformation is much smaller than the effort to manually derive values for a logic cone. it is also much faster and less error prone.

The above, as well as additional purposes, features, and advantages of the present invention will become apparent in the following detailed written description.

Brief Description of the Drawings

A preferred embodiment of the invention, as described in detail below, is shown in the drawings, in which FIG. 1 is a schematic flow diagram of a method of processing an error in a data processing device, in accordance with the preferred embodiment of the present invention; FIG. 2 is a schematic block diagram of a data processing device; FIG. 3 is a detailed flow diagram showing a part of the method of processing an error in a data processing device shown in FIG. 1, in accordance with the preferred embodiment of the present invention; FIG. 4 is a detailed flow diagram showing a different part of the method of processing an error in a data processing device shown in FIG. 1, in accordance with the preferred embodiment of the present invention; FIG. 5 is a detailed flow diagram showing another part of the method of processing an error in a data processing device shown in FIG. 1, in accordance with the preferred embodiment of the present invention; and FIG. 6 is a detailed flow diagram showing yet another part of the method of processing an error in a data processing device shown in FIG. 1, in accordance with the preferred embodiment of the present invention.

Detailed Description of the Preferred Embodiments

The main idea of the invention is to use the available state data from the real chip hardware and to feed the state data into a verification setup. This allows a much easier debugging of failures because of the convenient debugging features already available in a simulation environment.

This comprises tools like a viewing device for showing an all event trace (AET) which allows watching the values of all signals in a simulation model cycle by cycle. Also, a value of a signal can be traced back in a logic cone to see which of the input signals is causing a failure.

FIG. 1 shows a schematic flow diagram of a method of processing an error in a data processing device 10, in accordance with the preferred embodiment of the present invention, and FIG. 2 shows a schematic block diagram of an embodiment of the data processing device 10 which comprises a number of state holding elements 12.1 to 12.5 and a logic unit 14 with a number of combinatorial logic elements 14.1 to 14.5. For example, a signal of interest SOl inside the logic unit 14 shows up at an output of a third logic element 14.3. To analyze the signal of interest SOT the method of processing an error in a data processing device 10 shown in FIG. 1 is used.

Referring to FIG. 1, the shown embodiment of the method of processing an error in a data processing device 10 extracts in a step SlO an actual state of the data processing device 10.

During a step S20 the extracted actual state of the data processing device 10 is transformed into facilities and/or signal names used by a simulation model 22. In step S30 the transformed state of the data processing device 10 is load into a simulator 20 including the simulation model 22.

During step S40 required overrides for simulation like clock signals and/or extem stimuli are applied to the simulator 20. During step S50 simulation model 22 is run using the simulator 20 to evaluate the simulation model 22 and to generate output data 30 in form of an all event trace (AET) which can be analyzed to debug the error in the data processing device 10. The output data 30 can be generated in a single step to reconstruct transient signal values or in a simulation process generating a corresponding signal stream. In a step S60 the generated output data 30 is displayed on a viewing device to be analyzed to debug the error in the data processing device 10.

In the shown embodiment of the invention the simulator 20 is configured as a VHDL-Simulator, for example and the simulation model 22 is based on VHDL, for example (VHDL: Very High Speed Integrated Circuit Hardware Description Language).

FIG. 3 to FIG. 6 are showing different parts of the method of processing an error in a data processing device shown in FIG. 1 in detail.

Referring to FIG. 3, the step SlO of extracting the actual state of the data processing device 10 shown in FIG. 1 comprises a step S12 during which the state holding elements 12.1 to 12.5 of the data processing device 10 shown in FIG. 2 are connected together to form at least one scan chain 16. During step S14 values of the at least one scan chain 16 are read out using a not shown serial interface device. Tn a test (non-functional) mode, for example a special shift clock signal is used to shift out the values of the state holding elements 12.1 to 12.5 bit by bit. In this mode, the data processing device 10 behaves like one or more big shift register(s), depending on the number of scan chains 16. The data shifted out of the data processing device 10 is stored during step S16 in a "Chip Dump Data File" 18. This can be done by using state of the art scan chain tools which are described, for example in the above mentioned US-Patent 6,832,342 B2. The extracted state of the data processing device 10 comprises all readable state information of the at least one scan chain 16 and/or arrays and/or registers.

Referring to FIG. 4, the step S20 of transforming the extracted state of the data processing device in facilities and/or signal names used by the VHDL-Simulation-Model 22 comprises a step S21 during which the chip dump data file 18 is read in and parsed. Since the state holding elements 12.1 to 12.5 in the data processing device 10 are arranged in scan chains 16 to meet requirements for the test mode, which is completely separated from the functional mode, the data contained in the chip dump data file 18 has to be transformed in order to be usable for a simulation setup inside the VHDL-Simulator 20. So, after reading in and parsing the chip dump data file 18 during step S2 1, the bits in the chip dump data file 18 are descrambled during step S22 and rearranged in step S23 to bring the bits of the chip dump data file 18 in sequence and in correct order. For example, the bits of a bus may be scattered throughout the chip dump data file 18. They have to be extracted and put in sequence and in correct order. In addition, the chip dump data file 18 contains only individual bit values, while the chip design file (VHDL) uses a single element for multiple bits (e.g. a bus containing 64 bits). Therefore, during step S24 the bit values of the chip dump data file 18 are clustered in values corresponding with VHDL-Elements of the VHDL-Simulation-Model 22.

For a 4-bit wide bus latch, the algorithm in C-like notation would be, for example: bus_value = (bitO << 3) // bitO is MSB. Shift to left by 3 (bit 1 <<2) // Shift bit 1 left by 2 and OR to bitO (bit2 << 1) // Shift bit 2 left by 1 and or to bitO and biti (bit3 <<0); // Or bit3 to bitO, biti and bit2 The resulting bus_value would be <bitO, bit 1, bit2, bit3>.

The next step S25 in the transformation process is to transform names of the clustered bit values of the chip dump data file 18 into names used by the VHDL-Simulation-Model 22. During back end processing of the data processing device 10, the design hierarchy is flattened and the signal names may be modified by the backend tools (e.g. by appending an index number). Therefore the names of signals in the chip dump data file 18 need to be correlated to the names used in design. E.g. for the 4 bit wide bus latch, the individual bit signals may have names like bus bitO, busbiti, bus_bit2 and bus_bit3, which would correspond to the bus named bus latch(0 TO 3) in VHDL. The final steps in the transformation process is to map the facilities and/or signal names of said simulation model 22 to the values derived from the chip dump data file 18 during step S26 and to write them into a new file called "Model Initialization File" 28 during step S27. This model initialization file 28 contains initial values for all state holding facilities 12.1 to 12.5 in the data processing device 10. Again using the 4 bit wide bus latch example from above, the algorithm in C-like notation would be, for example: bus latch(0. .3) "<bus_value>" // replace <bus_value> with actual bit pattern.

Referring to FTG. 5, the step S50 of evaluating the VHDL-Simulation-Model 22 of the data processing device 10 comprises a step S5 1 during which the VHDL-Simulation-Model 22 is loaded into the VHDL-Simulator 20. During step S52 the model initialization file 28 is loaded into the VHDL-Simulator 20 to initialize the VHDL-Simulation-Model 22, wherein the simulator 20 assigns the values of the model initialization file 28 to facilities in the VHDL-Simulation-Model 22.

Depending on the user's choice, one way to run the VHDL-Simulation-Model 22 is to just evaluate the logic unit 14 without updating the state holding elements 12.1 to 12.5 during step S54 to generate a first all event trace 32 which is just one cycle long. This very quickly produces the first all event trace 32 which is just one cycle long, but contains all values for all of the signals in the VHDL-Simulation-Model 22, including combinatorial logic signal values of the signal of interest SOT showing a transient value reconstruction and solving the initial problem stated. With this method in place, it is very easy to investigate multiple logic cones with minimum effort.

In addition, the user has the choice to run one or more simulation cycle(s) during steps S55 and S56, wherein a single simulation cycle consists of an evaluation of the combinatorial logic plus the update of all state holding elements 12.1 to 12.5. The effort for this is bigger, because it is necessary to provide a correct clock stimulus and correct stimuli during step S55. One simple way to provide clock and input stimuli would be to write simple C++ drivers. Using this mode has the benefit that a checkpoint can be produced from real hardware which could be fed back into simulation. This allows to stop real hardware just short before an error state, and then switch over to simulation in order to get a second all event trace 34 of the history leading to an error state. The second all event trace 34 contains all values for all signals in the VHDL-Simulation-Model 22 including combinatorial logic signal values of the at least one logic unit 14 corresponding with the number of simulation cycles.

Referring to FIG. 6, the step S60 of displaying the state of the VHDL-Simulation-Model 22 of the data processing device 10 comprises a step S62 during which the all event trace 32, 34 is load in a viewing device, no matter which mode the all event trace 30 was created with. The visualization of the all event trace 30 during step S64 is done using state of the art tools like an all event trace 30 viewer.

The present invention can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment containing both hardware and software elements. Tn a preferred embodiment, the invention is implemented in software, which includes but is not limited to firmware, resident software, microcode, etc. Furthermore, the present invention can take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system. For the purposes of this description, a computer-usable or computer-readable medium can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.

The medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device) or a propagation medium. Examples of a computer-readable medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAIVI), a read-only memory (ROM), a rigid magnetic disk, and an optical disk. Current examples of optical disks include compact disk -read only memory (CD-ROM), compact disk -read/write (CD-RIW), and DVD.

A data processing system suitable for storing and/or executing program code will include at least one processor coupled directly or indirectly to memory elements through a system bus. The memory elements can include local memory employed during actual execution of the program code, bulk storage, and cache memories which provide temporary storage of at least some -10 -program code in order to reduce the number of times code must be retrieved from bulk storage during execution.

input/output or T/O devices (including but not limited to keyboards, displays, pointing devices, etc.) can be coupled to the system either directly or through intervening /O controllers.

Network adapters may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modems, and Ethernet cards are just a few of the currently available types of network adapters.

Embodiments of the present invention use the available state data from the real data processing device and feed it into a verification setup. This allows a much easier debug of failures because of the convenient debugging features already available in a simulation environment. This comprises tools like viewing devices which allow watching the value of all signals in a simulation model cycle by cycle. Also, a value of a signal can be traced back in a logic cone to see which of the input signals is causing a failure. So the method described above provides an efficient means to analyze and visualize chip dump data, because most parts of the method are reliable state of the art tools. The effort required to set up the transformation is much smaller than the effort to manually derive values for a logic cone. It is also much faster and less error prone.

Claims

CLAIMS1. A method of processing an error in a data processing device comprising at least one state holding element (12.1 to 12.5) and at least one logic unit (14) with at least one combinatorial logic element (14.1 to 14.5), said method comprising: extracting a state of said data processing device (10); transforming said extracted state of said data processing device (10) into facilities and/or signal names used by a simulation model (22); loading said transformed state of said data processing device (10) into a simulator (20) including said simulation model (22); and running said simulation model (22) using said simulator (20) generating output data (30) which can be analyzed to debug said error in said data processing device (10).
2. The method of claim 1, wherein extracting a state of said data processing device (10) comprises: connecting said state holding elements (12.1 to 12.5) of said data processing device (10) together to form at least one scan chain, wherein values of said at least one scan chain the are read out in a chip dump data file (18).
3. The method of claim 1 or 2, wherein said extracted state of said data processing device (10) comprises all readable state information of said at least one scan chain and/or arrays and/or registers.
4. The method according to anyone of claims 1 to 3, wherein transforming of said extracted state of said data processing device (10) in facilities and/or signal names used by a simulation model (22) comprises: reading in and parsing said chip dump data file (18); descrambling and rearranging of bits of said chip dump data file (18) to bring said bits in sequence and in correct order.
5. The method of claim 4, further comprising: clustering said bit values of said chip dump data file (18) in values corresponding with elements of said simulation model (22).

-12 -
6. The method of claim 5, further comprising: transforming names of said clustered bit values of said chip dump data file (18) into names used by said simulation model (22).
7. The method of claim 6, further comprising: mapping facilities and/or signal names of said simulation model (22) to said names derived from said chip dump data file (18).
8. The method of claim 7, further comprising: storing said mapped facilities and/or signal names into a model initialization file (28).
9. The method of claim 8, wherein said loading of said transformed state of said data processing device (10) into a simulator (20) including said simulation model (22) comprises: inputting of said model initialization file (28) to initialize said simulation model (22), wherein said simulator (20) assigns said values of said model initialization file (28) to facilities in said simulation model (22).
10. The method according to anyone of claims ito 9, wherein running said simulation model (22) using said simulator (20) comprises: evaluating said at least one logic unit (14) without updating said state holding elements (i2.i to 12.5) to generate an all event trace (32) which is just one cycle long.
11. The method according to claim 10, wherein said all event trace (32) contains all values for all signals in said simulation model (22) including combinatorial logic signal values of said at least one logic unit (14) and shows a transient value reconstruction.
12. The method according to anyone of claims ito 9, wherein running said simulation model (22) using said simulator (20) comprises: applying a clock signal and inputting extem stimuli to run at least one simulation cycle of said simulation model (22) to generate an all event trace (34) corresponding with the number of simulation cycles.
13. The method according to claim 12, wherein said all event trace (34) contains all values for all signals in said simulation model (22) including combinatorial logic signal values of said at -13 -least one logic unit (14) corresponding with said at least one simulation cycle and represents a history leading to said error state.
14. The method according to anyone of claims ito 13, wherein said generated output data (30, 32, 34) is displayed on a viewing device to be analyzed to debug said error in said data processing device (10).
15. The method according to anyone of claims 1 to 14, wherein said simulator (20) is configured as VHDL-Simulator and said simulation model (22) is based on VHDL.
16. The method according to anyone of claims ito 15, wherein said viewing device is an all events trace viewer.
17. A data processing program for execution in a data processing system comprising software code portions for performing a method of processing an error in a data processing device according to anyone of the preceding claims ito 16 when said program is run on said data processing system.
18. A computer program product stored on a computer-usable medium, comprising computer-readable program means for causing a computer to perform a method of processing an error in a data processing device according to anyone of the preceding claims ito 16 when said program is run on said computer.Amendments to the Claims have been filed as follows 1. A method of processing an error in the combinatorial logic (14) of a data processing device (10) comprising at least one state holding element (12.1 to 12.5) and at least one logic unit (14) with at least one combinatorial logic element (14.1 to 14.5), said method comprising: Extracting (S 10) a state from the at least one state holding elements (12.1 to 12.5) of said data processing device (10); transforming (S20) said extracted state of said data processing device (10) into a model initialization file (28) comprising facilities andlor signal names used by a simulation model (22); loading (S30) said model initialization file (28) into a simulator (20) to initialize (S52) said simulation model (22) included in said simulator (20); and running (S50) said simulation model (22) using said simulator (20) generating output data (30) which can be analyzed to debug said error in the combinatorial logic of said data processing device (10).2. The method of claim 1, wherein extracting a state of said data processing device (10) comprises: connecting said state holding elements (12.1 to 12.5) of said data processing device (10) together to form at least one scan chain, wherein values of said at least one scan chain the are read out in a chip dump data file (18).3. The method of claim I or 2, wherein said extracted state of said data processing device (10) comprises all readable state information of said at least one scan chain and/or arrays and/or registers. *.S. * * .*:.. 4. The method according to anyone of claims I to 3, wherein transforming of said extracted **** state of said data processing device (10) in facilities and/or signal names used by a simulation model (22) comprises: reading in and parsing said chip dump data file (18); descrambling and rearranging of bits of said chip dump data file (18) to bring said bits in * sequence and in correct order.5. The method of claim 4, further comprising: clustering said bit values of said chip dump data file (118) in values corresponding with elements of said simulation model (22).6. The method of claim 5, further comprising: transforming names of said clustered bit values of said chip dump data file (18) into names used by said simulation model (22).7. The method of claim 6, further comprising: mapping facilities andlor signal names of said simulation model (22) to said names derived from said chip dump data file (18).8. The method of claim 7, further comprising: storing said mapped facilities and/or signal names into a model initialization file (28).9. The method of claim 8, wherein said loading of said transformed state of said data processing device (10) into a simulator (20) including said simulation model (22) comprises: inputting of said model initialization file (28) to initialize said simulation model (22), wherein said simulator (20) assigns said values of said model initialization file (28) to facilities in said simulation model (22).10. The method according to anyone of claims 1 to 9, wherein running said simulation model (22) using said simulator (20) comprises: evaluating said at least one logic unit (14) without updating said state holding elements (12.1 to 12.5) to generate an all event trace (32) which is just one cycle long.11. The method according to claim 10, wherein said all event trace (32) contains all values for all signals in said simulation model (22) including combinatorial logic signal values of said at * : .: least one logic unit (14) and shows a transient value reconstruction. ***.* .. : 12. The method according to anyone of claims 1 to 9, wherein running said simulation model (22) using said simulator (20) comprises: applying a clock signal and inputting extern stimuli to run at least one simulation cycle of said simulation model (22) to generate an all event trace (34) corresponding with the number of simulation cycles.13. The method according to claim 12, wherein said all event trace (34) contains all values for all signals in said simulation model (22) including combinatorial logic signal values of said at least one logic unit (14) corresponding with said at least one simulation cycle and represents a history leading to said error state.14. The method according to anyone of claims I to 13, wherein said generated output data (30, 32, 34) is displayed on a viewing device to be analyzed to debug said error in said data processing device (10).15. The method according to anyone of claims ito 14, wherein said simulator (20) is configured as VHDL-Simulator and said simulation model (22) is based on VHDL.16. The method according to anyone of claims 1 to 15, wherein said viewing device is an all events trace viewer.17. A data processing program for execution in a data processing system comprising software code portions for performing a method of processing an error in the combinatorial logic (14) of a data processing device according to anyone of the preceding claims 1 to 16 when said program is run on said data processing system.* *,. 18. A computer program product stored on a computer-usable medium, comprising **. computer-readable program means for causing a computer to perform a method of processing an * error in the combinatorial logic (14) of a data processing device according to anyone of the * * preceding claims 1 to 16 when said program is run on said computer. **...*S * * *** * S * S. * 1. A method of processing an error in the combinatorial logic (14) of a data processing device (10) comprising at least one state holding element (12.1 to 12.5) and at least one logic unit (14) with at least one combinatorial logic element (14.1 to 14.5), said method comprising: Extracting (SlO) a state from the at least one state holding elements (12.1 to 12.5) of said data processing device (10); transforming (S20) said extracted state of said data processing device (10) into a model initialization file (28) comprising facilities and/or signal names used by a simulation model (22); loading (S30) said model initialization file (28) into a simulator (20) to initialize (S52) said simulation model (22) included in said simulator (20); and running (S50) said simulation model (22) using said simulator (20) generating output data (30) which can be analyzed to debug said error in the combinatorial logic of said data processing device (10).2. The method of claim 1, wherein extracting a state of said data processing device (10) comprises: connecting said state holding elements (12.1 to 12.5) of said data processing device (10) together to form at least one scan chain, wherein values of said at least one scan chain the are read out in a chip dump data file (18).3. The method of claim 1 or 2, wherein said extracted state of said data processing device (10) comprises all readable state information of said at least one scan chain and/or arrays and/or registers. *..* * * S* 4. The method according to anyone of claims I to 3, wherein transforming of said extracted state of said data processing device (10) in facilities and/or signal names used by a simulation model (22) comprises: *:** reading in and parsing said chip dump data file (18); descrambling and rearranging of bits of said chip dump data file (18) to bring said bits in : sequence and in correct order.5. The method of claim 4, further comprising: clustering said bit values of said chip dump data file (18) in values corresponding with elements of said simulation model (22).6. The method of claim 5, further comprising: transforming names of said clustered bit values of said chip dump data file (18) into names used by said simulation model (22).7. The method of claim 6, further comprising: mapping facilities and/or signal names of said simulation model (22) to said names derived from said chip dump data file (18).8. The method of claim 7, further comprising: storing said mapped facilities and/or signal names into a model initialization file (28).9. The method of claim 8, wherein said loading of said transformed state of said data processing device (10) into a simulator (20) including said simulation model (22) comprises: inputting of said model initialization file (28) to initialize said simulation model (22), wherein said simulator (20) assigns said values of said model initialization file (28) to facilities in said simulation model (22).10. The method according to anyone of claims 1 to 9, wherein running said simulation model (22) using said simulator (20) comprises: evaluating said at least one logic unit (14) without updating said state holding elements (12.1 to 12.5) to generate an all event trace (32) which is just one cycle long. *. * d11. The method according to claim 10, wherein said all event trace (32) contains all values for all signals in said simulation model (22) including combinatorial logic signal values of said at *,.*e least one logic unit (14) and shows a transient value reconstruction.** : 12. The method according to anyone of claims 1 to 9, wherein running said simulation model (22) using said simulator (20) comprises: applying a clock signal and inputting extern stimuli to run at least one simulation cycle of said simulation model (22) to generate an all event trace (34) corresponding with the number of simulation cycles.13. The method according to claim 12, wherein said all event trace (34) contains all values for all signals in said simulation model (22) including combinatorial logic signal values of said at least one logic unit (14) corresponding with said at least one simulation cycle and represents a history leading to said error state.14. The method according to anyone of claims I to 13, wherein said generated output data (30, 32, 34) is displayed on a viewing device to be analyzed to debug said error in said data processing device (10).15. The method according to anyone of claims I to 14, wherein said simulator (20) is configured as VHDL-Simulator and said simulation model (22) is based on VHDL.16. The method according to anyone of claims I to 15, wherein said viewing device is an all events trace viewer.17. A data processing program for execution in a data processing system comprising software code portions for performing a method of processing an error in the combinatorial logic (14) of a data processing device according to anyone of the preceding claims ito 16 when said program is run on said data processing system.*... 18. A computer program product stored on a computer-usable medium, comprising * * . ::..: computer-readable program means for causing a computer to perform a method of processing an ** . error in the combinatorial logic (14) of a data processing device according to anyone of the preceding claims 1 to 16 when said program is run on said computer.S 5*5*5 * S * S. . S