GB2486916A

GB2486916A - A multi-band switchable low-noise receiver amplifier with notch filters

Info

Publication number: GB2486916A
Application number: GB1022115.8A
Authority: GB
Inventors: Waleed Fouad Aboueldahab
Original assignee: Genasic Design Systems Ltd
Current assignee: Genasic Design Systems Ltd
Priority date: 2010-12-31
Filing date: 2010-12-31
Publication date: 2012-07-04
Anticipated expiration: 2030-12-31
Also published as: GB2486916B; GB201022115D0

Abstract

A multi-band switchable low-noise receiver amplifier with notch filters Input signals in different bands are received at ports 311,321,331 and coupled to input transistors 310,320,330, one of which is enabled by a gate bias signal. The gate-drain capacitor of each inactive transistor, in conjunction with the respective inactive input port impedance, provides a set of series resonant notches in the transfer function of the active transistor. The notches attenuate blocker signals and transmitter leakage signals. The capacitors may be provided as varactors or as capacitor banks.

Description

LOW NOISE AMPLIFIER

The present invention relates to a low noise amplifier, in particular a multi-band low noise amplifier.

Modern wireless communication devices are typically required to operate in a plurality of frequency bands, for example the GSM communication standard allows for communication to occur in up to four different frequency bands. Similarly, the Long Term Evolution LTE communication standard allows for communication to occur in several frequency bands.

To allow a received signal to be processed, conventional wireless communication devices having a multi-band receiver front end will typically include a plurality of low noise amplifiers LNA's that are used to amplify the weak received signals, where a separate low noise amplifier is assigned to each respective frequency band.

However, the use of multiple LNA's within a receiver can require a large semiconductor area with long interconnect routings required over a large area, which has the disadvantage of increasing production costs and increased device size.

To overcome this problem there has been a drive to develop single LNA devices that can support multiple frequency bands. One such solution has been the use of LNA's with multiple input transistors, where each transistor acts as an amplifier stage for a respective frequency band, such an example is illustrated in Figure 1. In this example, a first transistor, having a first input, is arranged to act as LNA driver stage for a first frequency band with a second transistor, having a second input, being arranged to act as an LNA driver stage for a second frequency band, where the unused transistor can be powered down by pulling the DC bias voltage at the respective input to OV. Figure 2 illustrates a similar LNA configuration with each multiple driver stages having a differential topology.

Additionally, for frequency division duplex (FDD)operation, power levels associated with transmitter leakage and blocker signals at the receiver front end can be at an undesirable level. To minimise the effects of leakage and blocker signals one solution has been the use of SAW filters, however SAW filters can be bulky and expensive. An alternative solution has been to use a highly linear receiver front end; however these receivers typically have a high current consumption.

Further, for time division duplex operation, the blocker signals at the receiver front end can also be at a non desirable level.

Accordingly, there is a need for an improved multi-band receiver having high transmitter leakage and blocker rejection.

In accordance with an aspect of the present invention there is provided a low noise amplifier and method according to the accompanying claims.

This provides the advantage of allowing a notch to be created in the receive gain response of an LNA using an on-chip feedback capacitance, or other element, as a feedback circuit between the drain and gate of a transistor while also making use of the termination impedance of unused IJNA ports. This has the advantage of minimising cost, size and complexity of the LNA circuit while providing a suitable frequency response. The claimed invention also allows existing off-chip matching networks, including active or passive rf front end circuitry, for unused ports within a multi-band IJNA to define the characteristics of the created notches.

The present invention will now be described, by way of example, with reference to the accompanying drawings, in which:

Figure 1 illustrates a first prior art LNA;

Figure 2 illustrates a second prior art LNA;

Figure 3 illustrates a IJNA according to an embodiment of the present invention; Figure 4 illustrates a frequency response of an LNA according to an embodiment of the present invention having two notches.

Figure 3 illustrates a three port LNA, where each port supports a specific frequency band within a multi-band communication system. Although the present embodiment illustyates a three port LNA, the IJNA can have any number of ports.

The IJNA 300 illustrated in Figure 3 has three driver stages 310, 320, 330, where each port (i.e. input) 311, 321,, 331 is arranged to control the operation of a respective driver stage. Each of the driver stages 310, 320, 330 in the LNA have two field effect transistors (FET) 341, 342 configured as a differential amplifier, where the source of the respective FET's are coupled together and the drains of the respective FET's are coupled together. That is to say, the three driver stages share the drain and source of the LNA transistors.

Although the present embodiment illustrates each driver stage as being a differential amplifier, a single transistor can be used. :ic

Coupled between the drain and gate of the respective transistors is a passive device that acts as a feedback circuit. When one of the transistors is inactive the respective passive device is connected between the gate of the inactive device and its drain, which is a shared drain between the active and inactive devices. The passive device, in addition to off-chip circuitry at the gate of the inactive device, creates a series resonance circuit at the shared drain that creates a notch filter effect for the active device output current at the shared drain node and thus creates a notch filter effect in the whole LNA response with its centre frequency and level of attenuation dependent on the passive feedback capacitor and the off-chip circuitry and termination.

For the purposes of the present embodiment, the passive device that creates a feedback circuit between the drain and gate of the respective transistors is a capacitor 350, where to allow the loading effect of an inactive port on an active port to be varied the feedback capacitor is preferably a variable capacitor. However, other elements may be used, for

example an inductor.

Coupled to the drain is a cascode transistor 360. The cascode transistor 360 improves input-output isolation by decoupling the output from the input as is well known to a person skilled in the art and will not, for the purposes of the present description be described in any further detail.

The respective driver stage inputs (i.e. ports) 311, 321, 331 control the gate voltage at the respective FET's.

An off-chip matching network (not shown) is coupled to the respective IJNA ports. The matching network allows power transfer to be maximised through input/output impedance matching.

During operation of the]IJNA 300, one of the driver stages is made active by applying a bias voltage to the respective port (i.e. gate) . The other two driver stages are made inactive by reducing the bias voltage, where the circuitry connected to the inactive ports of the LNA are used to create notches in the]IJNA gain response of the active port using the feedback capacitors to create a series resonance loading effect, as described above.

In particular, the creation of notches achieved through the use of the internal feedback capacitors 350 coupled between the drain and gate of the inactive transistors inside the IJNA and the off chip circuitry connected to the gate of the inactive transistors has the effect of creating a series resonance notch filter, where the number of notches is dependent upon the number of inactive driver stages. That is to say, for an IJNA having three driver stages the two inactive driver stages can be used to create a respective notch, thereby allowing a two notch filter to be created.

For a four driver stage LNA a three notch filter can be created.

The location of a notch in the]IJNA frequency response can be made variable by adjusting the feedback capacitance value and the attenuation value will be dependent on the Q of the off chip network and its termination.. For example the capacitance value can be varied digitally or by means of an integrated varactor. :ic

By varying on-chip capacitance values, for example through the use of a capacitance bank, the position of notches created in the frequency response will vary across a centre point that is dependent on the off-chip circuitry resonance frequency, where the feedback capacitor and the off chip circuitry forms a resonance circuit.

Off-chip components will typically also be used to determine the actual band of operation.

To create a plurality of notches at different frequencies within the LNA frequency response, the feedback capacitor 350 for each inactive driver stage is selected to have a different loading effect, together with the off-chip circuitry, on the active driver stage. The variable capacitor will typically vary between values of 50fF and lpF dependent upon the required notch frequency range.

Figure 4 illustrates a frequency response of a three driver stage IJNA, where the loading effect of a capacitor coupled between the drain and gate of a first inactive FET, together with off-chip circuitry, is used to create a first notch at 1.7 GHz and the loading effect of a capacitor coupled between the drain and gate of a second inactive FF1, together with the off-chip circuitry, is used to create a second notch at 2.35 GHz, with the LNA gain of the active FF1 being centred at 2.1 GHz.

If additional notches are required dummy ports can be implemented, where the dummy ports are used to create notches within the IJNA frequency response in the same manner as for the existing inactive ports. Dummy ports are identical to the other IJNA input ports, their purpose would be to simply provide frequency nulls in the wanted signal band of the used LNA inputs.

It will be apparent to those skilled in the art that the disclosed subject matter may be modified in numerous ways and may assume embodiments other than the preferred forms specifically set out as described above, for example the feedback capacitor can be located of chip.

Claims

CLAIMS1. A low noise amplifier comprising a first transistor and a second transistor that have a shared drain and source, wherein a first feedback circuit is provided between the drain and gate of the second transistor that is arranged to have a loading effect on the gain response of the first transistor when a first DC bias voltage is applied to the first transistor to make the first transistor active and a second DC bias voltage is applied to the second transistor to make the second transistor inactive, wherein the loading effect is arranged to create a notch in the gain response of the first transistor.
2. A low noise amplifier according to claim 1, wherein a second feedback circuit is provided between the drain and gate of the first transistor that is arranged to have a loading effect on the gain response of the second transistor when a first DC bias voltage is applied to the second transistor to make the second transistor active and a second DC bias voltage is applied to the first transistor to make the first transistor inactive, wherein the loading effect is arranged to create a notch in the gain response of the second transistor.
3. A low noise amplifier according to claim 1 or 2, wherein the first and second feedback circuit includes a capacitor or other element that creates the loading effect.
4. A low noise amplifier according to any one of the preceding claims, wherein the first and/or second feedback circuit includes a variable capacitor.
5. A low noise amplifier according to any one of the preceding claims, wherein the first transistor has a corresponding differential transistor, wherein the first transistor and the corresponding differential transistor form a first driver stage.
6. A low noise amplifier according to claim 5, wherein the second transistor has a corresponding differential transistor, wherein the second transistor and the corresponding differential transistor form a second driver stage.
7. A low noise amplifier according to any one of the preceding claims, wherein the first feedback circuit is coupled to a first inductor.
8. A low noise amplifier according to claim 7, wherein the first inductor is mounted external to the low noise amplifier.
9. A low noise amplifier according to claim 2, wherein the second feedback circuit is coupled to a second inductor.
10. A low noise amplifier according to claim 9, wherein the second inductor is mounted external to the low noise amplifier.
11. A low noise amplifier according to any one of claims 3 to 10 when dependent upon claim 2, further comprising a third transistor that have a shared drain and source with the first transistor and the second transistor, -10 -wherein the first feedback circuit and the second feedback circuit are arranged to have a loading effect on the gain response of the third transistor when a first DC bias voltage is applied to the third transistor to make the third transistor active and a second DC bias voltage is applied to the first and second transistor to make the first and second transistor inactive, wherein the loading effect of the first feedback circuit is arranged to create a first notch in the gain response of the third transistor and the loading effect of the second feedback circuit is arranged to create a second notch in the gain response of the third transistor.
12. A receiver having a low noise amplifier formed on a semiconductor chip according to any one of the preceding claims and off chip circuitry coupled to the low noise amplifier that is arranged to have a loading effect on the gain response of the first transistor.
13. A method of operating a low noise amplifier according to claim 1, the method comprising applying a first DC bias voltage to the first transistor to make the first transistor active and applying a second DC bias voltage to the second transistor to make the second transistor inactive to create a notch in the gain response of the first transistor.