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GB2494739B - Trench isolation structure - Google Patents

Trench isolation structure

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Publication number
GB2494739B
GB2494739B GB1210467.5A GB201210467A GB2494739B GB 2494739 B GB2494739 B GB 2494739B GB 201210467 A GB201210467 A GB 201210467A GB 2494739 B GB2494739 B GB 2494739B
Authority
GB
United Kingdom
Prior art keywords
trench isolation
source
isolation structure
gate stack
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
GB1210467.5A
Other versions
GB201210467D0 (en
GB2494739A (en
Inventor
Reinaldo Ariel Vega
Michael Vincent Aquilino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB201210467D0 publication Critical patent/GB201210467D0/en
Publication of GB2494739A publication Critical patent/GB2494739A/en
Application granted granted Critical
Publication of GB2494739B publication Critical patent/GB2494739B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/608—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having non-planar bodies, e.g. having recessed gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/795—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in lateral device isolation regions, e.g. STI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)

Abstract

A trench isolation structure and method of forming the trench isolation structure are disclosed. The method includes forming a shallow trench isolation (STI) structure having an overhang and forming a gate stack. The method further includes forming source and drain recesses adjacent to the STI structure and the gate stack. The source and drain recesses are separated from the STI structure by substrate material. The method further includes forming epitaxial source and drain regions associated with the gate stack by filling the source and drain recesses with stressor material.
GB1210467.5A 2011-09-15 2012-06-13 Trench isolation structure Active GB2494739B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/233,058 US8623713B2 (en) 2011-09-15 2011-09-15 Trench isolation structure

Publications (3)

Publication Number Publication Date
GB201210467D0 GB201210467D0 (en) 2012-07-25
GB2494739A GB2494739A (en) 2013-03-20
GB2494739B true GB2494739B (en) 2013-09-11

Family

ID=46605882

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1210467.5A Active GB2494739B (en) 2011-09-15 2012-06-13 Trench isolation structure

Country Status (3)

Country Link
US (2) US8623713B2 (en)
DE (1) DE102012215365B4 (en)
GB (1) GB2494739B (en)

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US8629040B2 (en) 2011-11-16 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for epitaxially growing active regions between STI regions
US8916443B2 (en) * 2012-06-27 2014-12-23 International Business Machines Corporation Semiconductor device with epitaxial source/drain facetting provided at the gate edge
US9059196B2 (en) 2013-11-04 2015-06-16 International Business Machines Corporation Bipolar junction transistors with self-aligned terminals
US9246005B2 (en) 2014-02-12 2016-01-26 International Business Machines Corporation Stressed channel bulk fin field effect transistor
US9330959B2 (en) 2014-04-13 2016-05-03 Texas Instruments Incorporated Isolated semiconductor layer in bulk wafer by localized silicon epitaxial seed formation
CN104103569A (en) * 2014-07-25 2014-10-15 上海华力微电子有限公司 Forming method of shallow groove isolation structure
CN104091779B (en) * 2014-07-25 2017-02-15 上海华力微电子有限公司 Shallow trench isolation structure forming method
CN104392956A (en) * 2014-11-26 2015-03-04 上海华力微电子有限公司 Semiconductor device manufacturing method
CN104409412A (en) * 2014-11-26 2015-03-11 上海华力微电子有限公司 STI (shallow trench isolation) edge epitaxial layer performance improving method and corresponding semiconductor structure
CN106505029B (en) * 2015-09-08 2019-11-01 中芯国际集成电路制造（天津）有限公司 Fleet plough groove isolation structure and forming method thereof, cmos image sensor
US20170141228A1 (en) * 2015-11-16 2017-05-18 Taiwan Semiconductor Manufacturing Co., Ltd. Field effect transistor and manufacturing method thereof
CN106847698B (en) * 2015-12-07 2019-09-27 中芯国际集成电路制造(上海)有限公司 Semiconductor device and method for improving performance of semiconductor device
US10475707B2 (en) 2016-02-02 2019-11-12 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US10439026B2 (en) * 2017-10-17 2019-10-08 Globalfoundries Inc. Fins with single diffusion break facet improvement using epitaxial insulator
CN109786337B (en) * 2017-11-13 2020-09-08 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and method of forming the same
CN110246803A (en) * 2018-03-08 2019-09-17 联华电子股份有限公司 Semiconductor element and preparation method thereof
US11424346B2 (en) * 2020-06-30 2022-08-23 Nanya Technology Corporation Semiconductor device with programmable feature and method for fabricating the same

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US5940716A (en) * 1996-03-15 1999-08-17 Samsung Electronics Co., Ltd. Methods of forming trench isolation regions using repatterned trench masks
US6093621A (en) * 1999-04-05 2000-07-25 Vanguard International Semiconductor Corp. Method of forming shallow trench isolation
US6137152A (en) * 1998-04-22 2000-10-24 Texas Instruments - Acer Incorporated Planarized deep-shallow trench isolation for CMOS/bipolar devices
US6242788B1 (en) * 1997-08-01 2001-06-05 Nippon Steel Corporation Semiconductor device and a method of manufacturing the same
US6368973B1 (en) * 2000-09-25 2002-04-09 Vanguard International Semiconductor Corp. Method of manufacturing a shallow trench isolation structure
US6383877B1 (en) * 1999-05-20 2002-05-07 Samsung Electronics Co., Ltd. Method of forming T-shaped isolation layer, method of forming elevated salicide source/drain region using the same, and semiconductor device having T-shaped isolation layer
WO2005038875A2 (en) * 2003-10-16 2005-04-28 International Business Machines Corp. High performance strained cmos devices
US20050124107A1 (en) * 2001-08-13 2005-06-09 Renesas Technology Corp. Method of fabricating a semiconductor device with a trench isolation structure and semiconductor device

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* Cited by examiner, † Cited by third party
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US5940716A (en) * 1996-03-15 1999-08-17 Samsung Electronics Co., Ltd. Methods of forming trench isolation regions using repatterned trench masks
US6242788B1 (en) * 1997-08-01 2001-06-05 Nippon Steel Corporation Semiconductor device and a method of manufacturing the same
US6137152A (en) * 1998-04-22 2000-10-24 Texas Instruments - Acer Incorporated Planarized deep-shallow trench isolation for CMOS/bipolar devices
US6093621A (en) * 1999-04-05 2000-07-25 Vanguard International Semiconductor Corp. Method of forming shallow trench isolation
US6383877B1 (en) * 1999-05-20 2002-05-07 Samsung Electronics Co., Ltd. Method of forming T-shaped isolation layer, method of forming elevated salicide source/drain region using the same, and semiconductor device having T-shaped isolation layer
US6368973B1 (en) * 2000-09-25 2002-04-09 Vanguard International Semiconductor Corp. Method of manufacturing a shallow trench isolation structure
US20050124107A1 (en) * 2001-08-13 2005-06-09 Renesas Technology Corp. Method of fabricating a semiconductor device with a trench isolation structure and semiconductor device
WO2005038875A2 (en) * 2003-10-16 2005-04-28 International Business Machines Corp. High performance strained cmos devices

Also Published As

Publication number Publication date
DE102012215365B4 (en) 2014-11-13
US8623713B2 (en) 2014-01-07
US20130069160A1 (en) 2013-03-21
US20130146985A1 (en) 2013-06-13
US8704310B2 (en) 2014-04-22
GB201210467D0 (en) 2012-07-25
DE102012215365A1 (en) 2013-03-21
GB2494739A (en) 2013-03-20

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