GB2632646A

GB2632646A - Structure including mechanical and photonic features

Info

Publication number: GB2632646A
Application number: GB2312272.4A
Authority: GB
Inventors: Lia Li Ying; M Fitzgerald Alissa; Beaudry Richard
Original assignee: Zero Point Motion Ltd
Current assignee: Zero Point Motion Ltd
Priority date: 2023-08-10
Filing date: 2023-08-10
Publication date: 2025-02-19
Also published as: WO2025032338A1; GB202312272D0

Abstract

A structure 700 includes a photonic integrated circuit (PIC) layer 701 with optical structure(s) 721 each having corresponding optical field(s), a sacrificial layer 727 and a micro-electromechanical system (MEMS) structural layer 705. At least one first gap 723 is formed in the PIC layer 701 defining at least one first portion 725 which is on an opposite side to where the optical structure(s) are located. The MEMS structure is suspended adjacent to the at least one first portion of the PIC layer, defined by at least one second gap in the MEMS structural layer. The sacrificial layer separates the PIC layer from the MEMS structural layer. Part of the sacrificial layer is absent so that the at least one first gap is open to the at least one second gap. The at least one first portion of the PIC layer is mechanically coupled to the MEMS structure allowing movement when the MEMS structure deflects under the application of a force or perturbation. A change in spacing between the at least one first portion and the optical structure causes a change in its optical field characteristic. An apparatus may include this structure, detector(s) and processor(s). A wafer may include these structures.

Description

STRUCTURE INCLUDING MECHANICAL AND PHOTONIC FEATURES

[0001] The present disclosure relates generally to a structure comprising a mechanical and/or electromechanical layer and a photonic layer, and the present disclosure also includes manufacturing methods thereof. Various examples disclosed herein relate to a chip, or structure, comprising micro-electro-mechanical (MEMS) structures and photonic integrated circuit (PIC) structures (e.g., via a MEMS layer and a PIC layer), with attachment or bonding between the structures, directly and/or indirectly. According to various examples, a MEMS-photonics circuit or chip comprises one or more optical structure(s) in a PIC layer and one or more MEMS structure(s) in a MEMS layer, with a displacement of the MEMS structure resulting in a change in a characteristic of an optical field associated with one or more of the optical structure(s). According to various examples, such a circuit or chip is included in a wafer comprising additional circuit(s)/chip(s).

BACKGROUND

[0002] A micro-electro-mechanical system, MEMS, is a microscopic device which includes both electronic and moving parts. A MEMS structure may have a thickness in the order of a few to tens of micrometres, e.g., greater than 1pm.

[0003] A photonic integrated circuit, PIC, (or an integrated optical circuit) is also a microscopic device, and may include a number of photonic components which form a functioning circuit. A PIC structure may have a thickness in the order of hundreds of nanometres, e.g., 70-1000nm.

[0004] Compared to a PIC structure, a MEMS structure may be very thick. Furthermore, a structure which makes use of functionality arising from combinations of MEMS features and PIC features may require a small distance (e.g., less than 1pm) between a MEMS structure and a PIC structure. This distance may be required in several dimensions if a combination of PIC structures with one or more MEMS structures are implemented, e.g., a MEMS structure may need to be located within 1pm of a PIC structure in a first direction, and the MEMS structure may need to be located within 1pm of another PIC structure in a second direction (e.g., perpendicular to the first direction). Yet further increasing the complexity, additional PIC structures may be located on the opposite sides of the MEMS structure relative to the PIC structures already described, again requiring a distance of less than 1pm between respective PIC and MEMS structures.

[0005] Using conventional processes for fabricating MEMS or PIC, respectively, it is very difficult to fabricate a structure combining MEMS features and PIC features owing to the mismatch in dimensions, and existing wafer bonding methods for joining separately fabricated MEMS and PIC wafers provide a number of disadvantages such as low alignment accuracy between MEMS and PIC wafer features. Further, techniques used to create MEMS structures inherently create variation in dimension(s), such that even if a wafer bond is accurate, the features on the two bonded wafers may differ in location and/or dimension.

SUMMARY

[0006] It is an aim of certain examples of the present disclosure to address, solve and/or mitigate, at least partly, at least one of the problems and/or disadvantages associated with the related art, for example at least one of the problems and/or disadvantages described herein. It is an aim of certain examples of the present disclosure to provide at least one advantage over the related art, for example at least one of the advantages described herein.

[0007] In various examples of the present disclosure, such as a 1st example, there is provided a structure comprising: a photonic integrated circuit (PIC) layer, wherein at least one first gap is formed in the PIC layer to define at least one first portion, and the PIC layer comprises one or more optical structures each having a corresponding optical field and located on an opposite side of one of the at least one first gap to one of the at least one first portion of the PIC layer; a micro-electro-mechanical system (MEMS) structural layer comprising a MEMS structure suspended adjacent to the at least one first portion of the PIC layer and defined by at least one second gap in the MEMS structural layer, the MEMS structure deflectable under the application of a force or a perturbation; and a sacrificial layer arranged to separate at least a first part of the PIC layer from at least a first part of the MEMS structural layer, wherein a first part of the sacrificial layer is absent such that the at least one first gap is open to the at least one second gap; wherein the at least one first portion of the PIC layer is mechanically coupled to the MEMS structure so as to move according to a deflection of the MEMS structure; and wherein a change in a spacing between the at least one first portion and an optical structure of the one or more optical structures causes a change in an optical field characteristic of that optical structure.

Advantageously, such a structure may allow for sensing changes in optical field characteristics in-plane, or substantially so, with the PIC layer (or, more specifically, the optical structure), allowing for one or more associated factors (e.g., a displacement, velocity or acceleration of the MEMS structure or at least one first portion) to be derived.

[0008] In another example of the present disclosure, there is provided a structure comprising: a photonic integrated circuit (PIC) layer, wherein at least one first gap is formed in the PIC layer to define at least one first portion, and the PIC layer comprises one or more optical structures each having a corresponding optical field and located on an opposite side of one of the at least one first gap to one of the at least one first portion of the PIC layer; a micro-electro-mechanical system (MEMS) structural layer comprising a MEMS structure suspended adjacent to the at least one first portion of the PIC layer, the MEMS structure deflectable under the application of a force or a perturbation; and a sacrificial layer arranged to separate at least a first part of the PIC layer from at least a first part of the MEMS structural layer, wherein a first part of the sacrificial layer is absent between the MEMS structure and the at least one first portion of the PIC layer; wherein the at least one first portion of the PIC layer is mechanically coupled to the MEMS structure so as to move according to a deflection of the MEMS structure; and wherein a change in a spacing between the at least one first portion and an optical structure of the one or more optical structures causes a change in an optical field characteristic of that optical structure. This may provide similar advantages as in the 1" example.

[0009] In various examples, such as a 2" example, there is provided a structure in accordance with any of the above, such as that of the 1st example, wherein the at least one first portion is electrically coupled to the MEMS structure.

[0010] In various examples, such as a 3' example, there is provided a structure in accordance with any of the above, such as that of the lst example or the 2' example, wherein the structure comprises at least one coupling element, and the mechanical coupling between the at least one first portion of the PIC layer and the MEMS structure is provided by the at least one coupling element.

[0011] In various examples, such as a 4th example, there is provided a structure in accordance with any of the above, such as that of the 3rd example, wherein the at least one coupling element is configured to electrically couple the at least one first portion to the MEMS structure; or wherein the integrated circuit further comprises at least one coupler configured to electrically couple the PIC layer to the MEMS structure. Advantageously, providing both mechanical and electrical coupling via the at least one coupling element may increase functionality.

[0012] In various examples, such as a 5th example, there is provided a structure in accordance with any of the above, such as that of the 3rd example or the 4th example, wherein the at least one coupling element comprises polysilicon, doped polysilicon, crystalline silicon, doped crystalline silicon, an electrically conducting material or a semiconducting material.

[0013] In various examples, such as a 6th example, there is provided a structure in accordance with any of the above, such as that of any of the 3rd to 5th examples, wherein each of the at least one coupling element is formed in a via through a part of one of the at least one first portion to a part of the MEMS structure, wherein the MEMS structure is noncontiguous with the at least one first portion.

[0014] In various examples, such as a 7th example, there is provided a structure in accordance with any of the above, such as that of the 6th example, further comprising a cavity provided under the at least one first portion on a side of the at least one first portion opposite to a side of the at least one first portion on which the MEMS structure is located. Advantageously, this may allow the at least one first portion to move more freely, e.g. in a direction perpendicular to a plane in which the PIC layer extends.

[0015] In various examples, such as an 8th example, there is provided a structure in accordance with any of the above, such as that of any of the 3rd to 5th examples, wherein the at least one coupling element is provided by a second part of the sacrificial layer between the MEMS structure and the at least one first portion, wherein the MEMS structure is non-contiguous with the at least one first portion. Advantageously, this may provide an alternative to forming the at least one coupling element using via(s), which may reduce a complexity in providing the at least one coupling element.

[0016] In various examples, such as a 9th example, there is provided a structure in accordance with any of the above, such as that of the 8th example, further comprising a cavity provided under the MEMS structure on a side of the MEMS structure opposite to a side of the MEMS structure on which the at least one first portion is located.

[0017] In various examples, such as a 10th example, there is provided a structure in accordance with any of the above, such as that of any of the 6th to 9th examples, wherein the MEMS structure is defined by the at least one second gap opened in the MEMS structural layer around the MEMS structure, to separate the MEMS structure from the remaining part of the MEMS structural layer.

[0018] In various examples, such as an 11th example, there is provided a structure in accordance with any of the above, such as that of any of the 3rd to 5th examples, wherein the at least one coupling element or the MEMS structure is formed through depositing material on the at least one first portion to provide the MEMS structure contiguous with, and mechanically coupled to, the at least one first portion. Advantageously, this may provide an alternative to forming the at least one coupling element using via(s), which may reduce a complexity in providing the at least one coupling element; or may provide a method of forming both MEMS structure and coupling element(s) together.

[0019] In various examples, such as a 12th example, there is provided a structure in accordance with any of the above, such as that of the 11th example, wherein the at least one coupling element is formed by epitaxial deposition on the at least one first portion and on at least part of the sacrificial layer to grow a first mass of first material on the at least one first portion and a second mass of second material on the sacrificial layer; wherein the first mass and the second mass correspond to the MEMS structural layer and the first layer comprises the MEMS structure; and wherein the at least one coupling element corresponds to a bonding region between the at least one first portion and the first mass.

[0020] In various examples, such as a 13'h example, there is provided a structure in accordance with any of the above, such as that of the 12'h example, wherein the PIC layer is formed of silicon; the sacrificial layer is formed of an oxide; the first material is crystalline silicon formed by silicon epitaxial deposition onto the PIC layer; and the second material is polysilicon formed by silicon epitaxial deposition onto the sacrificial layer.

[0021] In various examples, such as a 14th example, there is provided a structure in accordance with any of the above, such as that of any of the 11th to 13'h examples, wherein the at least one second gap is formed in the second mass around the first mass, and the at least one second gap is arranged to connect or align with the at least one first gap.

[0022] In various examples, such as a 15th example, there is provided a structure in accordance with any of the above, such as that of the 10th example or the 14th example, wherein each of the at least one first gap is a gap of between 100nm to 500nm; and/or wherein each of the at least one second gap around the MEMS structure is larger than each of the at least one first gap.

[0023] In various examples, such as a 16th example, there is provided a structure in accordance with any of the above, such as that of any of the 1st to 15th examples, wherein the PIC layer further comprises: one or more input waveguides each configured to provide input light to one of the one or more optical structures; and one or more output waveguides each configured to receive output light from one of the one or more optical structures.

[0024] In various examples, such as a 17'h example, there is provided a structure in accordance with any of the above, such as that of any of the 1st to 16th examples, wherein the one or more optical structures are optical resonators and the optical field characteristic is an optical resonance characteristic.

[0025] In various examples, such as an 18'h example, there is provided a structure in accordance with any of the above, such as that of the 17th example, wherein the change in the optical field characteristic is a shift in the optical resonance and/or a broadening or deepening of the curve of the optical resonance.

[0026] In various examples, such as a 19th example, there is provided a structure in accordance with any of the above, such as that of any of the 1st to 18th examples, wherein the structure comprises two optical structures; and wherein a change in a first spacing between a first of the at least one first portion and a first of the optical structures and a change in a second spacing between a second of the at least one first portion and a second of the optical structures causes a differential change in the optical field characteristic of the first and the second of the at least two optical structures.

[0027] In various examples, such as a 20th example, there is provided a structure in accordance with any of the above, such as that of any of the is' to 19th examples, wherein at least one active optical structure is formed on the PIC layer.

[0028] In various examples of the present disclosure, such as a 21st example, there is provided a method of manufacturing a structure, the method comprising: preparing a stacked structure comprising a photonic integrated circuit (PIC) layer by: forming, in the PIC layer, at least one first gap to define at least one first portion; and forming, in the PIC layer, one or more optical structures, each having a corresponding optical field, wherein each of the one or more optical structures is located on an opposite side of one of the at least one first gap to one of the at least one first portion, wherein the stacked structure further comprises a sacrificial layer adjacent to the PIC layer; and providing, in a micro-electro-mechanical system (MEMS) structural layer, a MEMS structure mechanically coupled to and suspended adjacent to the at least one first portion, such that the MEMS structure is deflectable under the application of a force or a perturbation, and a deflection of the MEMS structure moves the at least one first portion; wherein the MEMS structure is defined in the MEMS structural layer by at least one second gap; wherein the sacrificial layer is arranged to separate at least a first part of the PIC layer from at least a first part of the MEMS structural layer, wherein a first part of the sacrificial layer is absent such that the at least one first gap is open to the second gap; and wherein a change in a spacing between the at least one first portion and an optical structure of the one or more optical structures causes a change in an optical field characteristic of that optical structure.

[0029] In various examples, such as a 22nd example, there is provided a method in accordance with any of the above, such as that of the 21st example, further comprising electrically coupling the at least one first portion to the MEMS structure.

[0030] In various examples, such as a 23'd example, there is provided a method in accordance with any of the above, such as that of the 21st or 22" example, further comprising providing at least one coupling element in the structure to mechanically couple the at least one first portion of the PIC layer to the MEMS structure.

[0031] In various examples, such as a 24'h example, there is provided a method in accordance with any of the above, such as that of the 231d example, wherein the at least one coupling element is configured to electrically couple the at least one first portion to the MEMS structure; or wherein the method further comprises providing, in the structure, at least one coupler configured to electrically couple the PIC layer to the MEMS structure.

[0032] In various examples, such as a 251h example, there is provided a method in accordance with any of the above, such as that of the 23'd or 24'h example, wherein the at least one coupling element comprises polysilicon, doped polysilicon, crystalline silicon, doped crystalline silicon, an electrically conducting material or a semiconducting material.

[0033] In various examples, such as a 26'h example, there is provided a method in accordance with any of the above, such as that of any of the 23' to 25'h examples, wherein providing the at least one coupling element comprises: defining, for each of the at least one coupling element, a via through a part of one of the at least one first portions to a part of the MEMS structure, and forming each of the at least one coupling elements in a respective one of the at least one vias; and wherein the MEMS structure is mechanically coupled with the at least one first portion to be non-contiguous with the at least one first portion.

[0034] In various examples, such as a 27th example, there is provided a method in accordance with any of the above, such as that of the 26'h example, further comprising providing a cavity under the at least one first portion on a side of the at least one first portion opposite to a side of the at least one first portion on which the MEMS structure is located.

[0035] In various examples, such as a 28th example, there is provided a method in accordance with any of the above, such as that of any of the 23' to 2511' examples, wherein the at least one coupling element is provided by a second part of the sacrificial layer between the MEMS structure and the at least one first portion; and wherein the MEMS structure is mechanically coupled with the at least one first portion to be non-contiguous with the at least one first portion.

[0036] In various examples, such as a 29th example, there is provided a method in accordance with any of the above, such as that of the 28'h example, further comprising providing a cavity under the MEMS structure on a side of the MEMS structure opposite to a side of the MEMS structure on which the at least one first portion is located.

[0037] In various examples, such as a 30th example, there is provided a method in accordance with any of the above, such as that of any of the 26th to 29'h examples, further comprising defining the MEMS structure by opening the at least one second gap in the MEMS structural layer around the MEMS structure, to separate the MEMS structure from the remaining part of the MEMS structural layer.

[0038] In various examples, such as a 31st example, there is provided a method in accordance with any of the above, such as that of any of the 26'h to 30'h examples, further comprising: after forming the at least one first gap and the one or more optical structures, providing the sacrificial layer over the PIC layer.

[0039] In various examples, such as a 32' example, there is provided a method in accordance with any of the above, such as that of the 31st example, further comprising: after providing the sacrificial layer, bonding the MEMS structural layer to a side of the sacrificial layer opposite to a side of the sacrificial layer on which the PIC layer is located.

[0040] In various examples, such as a 33rd example, there is provided a method in accordance with any of the above, such as that of the 32" example, further comprising: after bonding the MEMS structural layer and providing the MEMS structure, removing the first part of the sacrificial layer from between the MEMS structure and the at least one first portion of the PIC layer.

[0041] In various examples, such as a 34th example, there is provided a method in accordance with any of the above, such as that of any of the 21st to 33' examples, wherein: the PIC layer is formed of silicon; the sacrificial layer is formed of an oxide; and the MEMS structural layer is formed of silicon.

[0042] In various examples, such as a 35'h example, there is provided a method in accordance with any of the above, such as that of any of the 21st to 25th examples, wherein providing the MEMS structure and/or providing the at least one coupling element comprises: depositing material on the at least one first portion to provide the MEMS structure contiguous with, and mechanically coupled to, the at least one first portion.

[0043] In various examples, such as a 36'h example, there is provided a method in accordance with any of the above, such as that of the 35'h example, wherein providing the MEMS structure and/or providing the at least one coupling element comprises: growing a first mass of first material on the at least one first portion and a second mass of second material on the sacrificial layer through epitaxial deposition on the at least one first portion and on at least part of the sacrificial layer; wherein the first mass and the second mass correspond to the MEMS structural layer and the first layer comprises the MEMS structure; and wherein the at least one coupling element corresponds to a bonding region between the at least one first portion and the first mass.

[0044] In various examples, such as a 37th example, there is provided a method in accordance with any of the above, such as that of the 36'h example, wherein: the PIC layer is formed of silicon; the sacrificial layer is formed of an oxide; the first material is crystalline silicon formed by silicon epitaxial deposition onto the PIC layer; and the second material is polysilicon formed by silicon epitaxial deposition onto the sacrificial layer.

[0045] In various examples, such as a 38th example, there is provided a method in accordance with any of the above, such as that of the 36th or 37th example, wherein the at least one second gap is formed in the second mass around the first mass, the at least one second gap connecting with the at least one first gap.

[0046] In various examples, such as a 39'h example, there is provided a method in accordance with any of the above, such as that of any of the 35th to 38th examples, further comprising: before providing the MEMS structure, removing the first part of the sacrificial layer from adjacent to the at least one first portion of the PIC layer.

[0047] In various examples, such as a 40th example, there is provided a method in accordance with any of the above, such as that of the 30th or 38th example, wherein each of the at least one first gap is a gap of between 100nm to 500nm; and/or wherein each of the at least one second gap around the MEMS structure is larger than each of the at least one first gap.

[0048] In various examples, such as a 41st example, there is provided a method in accordance with any of the above, such as that of any of the 21st to 40th examples, further comprising: forming, in the PIC layer, one or more input waveguides each configured to provide input light to one of the one or more optical structures; and forming, in the PIC layer, one or more output waveguides each configured to receive output light from one of the one or more optical structures.

[0049] In various examples, such as a 42nd example, there is provided an apparatus comprising a structure in accordance with any of the above, such as that of any of the 1s1 to 20th examples, wherein light is coupled into and out of each of the one or more optical structures; one or more detectors configured to detect light received from one or more optical structures; and one or more processor configured to: receive an output of the one or more detectors, and determine the change in the spacing between the at least one first portion and an optical structure of the one or more optical structures by detecting the change in the optical field characteristic of that optical structure.

[0050] In various examples, such as a 43'd example, there is provided an apparatus in accordance with any of the above, such as that of the 42nd example, wherein the apparatus is, or is included in, an inertial sensor, a microphone, a timing oscillator, a pressure sensor, an ultrasound transceiver, an ultrasound receiver, a micro-mirror or any similar micro-structure having change in a spacing as a result of an applied force or perturbation.

[0051] In various examples, such as a 44'h example, there is provided a wafer comprising a plurality of structures according to one of the 1' to 201h examples.

[0052] Other aspects, advantages, and salient features of the invention will become apparent to those skilled in the art from the following detailed description taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Embodiments, examples and aspects of the disclosure are further described hereinafter with reference to the accompanying drawings, in which: Figures 1A to 1D schematically illustrate a first method for providing a structure according to various examples of the present disclosure.

Figures 2A to 2C schematically illustrate a first method for providing a layered structure according to various examples of the present disclosure.

Figures 3A to 3D schematically illustrate a second method for providing a layered structure according to various examples of the present disclosure.

Figures 4A to 4F schematically illustrate a second method for providing a structure according to various examples of the present disclosure.

Figures 5A to 5H schematically illustrate a third method for providing a structure according to various examples of the present disclosure.

Figures 6A to 6F schematically illustrate a fourth method for providing a structure according to various examples of the present disclosure.

Figure 7 schematically illustrates a layered structure according to various examples of the present disclosure.

DETAILED DESCRIPTION

[0054] Throughout the description and claims of this specification, the words "comprise" and "contain" and variations of them mean "including but not limited to", and they are not intended to (and do not) exclude other additives, components, integers or steps. Throughout the description and claims of this specification, the singular encompasses the plural unless the context otherwise requires. In particular, where the indefinite article is used, the specification is to be understood as contemplating plurality as well as singularity, unless the context requires otherwise.

[0055] The phrases or expressions "at least one of", "one or more of', and "and/or", when used with a list of items, means that different combinations of one or more of the listed items may be used, and only one item in the list may be needed. For example, "at least one of: A, B, and C" (and "one or more of A, B and C", and "A, B and/or C") includes any of the following combinations: A, B, C, A and B, A and C, B and C, and A and B and C. [0056] The present disclosure provides a number of methods or processes for manufacturing a structure comprising MEMS feature(s) and photonic integrated circuit (PIC) feature(s), such as a chip or a circuit (e.g., without limitation, an integrated circuit (IC)) comprising a mechanical layer and a photonic chip layer (which may itself comprise one or more layers that define active photonic structure(s), for example: laser(s), detector(s), heater(s) etc.). Also provided are a structure comprising MEMS feature(s) and PIC feature(s), such as a chip or circuit, comprising a MEMS layer and a photonic chip layer. In certain examples, such a structure may be produced by one of the processes disclosed herein.

[0057] In the following, references to a "first step", a "second step", a "third step" (or similar, e.g. "operation" or "sub-process" may be used in place of "step") are not intended to indicate a chronological order for performing the steps, but rather the terms "first', "second" and "third" are used to distinguish the various steps.

[0058] Figures 1A, 1 B, 1C and 10 schematically illustrate a first method for providing a structure (at times referred to non-limitingly as a chip or circuit in the given example) comprising a PIC layer and a MEMS layer. This may be regarded as a die-to-die flip chip bond process.

[0059] Figure 1A illustrates, via a cross section, a MEMS die 100 comprising a first layer 101 (e.g. a first silicon layer), a second layer 103 (e.g., a buried oxide (BOX) layer, such as a silicon dioxide layer) and a third layer 105 (e.g. a second silicon layer). The MEMS die 100 also includes metallic (e.g., gold, indium, aluminium, germanium or alloy (e.g., tin)) conductive elements 107. In various examples, elements 107 may additionally or alternatively be provided for bonding, or facilitating bonding, between the MEMS die 100 and the PIC die 120 shown in Fig. 1B. The portions of MEMS die 100 on which the elements 107 are disposed may be regarded as parts of a bonding frame.

[0060] The third layer 105 includes MEMS structure 109, which in one example may be a test-mass (or proof mass). The third layer 105, or the MEMS structure 109, may also be regarded as a MEMS device layer. MEMS die 100 may have been prepared using conventional methods. The first layer 101 may be regarded as a MEMS handle layer 101. As can be seen, the second layer 103 is not present between the MEMS structure 109 and the first layer 101. In some examples, the MEMS structure 109 is attached or coupled to the third layer 105 (e.g., a remaining portion of the third layer 105, other than the MEMS structure 109) via one or more springs, where the one or more springs are coupled or attached to one or more anchors attached to the third layer 105. The spring(s) may allow for movement of the MEMS structure 109, e.g. in response to an external force acting on MEMS die 100, where the MEMS structure 109 may subsequently be returned to a resting position by the spring(s), e.g. once the external force is no longer acting on the MEMS die 100.

[0061] Figure 1B illustrates, via a cross section, a PIC die 120 comprising a first layer 121 (e.g. a first silicon layer), a second layer 123 (e.g. a first silicon dioxide layer), a third layer 125 (e.g. a second silicon layer) and a fourth layer 127 (e.g. a second silicon dioxide layer). The PIC die 120 also includes metal (e.g. gold, indium, aluminium, germanium or alloy (e.g., tin)) conductive elements 129. In various examples, elements 129 may additionally or alternatively be provided for bonding, or facilitating bonding, between the MEMS die 100 and the PIC die 120.

[0062] Included within the third layer 125 is a PIC structure 131 or optical structure 131.

the third layer 125, or the optical structure 131 itself, may also be regarded as a PIC device layer. For illustrative purposes, the first layer 121 may be regarded as a PIC handle layer 121. Also shown in Fig. 1B are hard stops 133, which may optionally be formed on PIC die 120. In some examples, hard stops 133 may include an oxide layer, silicon or polysilicon. One or more active layers (e.g., including an on-chip photodetector or a laser) may also be included in or on PIC die 120, such as by being formed on the third layer 125.

[0063] Figure 1C illustrates, via a cross section, a structure 140, e.g. chip 140, resulting from bonding MEMS die 100 and PIC die 120. For example, a MEMS wafer comprising one or more MEMS die 100 may be bonded to a PIC wafer comprising a corresponding one or more PIC die 120, resulting in a wafer comprising a corresponding number of chip(s) 140. Reference numerals shown in Figs. 1A and 1B are omitted from Fig. 10 for clarity of viewing; however, the same components represented in Figs. 1A and 1B are present in Fig. 1C so may be referred to by the corresponding reference numerals.

[0064] In Fig. 10, it can be seen that the elements 107 of MEMS die 100 are in contact with elements 129 of PIC die 120. For example, the respective elements are permanently bonded or glued together (e.g., using metal joining (e.g., eutectic or thermocompression bonding) or an electrically conductive epoxy), thereby attaching the MEMS die 100 to the separate PIC die 120. In the drawing, the bonding is reflected by the change in shape of elements 107, 129, e.g. demonstrating that bonding may result in compression and/or bulging of these elements 107, 129. If hard stops 133 are included, the first layer 101 of the MEMS die 100 may be in contact with hard stops 133 when the elements 107 are bonded to elements 129.

[0065] Based on the attachment, the MEMS structure 109 is suspended close to (e.g., suspended adjacent to but non-contiguous with) the optical structure 131. For example, the MEMS structure 109 may be positioned at a distance d from the optical structure 131, where d < 1pm (e.g., d = 0.5pm). The edge of the MEMS structure 109 facing the optical structure 131 may be aligned with the facing edge of the optical structure 131.

[0066] Additionally, the MEMS structure 109 is suspended over the PIC handle layer 121 by a distance z, which may be based on one or more hard stops 133 included in/on the PIC die 120 (and/or in/on the MEMS die 100). That is, the hard stop(s) 133 may prevent, or at least restrict to some extent, further movement of the first layer 101 of the MEMS die 100 towards the first layer 121 of the PIC die in the y-direction (e.g., the -y' direction as shown in Figure 1C), when the first layer 101 of the MEMS die 100 is in contact with the hard stop(s) 133. To give a non-limiting example of dimensions, z = 1.3pm.

[0067] Locating the MEMS structure 109 close to (i.e., within a specified distance of) the optical structure 131 may be key, if not required, for providing certain functionality in/with chip 140.

[0068] For example, the optical structure 131 may be an optical microresonator having or exhibiting an optical field. For example, when light propagates along the microresonator (i.e., through the optical structure 131), an optical field of the microresonator may correspond to, or include, the evanescent field outside the microresonator, extending from a boundary of the microresonator (e.g., a silicon-air or silicon-vacuum boundary). It will be appreciated that the evanescent field (i.e., optical field) extends in different directions, e.g., horizontally (e.g., in-plane with the microresonator, towards the MEMS structure 109; along the x-direction shown in Fig. 1C), vertically (e.g., towards the second layer 123 and into the air surface/layer; along the y-direction shown in Fig. 1C), diagonally etc. [0069] The presence of the MEMS structure 109 (which may be a test, or proof mass, as mentioned earlier) in the optical field will alter a property of the microresonator (e.g., at least one characteristic of the optical field of the microresonator). For example, due to the MEMS structure 109 interacting with the evanescent field, the effective refractive index of the microresonator will change, causing a change in an optical resonance of a mode (e.g., whispering gallery mode) of the microresonator. For example, said change in the optical resonance may be a shift in resonance wavelength and/or a broadening or deepening of the curve of the optical resonance. It will therefore be appreciated that the distance d between the MEMS structure 109 and the microresonator will influence the change in the optical resonance (effective refractive index) arising due to the MEMS structure 109. In another example, the microresonator may be subject to increased loss due to scattering or absorption effects arising from the presence of the MEMS structure 109.

[0070] The MEMS structure 109 is suspended from the MEMS layer 105, for example via a system of spring(s) and anchor(s) as described above, such that it may be displaced or deflected (e.g., moved from an initial or equilibrium position). For example, as the chip 140 is moved or experiences force(s) (e.g., an inertial force), the MEMS structure 109 may be displaced accordingly. For example, a movement of the chip 140 to the right (i.e., a rightwards or '+x' direction in Fig. 1C) will cause displacement of the MEMS structure 109 to the left (i.e., a leftwards or '-x' direction in Fig. 1C) due to the unbalanced force initiating the movement of the chip 140 and the suspension of the MEMS structure 109. If the movement of the chip 140 ceases, the MEMS structure 109 will return to its initial position (assuming the orientation of chip 140 is the same as it was prior to the movement -e.g., no rotation has occurred).

[0071] Figure 10 illustrates an example of a system of springs and anchors for attaching (i.e. suspending, moveably attaching, coupling etc.) the MEMS structure 109 to another part of MEMS die 100 (such as the third layer 105).

[0072] In the plan view shown in the right-side image (which may reflect a plan view of part of chip 140 or MEMS die 100 where features of PIC die 120 are omitted, e.g. viewing in a '+y' direction relative to Fig. 1C), it is illustrated how a portion of the second layer 103 (e.g. buried oxide layer / silicon dioxide layer) has been removed from around (e.g., considering the arrangement shown in Fig. 1C, above or in a -Fy' direction from) MEMS structure 109 (or, to put another way, removed from around, e.g. in a +y' direction from, a portion of the third layer 105 including where MEMS structure 109 is formed). Springs 111a, 111b attach the MEMS structure 109 to anchors 113 (which may be formed of silicon), and the anchors 113a, 113b are attached or connected to the remaining portion of the third layer 105. In some examples, anchors 113a, 113b and/or springs 111a, 111b are formed from the third layer 105.

[0073] In an illustrative example, etching, such as hydrogen fluoride (HF) vapour etching, may be used to release the MEMS structure 109 from the second layer 103, which is a BOX layer. The opening around the MEMS structure 109 may allow the vapour HF to attack or process the BOX layer that is exposed around the MEMS structure 109.

However, where there is no opening, such as where the majority of anchors 113a, 113b are found, the BOX remains (i.e., is not removed by the vapour HF) such that the majority of the anchors 113a, 113b are still attached to the BOX layer.

[0074] Three cross-sections are also illustrated in Fig. 1D: A -A', B -B', C -C'. In the cross-section corresponding to dashed line A -A', an anchor 113a (i.e. a part thereof) is seen attached to the second layer 103 and third layer 105. In the cross-section corresponding to line B -B', a spring 111a (i.e. parts thereof) is shown suspended, i.e. not directly attached to the second layer 103 or the third layer 105 but attached between anchor 113a and MEMS structure 109. In the cross-section corresponding to line C -C', the suspension of MEMS structure 109 is shown, with MEMS structure 109 not directly attached to the second layer 103 or the third layer 105 but attached to anchor 113a via spring 111a (and also attached to anchor 113b via spring 111b).

[0075] It will be appreciated that, although a spring and anchor system has been described to give an example of how a MEMS structure may be suspended from a MEMS die (or within a PIC-MEMS structure), other means may be used to accomplish this so the given example should not be viewed as limiting. In the other examples found herein, a spring and anchor system such as illustrated in Fig. 1D may be used to suspend a MEMS structure.

[0076] It will be understood that a change in position of the MEMS structure 109 with respect to the microresonator, e.g. resulting from the displacement of the MEMS structure 109, will change the effect the presence of the MEMS structure 109 (or the surface thereof, which may be opaque) has on the optical field of the microresonator. For instance, the shift in the resonance wavelength may change (e.g., increase or decrease). The change in the optical field characteristic (e.g., the change in the optical resonance linewidth or shape, or the changed value of the optical resonance itself) may be measured so as to determine (or calculate, or infer etc.) the displacement of the MEMS structure 109.

[0077] PIC die 120 may comprise an input waveguide arranged to provide (e.g. couple) light to the optical structure 131. For example, the input waveguide may be located in the third layer 125 such that light (e.g., input to the input waveguide from a laser) propagating in the input waveguide is coupled into the microresonator. It will be appreciated that other methods of inputting light to the optical structure 131 exist, the above is merely one

example.

[0078] PIC die 120 may also comprise an output waveguide arranged to receive, or obtain, light from the optical structure 131. The output waveguide may form part of the same element/component (e.g. waveguide) in the PIC die 120 (e.g., in the third layer 125) as the input waveguide or may be provided separately in the PIC die 120. For example, the output waveguide may be located in the third layer 125 proximate to the microresonator such that light propagating in the microresonator is coupled into the output waveguide. In some cases, an optical coupler included in the PIC die 120 may comprise the input waveguide and the output waveguide, e.g., in an all-pass arrangement where a single waveguide provides the input and through port, or in an add-drop arrangement where two separate waveguides are used to provide four ports (add to drop, input to through).

[0079] The output waveguide may provide light to a detector (e.g., a measuring means, or any device that converts an optical signal into an electrical signal, with an example of a detector being a photodetector). The detector may be included in the chip 140 and be arranged to receive light from the output waveguide, or may be provided separately and arranged in relation to chip 140 to receive light from the output waveguide. The detector, either alone or in combination with another component (which may also be included in or separate to chip 140) may detect the change in characteristic of the optical field. Based on the detected change, e.g., the shift in resonance wavelength or broadening/narrowing of the resonance linewidth, a displacement of the MEMS structure 109 may be determined.

[0080] It will be appreciated that detection or calculation of the displacement of the MEMS structure 109 may have a number of practical uses. For example, knowledge of the displacement and/or, by extension, the rate at which the displacement occurs (i.e., the speed of the displacement, as can be determined through measuring multiple changes in the optical field characteristic), may be used to determine an acceleration, rotation or velocity of the chip 140 or an apparatus including chip 140. For example, if chip 140 is, or is included in, an inertial sensor (which may itself be included in a mobile phone or other device), the inertial sensor may determine an applied inertial force. Accordingly, chip 140 may facilitate the provision of accelerometers, gyroscopes and other inertial sensors.

[0081] Other uses exist for a chip or circuit such as structure/chip 140. For example, if MEMS structure 109 is driven at its mechanical resonance, such as by an electrostatic comb drive actuator also present in third layer 105 (or in a suitable location), then structure 140 may function as an oscillator element or clock. In another example, if MEMS structure 109 is formed as a plate or membrane structure upon which sound waves may impinge, then structure 140 may be used as a pressure sensor, microphone, or ultrasonic transceiver. In another example, if MEMS structure 109 is formed as a plate or membrane structure upon which infrared light may impinge, then structure 140 may be used as a calorimeter or temperature sensor.

[0082] The die-to-die flip chip bond process disclosed in combination with Figs. 1A to 1D has advantages in that separate PIC-specific and MEMS-specific foundries or manufacturing facilities may produce the PIC die 120 and the MEMS die 100, respectively.

Thus, each facility makes the type of device for which its tooling is optimized, so wafer fabrication runs may cost less and enjoy higher yields. Additionally, this process can create high performing chips/circuits if the best performing die are selected from each of the PIC and MEMS wafers and then bonded together.

[0083] However, there are also disadvantages associated with this method. For one, while the method may be suitable for die-to-die bonding, it is not suitable for wafer-to-wafer bonding because it is preferable, if not necessary, for the optical structure 131 to be located close to the edge of the MEMS structure 109, e.g., less than 1 micron away (i.e., d < 1pm). This is because the evanescent field does not extend far from the optical structure 131 and so it is only within a short distance from the optical structure 131 that the MEMS structure 109 may have an appreciable, or measurable, effect on the optical field characteristic(s) of the optical structure 131. For example, if a test mass is located too far from a microresonator, the test mass, or a displacement thereof, may not have a suitably measurable effect on the optical resonance of the microresonator, or may not consistently have a suitably measurable effect on the optical resonance, such that accurate detection of a displacement is not consistently viable. With the die-to-die method, the MEMS structure(s) cannot be etched as accurately or precisely as the PIC structures, meaning that a square on the MEMS wafer will not be aligned to a corresponding square on the PIC wafer uniformly across the wafer formed by bonding the MEMS wafer to the PIC wafer, resulting in misalignment of components between individual MEMS die and PIC die. The die-to-die method may also have scalability issues, considering that throughput may be too slow and the process too expensive for high volume manufacturing.

[0084] Another disadvantage is that wafer bowing may occur after processing both a PIC wafer and a MEMS wafer such that the perimeter of the wafer is curved upwards, forming a bowl shape. If using wafer-to-wafer bonding, misalignment may result across the edges of the individual dies and/or across the perimeters of the wafers, when compared to the centre. This could lead to failure to reach the critical gap (i.e., this being the space between a MEMS structure (e.g., MEMS structure 109) and a corresponding optical structure (e.g., optical structure 131)) via the bonding process or even potential damage to features if misalignment causes mechanical interference. After bonding, it may be unlikely that a chip will provide high yield, and there will be variation between different chips. As a result, it may be very difficult, if not unfeasible, to perform differential sensing using a chip manufactured in this manner.

[0085] Furthermore, the robustness of the bonding scheme may possess weaknesses, as it may rely on a bonding layer (e.g., metal, epoxy, polymer) which has very different properties to a material used to define/form the PIC structure(s) (e.g., optical structure 131) and the MEMS structure(s) (e.g., MEMS structure 109). Mismatch in coefficient of thermal expansion, for example, can stress the bonding layer and compromise the bond integrity over time. Variation in the bonding layer and resulting bonding interface could vary and cause variation in the vertical position ("z" on Figure 1C), which could cause variation in

the evanescent field.

[0086] Accordingly, various examples of the present disclosure provide alternative methods for manufacturing a structure (e.g., including a chip or circuit) comprising PIC feature(s) and MEMS feature(s), with an intention of some examples being to avoid one or more of the aforementioned disadvantages of the die-to-die flip chip bond method and/or provide advantages of their own.

[0087] According to various examples of the present disclosure, higher yield and more robust methods are provided, in which photonic and mechanical structures are created from a single wafer. In such a structure, alignment between MEMS features and PIC features is defined by design (e.g., mask, etching etc.) rather than by integrating or bonding two separate wafers.

[0088] Figures 2A to 2C schematically illustrate a method for providing a structure comprising a PIC layer and a MEMS layer, where the structure is formed from a single wafer (e.g., comprising the PIC layer and the MEMS layer).

[0089] Figures 3A to 3D schematically illustrate an alternative method for providing a structure comprising a PIC layer and a MEMS layer, where the structure is formed by bonding two separate wafers (i.e., sub-structures, e.g. corresponding to a MEMS wafer comprising the MEMS layer and a PIC wafer comprising the PIC layer).

[0090] As will be seen later, either structure (i.e., structure 240 arising from Figs. 2A to 2C or structure 360 arising from Figs. 3A to 3D) may be used in a second method for providing a structure comprising a PIC layer and a MEMS layer, as schematically illustrated into Figs. 4A to 4F.

[0091] Figure 2A illustrates, via a cross-section, a structure 200 comprising a first layer 201, a second layer 203, a third layer 205, a fourth layer 207 and a fifth layer 209. The first layer 201 is a PIC layer 201, and may be referred to as such from hereon. The third layer 205 is a MEMS layer 205, and may be referred to as such from hereon.

[0092] The PIC layer 201 may include, or be formed of, a photonic capable material. In some examples, the PIC layer 201 may include, or be formed of, a stack of photonic materials, for example the stack including indium phosphate or germanium etc., where one or more material included in the stack may be used to define a laser(s) and/or a photodetector(s) (i.e. an active layer(s)). The MEMS layer 205 may include, or be formed of, a crystalline or polycrystalline material such as silicon or glass. If silicon, dopants may be added to achieve semiconducting or conducting capabilities. In various examples, MEMS layer 205 and PIC layer 201 may both be layers of silicon. Alternatively, each of MEMS layer 205 and PIC layer 201 (or each layer/material in a stack of photonic materials included in the PIC layer 201) may be formed of the same or a different one of: silicon, silicon nitride, polysilicon, silicon germanium, germanium, indium phosphide, gallium nitride, silicon carbide.

[0093] The second layer 203 and the fourth layer 207 may be insulator layers and/or sacrificial layers. In various examples, one or both of the second layer 203 and the fourth layer 207 may be a layer of silicon oxide (i.e., an oxide layer or buried oxide).

[0094] The fifth layer 209 may be a handle layer 209 (e.g., a handle wafer). In an example, the handle layer 209 is formed of crystalline silicon.

[0095] In an exemplary case where the PIC layer 201 and the MEMS layer 205 are silicon layers and the second layer 203 and the fourth layer 207 are buried oxide layers, structure 200 may be provided by a double silicon-on-insulator (S01) wafer (DSOI wafer).

[0096] In a first step (a PIC processing step), structure 220 shown in Fig. 2B is obtained by processing the PIC layer 201 to define a plurality of features. In various, non-limiting examples, this processing may be performed using electron-beam lithography or deep ultraviolet lithography, or next-generation lithography methods such as X-ray lithography, focused ion beam lithography, quantum lithography, extreme ultraviolet lithography and nanoimprint lithography, followed by etching. In the present disclosure, where there is description of defining features in a PIC layer, it should be assumed that various examples consider said defining/processing to be performed using one of the aforementioned methods (although not to the exclusion of other methods).

[0097] In particular, as shown in Fig. 2B, PIC layer 201 may be processed to form: one or more optical structure 221 (where one is shown in the cross-sectional example of Fig. 2B but more may be formed in structure 220), at least one gap 223 (e.g., first gap(s) 223; these may alternatively be termed first space(s), first opening(s), first trench(es) etc.), at least one portion 225 (e.g., first portion(s) 225 -where two are shown in the cross-sectional example of Fig. 2B but more or fewer may be formed in the structure 220; these may alternatively be termed first region(s), first part(s), first section(s) etc.), and other gap(s) (e.g., the gap between the two first portions 225). Other features which may (optionally) be formed in the PIC layer 201 include grating(s) and/or waveguides(s) (e.g., an input waveguide and/or an output waveguide). According to various examples, these features may be formed by etching the PIC layer 201.

[0098] The first gap(s) 223 may have a size similar to that of distance d as defined in relation to Fig. 1C. For example, the first gap(s) may have a width (i.e., wall to wall) of < 1 pm, with the gap being < 500nm in certain examples. The width of the first gap(s) may be dependent on the limits of the lithography performed prior to the etching of the first gap(s).

An example accuracy of this process is ±50nm, although it will be appreciated that this may change depending on the lithographic (or other) method used.

[0099] The first gap(s) 223 may define, at least partly, the first portion(s) 225. For example, in Fig. 2B the first portion(s) 225 are each defined by a first gap 223 and the gap etched between the two illustrated first portions 225. In an example, in addition to the other gap defined between two first portions 225 as shown in Fig. 2B, a single first gap 223 may be defined in a closed loop around the two first portions 225; here, the two first gaps 223 indicated/numbered in Fig. 2B are actually cross-sections of the same first gap 223. In other examples, a plurality of separate first gaps 223 are provided for defining the first portion(s) 225.

[00100] The optical structure(s) 221 may have a corresponding optical field, similar to as described for optical structure 131 in relation to Figs. 1A to 1C. For instance, the optical structure 211 may be a microresonator (e.g., a whispering gallery mode resonator), and the optical field may correspond to the evanescent field deriving from light propagating in the microresonator. Although not shown, the PIC layer 201 may further include an input waveguide arranged to provide light to the optical structure 221 (e.g., via coupling) and an output waveguide arranged to receive light from the optical structure 221 (e.g., via coupling). Alternatively, such waveguides may be provided elsewhere on the structure 220 or on a wafer comprising the structure 220.

[00101] A second step, as illustrated in Figure 2C, is to oxidize to protect the features formed in the PIC layer 201. As a result, structure 240 comprises an oxidized layer 227, or sacrificial layer 227 hereafter, which at least partly surrounds the PIC layer 201 (in particular, covering the optical structure(s) 221, the first gaps 223 and the at least one first portion 225 so as to protect these features). As well as, or as an alternative to, oxidation, in some examples, silicon oxide materials may be deposited and/or planarization is also performed to smooth the surface of the sacrificial layer 227. In various examples, a second processing step may include deposition of silicon oxide materials(s), such as plasma-enhanced chemical vapor deposition (PECVD) oxide or Tetraethyl orthosilicate (TEOS) over the PIC layer 201.

[00102] In various examples, one or more active layers (not shown in the figures) are formed in structure 240, such as prior to the oxidization step or deposition step. For example, an active layer (e.g., of germanium or indium phosphide) may be formed on at least part of PIC layer 201, for use in defining one or more lasers and/or one or more photodetectors in a resulting structure/chip/wafer, and oxidization results in the sacrificial layer 227 at least partly surrounding the active layer. A further discussion of these features, examples etc. is found below in relation to Figure 7.

[00103] In certain examples, it may be considered that sacrificial layer 227 and the second layer 203 essentially form a single layer or portion of structure 240 (e.g., sacrificial layer 227 comprises the second layer 203, as well as the protective layer over and around the features in the PIC layer 201). In the following, references to the sacrificial layer 227 may also be considered to refer to at least part of the second layer 203 and/or to at least part of the material resulting from the oxidation step (or other deposition step).

[00104] Turning now to Figure 3A, this illustrates, via a cross-section, a structure 300 comprising a first layer 301, a second layer 303 and a sixth layer 311.

[00105] The first layer 301 is a PIC layer 301, and may be referred to as such from hereon. As for PIC layer 201, the PIC layer 301 of structure 300 may be formed of, or include, a photonic capable material. In some examples, the PIC layer 301 may include, or be formed of, a stack of photonic materials, for example the stack including indium phosphate or germanium etc., where one or more material included in the stack may be used to define a laser(s) and/or a photodetector(s) (i.e., one or more active layers). For example, PIC layer 301 may be formed of (or each layer/material in a stack of photonic materials included in the PIC layer 301 may be formed of the same or a different one of) silicon, silicon nitride, polysilicon, silicon germanium, germanium, indium phosphide, gallium nitride, or silicon carbide.

[00106] The second layer 303 may be an insulator layer or sacrificial layer. In various examples, the second layer 303 may be formed of silicon oxide (i.e., may be an oxide layer or buried oxide). The sixth layer 311 may be a handle layer 311 (e.g., a handle wafer), which may, in various examples, be formed of crystalline silicon.

[00107] In an exemplary case where the PIC layer 301 is a silicon layer and the second layer 303 is an oxide layer, structure 300 may be provided by a silicon-on-insulator wafer (S01 wafer), particularly a PIC quality SOI wafer.

[00108] In a first step, (a PIC processing step), structure 320 shown in Fig. 3B is obtained by processing the PIC layer 301 to define a plurality of features. In various, non-limiting examples, this processing may be performed using electron-beam lithography or deep ultraviolet lithography, or next-generation lithography methods such as X-ray lithography, focused ion beam lithography, quantum lithography, extreme ultraviolet lithography and nanoimprint lithography, followed by etching.

[00109] As shown in Fig. 3B, PIC layer 301 may be processed to form: one or more optical structures 321 (where one is shown in the cross-sectional example of Fig. 3B but more may be formed in the structure 320), at least one gap 323 (e.g., first gap(s) 323; these may alternatively be termed first space(s), first opening(s), first trench(es) etc.), at least one portion 325 (e.g., first portion(s) 325 -where two are shown in the cross-sectional example of Fig. 3B but more or fewer may be formed in the structure 320; these may alternatively be termed first region(s), first part(s), first section(s) etc.), and other gap(s) (e.g., the gap between the two first portions 325). Other features which may (optionally) be formed in the PIC layer 301 include grating(s) and/or waveguides(s) (e.g., an input waveguide and/or an output waveguide). According to various examples, these features may be formed by etching the PIC layer 301.

[00110] The first gap(s) 323 may be defined similarly to the first gap(s) 223 of structure 220 described in relation to Fig. 2B. The optical structure(s) 321 may be defined similarly to optical structure(s) 221 described in relation to Fig. 2B. Corresponding descriptions are therefore omitted here, for brevity. Additionally, as mentioned in combination with structure 220 of Fig. 2B, although not shown in Fig. 3B, the PIC layer 301 may further include an input waveguide arranged to provide light to the optical structure 321 (e.g., via coupling) and an output waveguide arranged to receive light from the optical structure 321 (e.g., via coupling). Alternatively, such waveguides may be provided elsewhere on the structure.

Other photonic features may also be formed in PIC layer 301, if desired.

[00111] The first gap(s) 323 may define, at least partly, the first portion(s) 325. For example, in Fig. 3B the first portion(s) 325 are each defined by a first gap 323 and the gap etched between the two illustrated first portions 325. In an example, in addition to the other gap defined between two first portions 325 as shown in Fig. 3B, a single first gap 323 is defined in a closed loop around the two first portions 325; here, the two first gaps 323 numbered in Fig. 3B are actually cross-sections of the same first gap 323. In other examples, a plurality of separate first gaps 323 are provided for defining the first portion(s) 325.

[00112] A second step, as illustrated in Figure 3C, is to oxidize to protect the features formed in the PIC layer 301. As a result, structure 340 comprises an oxidized layer 327, or sacrificial layer 327 hereafter, which at least partly surrounds the PIC layer 301 (in particular, covering the optical structure(s) 321, the first gap(s) 323 and the at least one first portion 325 so as to protect these features). As well as, or as an alternative to, oxidation, in some examples, silicon oxide materials may be deposited and/or planarization is also performed to smooth the surface of the sacrificial layer 327. In various examples, a further processing step may include deposition of silicon oxide materials(s), such as PECVD oxide or TEOS.

[00113] In certain examples, it may be considered that sacrificial layer 327 and the second layer 303 essentially form a single layer or portion of structure 340 (e.g., sacrificial layer 327 comprises the second layer 303, as well as the protective layer over and around the features of PIC layer 301). In the following, references to the sacrificial layer 327 may also be considered to refer to at least part of the second layer 303 and/or to at least part of the material resulting from the oxidation step (or other deposition step).

[00114] In a third step, as illustrated in Fig. 3D, the structure 340 is bonded to a MEMS structure (or a PIC wafer comprising structure 340 repeated one or more times across it is bonded to a MEMS wafer), resulting in structure 360. This may be achieved by bonding the sacrificial layer 327 to another structure (e.g., a MEMS chip/die or a MEMS wafer) comprising a third layer 305, a fourth layer 307 and a fifth layer 309. A surface of the sacrificial layer 327 (e.g., the surface opposite the surface of the sacrificial layer 327 in contact with the handle layer 311) may be bonded or attached to the third layer 305, for example. Once the sacrificial layer 327 is bonded to the third layer 305, the handle layer 311 may be removed.

[00115] The third layer 305 is a MEMS layer 305, and may be referred to as such from hereon. In various examples, the MEMS layer 305 may be formed of, or include, one or more of silicon, silicon nitride, polysilicon, silicon oxide, silicon germanium, germanium, silicon carbide or gallium nitride.

[00116] The fourth layer 307 may be an insulator layer or sacrificial layer. In various examples, the fourth layer 307 may be formed of silicon oxide (i.e., may be an oxide layer or buried oxide).

[00117] The fifth layer 309 may be a handle layer 309 (e.g., a handle wafer), which may, in various examples, be formed of silicon, crystalline silicon or glass.

[00118] In an exemplary case where the M EMS layer 305 is a silicon layer and the fourth layer 307 is an oxide layer, the other structure (e.g., MEMS wafer) may be provided by a silicon-on-insulator wafer (S01 wafer), particularly a MEMS quality SOI wafer.

[00119] That the locations of the optical features in structure 360 as illustrated in Fig. 3D appears to differ from the locations of the optical features in structure 240 as illustrated in Fig. 2C is incidental and not of any relevance. The locations shown in Fig. 3D are merely to illustrate the attachment of MEMS wafer to structure 240. It will be appreciated that structure 240 is highly similar to structure 360, and may be regarded as the same for the

purposes of this disclosure.

[00120] In various examples, one or more active layers (not shown in the figures) are formed in structure 360, such as prior to an oxidization step and/or an oxide material deposition step. For example, an active layer (e.g., of germanium or indium phosphide) may be formed on at least part of PIC layer 301, for use in defining one or more lasers and/or one or more photodetectors in a resulting structure/chip/wafer, and oxidization results in the sacrificial layer 327 at least partly surrounding the active layer. A further discussion of these features, examples etc. is found below in relation to Figure 7.

[00121] Accordingly, Figs. 2A to 2C describe a method of providing a structure 240 using a DSOI wafer, while Figs. 3A to 3D describe a method of providing a structure 360 using two SOI wafers. Resulting structure 360 may be regarded as a 0501 wafer. It will be appreciated that other methods of providing a structure similar to that of structure 240 or structure 360 are included within the scope of the present disclosure.

[00122] In both cases, it will be appreciated that, in various examples, the cross-sectional figures may show only part of a larger wafer, in which the illustrated structures (or similar) are repeated. For example, structure 240 or structure 360 may be repeated across/throughout a wafer by processing separate portions of the wafer to define optical structures, first gap(s) and first portion(s) (and, e.g., other gap(s)). Note that optical structures may differ between the different portions of the wafer (i.e., the individual structures on the wafer need not be identical). Accordingly, one wafer in accordance with the present disclosure may comprise a plurality of regions where processed structures are disposed, said structures each comprising one or more optical structures, gaps and one or more portion(s).

[00123] Figure 7 schematically illustrates the formation of one or more active layers or one or more active optical structures in a structure 700.

[00124] Structure 700 may correspond to structure 240 or structure 360, such that structure 700 may be obtained through the process for providing structure 240 as shown in Figs. 2A to 2C or the process for providing structure 360 as shown in Figs. 3A to 3D.

[00125] Accordingly, the following correspondence exists: first layer 701 to first layer 201, 301; second layer 703 to second layer 203, 303; third layer 305 to third layer 205, 305; fourth layer 707 to fourth layer 207, 307; fifth layer 709 to fifth layer 209, 309; optical structure 721 to optical structure 221, 321; first gap(s) 723 to first gap(s) 223, 323; first portion(s) 725 to first portion(s) 225, 325; and sacrificial layer 727 (which may include third layer 705) to sacrificial layer 227, 327 (which may include third layer 205, 305, respectively). In other words, each of these features in Figure 7 may have the same characteristics, details etc. as the corresponding feature in Figure 2 or Figure 3. To give an example, first layer 701 may be a PIC layer 701, while third layer 705 may be a MEMS layer.

[00126] In structure 700, active structures 783, 787 have been formed (these may also be termed active layers 783, 787, or metal layers 783, 787). For example, active structure 783 has been formed on optical structure 721, where an example of active structure 783 may be an on-chip photodetector or used in the formation/provision of an on-chip photodetector (e.g. for detecting light, and/or the characteristics thereof, propagating in optical structure 721) and may be formed of germanium. In another example, active structure 787, formed on another part of PIC layer 701, may be a laser or may be used in the formation/provision of a laser, and may be formed of indium phosphide. Active materials, such as germanium and indium phosphide, which are used in the formation of an active structure 783, 787 may be provided in layers on the first layer 701 or a part thereof. For example, in the case of an active structure being a laser, layers of active material may be provided for forming a laser having multi-quantum wells.

[00127] Also shown in Figure 7 is that structure 700 comprises, for each active structure 783, 787, one or more metal components 781a, 781b, 781c, 785b, 785b which are provided for driving a corresponding active structure (e.g., this may include supplying electrical power to a corresponding active structure). For example, metal components 781a, 781b, 781c are provided for driving active structure 783, and metal components 785a, 785b are provided for driving active structure 787. It will be appreciated that, in various examples, each metal component may connect to an electrical contact (not shown in Figure 7), such as N doped region or a P doped region in structure 700. For instance, an N doped region or P-doped region may be formed on portion(s) of PIC layer 701.

[00128] As mentioned above, Figures 4A to 4F schematically illustrate, via cross sections of a part of a wafer, a second method for providing a structure comprising a PIC layer and a MEMS layer, where at times the structure may be non-limitingly referred to as a chip (or circuit) in the given example.

[00129] In Fig. 4A, structure 400 comprises a PIC layer 401 (corresponding to PIC layer 201, PIC layer 301 and/or PIC layer 701), a sacrificial layer 427 (corresponding to sacrificial layer 227, sacrificial layer 327 and/or sacrificial layer 727), a MEMS layer 405 (corresponding to MEMS layer 205, MEMS layer 305 and/or MEMS layer 705), another buried oxide or insulator layer 407 (corresponding to fourth layer 207, fourth layer 307 and/or fourth layer 707) and a handle wafer 409 (corresponding to handle wafer 209, handle wafer 309 and/or handle wafer 709). Furthermore, the structure 400 may comprise (e.g., in the PIC layer 401): optical structure 421 (corresponding to optical structure 221, optical structure 321 and/or optical structure 721), first gap(s) 423 (corresponding to first gap(s) 223, first gap(s) 323 and/or first gap(s) 723; which may also be regarded as evanescent gap(s)), and at least one portion 425 (e.g. first portion(s) 425; corresponding to first portion(s) 225, first portion(s) 325 an/or first portion(s) 725). Although not shown, one or more active optical structures may be included in structure 400 (e.g., such as shown in structure 700).

[00130] The structure 400 shown in Fig. 4A may correspond to structure 240, structure 360 or structure 700 where the optical features are/have been exposed (e.g., part of the PIC layer 201, 301, 701, such as optical structure 221, 321, 721 have been exposed); that is, a part of sacrificial layer 427 may be removed to expose the optical features, making the sacrificial layer absent in the corresponding locations. In an example, removal of the part of the sacrificial layer 427 may be achieved by liquid, vapor or plasma etch methods. Furthermore, another part 431 of sacrificial layer 427 (e.g., a part between the first portion(s) 425) is removed to open, or expose, a portion of MEMS layer 405, e.g., part of the surface of MEMS layer 405.

[00131] In other words, it may be considered that the method described in combination with Figs. 4A to 4F begins with a structure (e.g., layered structure) such as structure 240 of Fig. 2C, structure 360 of Fig. 3D or structure 700 of Fig. 7. Advantageously, contrary to the first method described in combination with Figs. 1A to 1D, the PIC layer and the M EMS layer of the structure are bonded, or attached, prior to the formation of MEMS structures in the MEMS layer.

[00132] Additionally, at least one coupling element 429 has been formed, as shown in structure 400, to mechanically couple the PIC layer 401 to the MEMS layer 405. It will be appreciated that while two coupling elements 429 are shown in the cross sectional example of Fig. 4A, one coupling element or more than two coupling elements may be formed in structure 400 for this purpose.

[00133] Referring to the coupling element(s) 429, each coupling element 429 mechanically couples one of the first portion(s) 425 to the MEMS layer 405, e.g., a portion of the MEMS layer below the respective first portion 425. In an example, a coupling element(s) 429 is formed by opening a via in the PIC layer 401 (i.e., in the first portion(s) 425) down to (and, optionally, into) the MEMS layer 405 (through sacrificial layer 427), and filling the via with a suitable material for the coupling.

[00134] The coupling element(s) 429 may cause attachment between the PIC layer 401 and the MEMS layer 405 by solidly filling the via with a material that adheres well to its walls, such as CVD metal, electroplated metal or LPCVD polycrystalline materials. The coupling element(s) 429 may alternatively be termed: through silicon via(s), nail(s), coupler(s), affixer(s), attacher(s) or bonder(s). The coupling element(s) 429 may prevent, or reduce, misalignment between the MEMS layer 405 (e.g., a later-processed MEMS structure of the MEMS layer 405, as will be described shortly) and the PIC layer 401 (e.g., a feature such as an optical structure 421, defined in the PIC layer 401).

[00135] The coupling element(s) 429 may be formed, for example, from a material with low resistivity, a conducting material, a semiconducting material or polysilicon. For example, forming the coupling element(s) 429 may be achieved through use of a mechanism for conformally depositing (e.g., in an opened via(s)) a film with low resistivity.

[00136] In certain examples of the present disclosure, the coupling element(s) 429 also provide electrical coupling between the PIC layer 401 and the MEMS layer 405. This may provide a number of advantages in the resulting structure. For example, electrical connection between the PIC layer 401 (or a portion thereof, such as a specific optical structure) and the MEMS layer 305 (or a portion thereof, such as a MEMS structure in the MEMS layer 405 as will be introduced shortly in Figure 4E) may prevent unwanted surface charge build-up, which could otherwise damage or negatively impact the functionality of a chip and may keep the first portion(s) 425 and the MEMS layer 405 at the same (or substantially the same) electrical potential (voltage) which may be needed for correct MEMS function.

[00137] In various examples, as an alternative to providing electrical coupling between the MEMS layer 405 and the PIC layer 401 via the coupling element(s) 429, or in addition to the coupling element(s) 429 providing electrical coupling, separate electrical coupling elements or couplers (not shown in the figures) may be provided. For example: the PIC layer 401 may comprise one or more capacitive plate arranged to capacitively couple to one or more capacitive plates included in the MEMS layer 405; or the PIC layer 401 may comprise one or more electrical contacts arranged to contact with one or more electrical contacts included in the MEMS layer 405 (e.g., by way of another via through sacrificial layer 427 or by some other connection means). In another example, one or more parts of the PIC layer 401 may be doped to provide electrical routing to the M EMS layer 405 or a part(s) thereof.

[00138] In an example, the coupling element(s) 429 are formed of polysilicon or doped polysilicon, such as with boron to create a p-type electrical conductor. Here, an opened via may be filled with (doped) polysilicon to provide a mechanical anchor between the first portion(s) 425 of PIC layer 401 and a portion of the MEMS layer 405, and to provide an electrical connection between the PIC layer 401 and the MEMS layer 405. Polysilicon may be an advantageous material to use for the coupling element(s) 429 in the event that PIC layer 401 and/or MEMS layer 405 are silicon layers because polysilicon has similar material properties to silicon, and is therefore a good option for linking two silicon layers (or linking two layers, at least one of which is silicon). Thermal expansion coefficient matching is of particular importance so as to limit mechanical stress that could slightly affect the first gap(s) 423 and even cause buckling of the first portion(s) 425.

[00139] Figure 4B illustrates a cross-section of a secondary structure 420, separate to structure 400 of Fig. 4A. The secondary structure 420 comprises, or is formed in, a bulk wafer 431, such as silicon.

[00140] Referring to Figure 4C, the bulk wafer 431 is processed to etch at least one cavity 435 (although the cross-sectional example of Fig. 4C shows one cavity 435, it will be appreciated that a plurality of cavities could be etched in bulk wafer 431). As will be seen, the at least one cavity 435 may be located in correspondence with a portion of the PIC layer 401 (e.g., the first portion(s) 425) and/or a portion of the MEMS layer 405 (e.g., the part exposed by removal of the part 431 of the sacrificial layer 427), such that a cavity 435 is provided below a corresponding portion of the PIC and/or MEMS layers. The cavity 435 may therefore allow for displacement of a corresponding portion of the MEMS layer 405, such as a portion acting as a test mass or otherwise attached to the first portion(s) 425 of the PIC layer 401, and/or allow for displacement of the first portion(s) 425.

[00141] Once the at least one cavity 435 is formed in bulk wafer 431, oxidation is performed resulting in oxide layer 433. Secondary structure 440 therefore comprises bulk wafer 431 (i.e., the remaining part of bulk wafer 431), oxide layer 433 and cavity 435.

[00142] Referring now to Figure 4D, there is shown a cross-sectional example of a structure 460 resulting from bonding structure 400 with secondary structure 440. In Fig. 4D, it is shown that structure 400 is flipped and placed on secondary structure 440, but it will be appreciated that other orientations are possible.

[00143] In various examples, structure 400 is fusion bonded to secondary structure 440. In other examples, structure 400 is eutectic bonded (e.g., with gold-tin or gold-indium) to secondary structure 440. Additionally, handle layer 409, or at least a part thereof (such as the part above where a structure (see below) will be formed in the MEMS layer 405), is removed, as is other layer 407 (i.e. insulator or other buried oxide layer 407) or at least a part thereof (e.g., these layers/parts may be removed together).

[00144] As can be seen, the attachment aligns cavity 435 with the exposed part of the MEMS layer 405 and/or to align the cavity 435 with the first portion(s) 425 of the PIC layer 401. It will be appreciated that, in a case of the structure 460 being repeated across/throughout a wafer (or a pair of bonded wafers. one in which structure 400 is repeated and one in which structure 440 is repeated), individual cavities 435 may be aligned with corresponding parts of the MEMS layer (e.g., parts corresponding to a MEMS structure, as will be described shortly) and/or corresponding parts of the PIC layer 401 (e.g., first portion(s) 425).

[00145] Additionally, structure 460 may be processed to form one or more elements 441, 443 and 445. In an example, this results in electrical connector (or connection pads) 445, and bond ring elements 441, 443 (or bond frame elements 441, 443, such as may be included in a bond frame). In various examples, bond ring elements 441, 443 correspond to a single bond ring surrounding a portion of the surface of MEMS layer 405. In other words, when viewed from above, structure 460 comprises a bond ring encircling part of the top of structure 460, such as by surrounding the second gap(s) 453. Bond ring elements 441, 443 may thereby illustrate different parts of the cross section of the bond ring, in this example.

[00146] Figure 4E illustrates a subsequent step of processing the MEMS layer 405 to provide, define or form at least one MEMS structure 451, resulting in structure 480. For example, deep reactive ion etching (DRIE) may be used to form the MEMS structure 451. MEMS structure 451 may be a test/proof mass (e.g., for use in inertial sensing as indicated above), a thin plate or diaphragm (e.g. for use in a microphone, pressure sensor, or ultrasonic transceiver) or a resonant structure (e.g. for use in an oscillator or clock).

[00147] As can be seen, one or more second gap(s) 453 are opened in MEMS layer 405 (down to the sacrificial layer 427) to define MEMS structure 451. In various examples, a single second gap 453 may be etched around MEMS structure 451 (e.g., in a loop or other type of closed gap), while in other examples, several second gaps 453 are opened to define MEMS structure 451 (e.g., separate second gaps are opened which then connect to form a gap around MEMS structure 451).

[00148] In various examples, a width of the second gaps 453 may be larger than a width of the first gaps 423. The second gaps 453, being defined in the MEMS layer 405, may be formed using a process, such as deep UV lithography, which is less-precise than a process by which the first gaps 423 were formed (such as extreme UV, electron-beam lithography or other lithography method). Advantageously, the formation of structure 480 allows for such a process to be used to form second gaps 453 while a more-precise process is used to form the optical structure(s) 421 and gaps in the PIC layer 401.

[00149] MEMS structure 451 is defined (e.g., formed in a location in MEMS layer 405) such that it includes the portion(s) of the MEMS layer 405 which are mechanically coupled, via the coupling element(s) 429, to the first portion(s) 425 of the PIC layer 401. Accordingly, MEMS structure 451 is separated from the remainder of MEMS layer 405 (and any other MEMS structures defined in MEMS layer 405) or coupled to the remainder of MEMS layer 405 only via an attachment system such as the anchor and spring system described herein. Further, MEMS structure 451 is mechanically coupled to the PIC layer 401.

[00150] MEMS structure 451 is moveable (i.e., deflectable); for example, responsive to a force acting on MEMS structure 451 or on structure 480 as a whole, MEMS structure 451 would be displaced (e.g., would deflect) from a position at which it is initially located (e.g., when at rest, or an equilibrium position etc.). Additionally, the mechanical coupling to the first portion(s) 425 means that displacement of MEMS structure 451 may result in displacement of the first portion(s) 425 of the PIC layer. For example, the resulting displacement of the first portion(s) 425 may be the same as, proportional to or at least based on the displacement of the MEMS structure 451.

[00151] It will be appreciated that an optical field characteristic of the optical structure 421 may be influenced or affected by MEMS structure 451, first portion(s) 425, displacement of MEMS structure 451 and/or displacement of first portion(s) 425. For instance, an optical field (e.g., evanescent field) may extend from the (boundary of the) optical structure 421 such that the first portion(s) 425 and/or the MEMS structure 451 are located within the optical field. This has an effect on one or more optical field characteristics of the optical structure 421 as described above in relation to Figures 1A to 10 (where proximity of the first portion(s) 425 may have an analogous effect to that arising due to the proximity of MEMS structure 109 in Fig. 10). For example, in the case of optical structure 421 being an optical microresonator, a resonance wavelength may be shifted and/or a broadening or deepening of the curve of the optical resonance may arise due to presence and/or movement of a mass (i.e., first portion(s) 425, MEMs structure 451) in the evanescent field of the microresonator.

[00152] In some examples, an optical microresonator may be provided in the PIC layer 401 on two or more (e.g., opposite) sides of the MEMS structure 451, with interaction between the two or more optical microresonators. In various examples, two or more optical structures (e.g., optical microresonators) may be located with respect to the MEMS structure 451 such that a movement of the MEMS structure 451 towards one of the optical structures results in a corresponding movement of the MEMS structure 451 away from another one of the optical structures (thereby allowing for differential sensing). For instance, a first optical microresonator may be defined in a first region of PIC layer 401 located on the other side of a first gap 423 from a side on which a first portion 425 with a corresponding coupling element 429 are provided, and a second optical microresonator may be defined in a second region of PIC layer 401 located on the other side of another first gap 423 (or the same first gap 423, if the first gap 423 loops around the first portions 425) from a side on which another first portion 425 with another corresponding coupling element are provided. The first optical microresonator and the second optical microresonator are located on opposite sides of the MEMS structure 451. For example, when structure 480 is viewed from above, such as from a direction perpendicular to a surface of the PIC layer 401 or MEMS layer 405, the first optical microresonator is viewed to be on one side of the MEMS structure 451 while the second optical microresonator is viewed to be on an opposite side of the MEMS structure 451. Accordingly, movement of the MEMS structure 451, or first portion(s) 425 towards one of the first and second optical microresonators will result in a corresponding movement away from the other one or the first and second optical microresonators, and vice versa. It will be appreciated that other examples may provide four optical microresonators in the PIC layer 401, such as to surround the MEMS structure 451 at equal intervals.

[00153] Although not shown in Fig. 4E, in certain examples MEMS structure 451 may also be coupled to another part of structure 480, such as to another part of MEMS layer 405, or to a part of handle layer 409 or other/insulator layer 407 which remains above the MEMS layer 405 after the removal described in combination with Fig. 4D, or to an external structure, via one or more resiliently deformable coupling elements, such as (but not limited to) a spring(s) as mentioned above, so as to aid suspension of MEMS structure 451 and first portion(s) 425 while allowing for displacement of MEMS structure 451 and also controlling displacement of MEMS structure 451 (e.g., depending on a tension of the resiliently deformable coupling element(s)). Additionally, other components (not shown) may be provided for controlling the displacement of MEMS structure 451; e.g., providing a force (e.g., actuating force, countering force etc., via one or more electrodes) to restore a displaced MEMS structure 451 back to an equilibrium position, or otherwise limiting an extent to which MEMS structure 451 may displace without loss of information on a force experienced by the MEMS structure 451. For example, an actuating force of an electrode as mentioned above may be used to actively restore the MEMS structure 451 back to equilibrium, extending the linearity and sensing range, and reducing or counteracting drift that may occur over time due to temperature fluctuations, biases or non-linearities at large displacements.

[00154] It will be appreciated that, in some examples, when a plurality of optical structures are provided in the PIC layer 401 around the MEMS structure 451, the MEMS structure 451 may be attached to a part of a layer (e.g. another part of MEMS layer 405, handle layer 409 or insulator layer 407) remaining around the MEMS layer 405 (i.e., a part not removed from around the region of the MEMS layer 405 where the MEMS structure 451 was to be formed) using a system of springs and anchors, such that the MEMS structure is suspended between the optical structures and capable of being resiliently displaced from an at-rest or initial position. Also, the other components/elements referred to above (e.g., an electrode, actuator etc.) may also be provided in combination with the spring(s) to aid in returning the MEMS structure 451 to the equilibrium, limiting the extent to which MEMS structure 451 can move between the optical structures, and/or any other aim/effect mentioned above in relation to such elements/components. Reference is made to Figure 1D for an example of a system of springs and anchors for coupling a M EMS structure to a surrounding part of a MEMS layer.

[00155] Structure 480 is shown to include a single MEMS structure 451 in the cross-sectional example of Fig. 4E, but it will be appreciated that more than one (i.e., other) MEMS structure(s) may be provided in MEMS layer 405. For example, in the case of structure 480 being repeated across/throughout a wafer (or a pair of bonded wafers), a plurality of MEMS structures 451 may be defined, each located in respect of corresponding PIC layer 401 features (e.g., first portion(s) 425), coupling element(s) 429 and/or cavity 435.

[00156] Figure 4F illustrates structure 490 obtained by processing structure 480. Said processing may be to remove a portion/part of the sacrificial layer 427 from at least between the first portion(s) 425 and the MEMS structure 451 and the first portion(s) 425 and first gap(s) 423 and/or to remove a portion/part of the sacrificial layer 427 so as to open the first gap(s) 423 to the second gap(s) 453 (i.e., such that a material, such as that forming the sacrificial layer 427, is not present between the one or more first gaps 423 and the one of more second gaps 453). This has the effect of releasing the MEMS structure 451 from the sacrificial layer; e.g., the MEMS structure 451 may move freely as a result (or move based on the constraints arising from a spring and anchor system, or the like, attaching the MEMS structure 451 to another part of the MEMS layer 405), as can the first portion(s) 425 via the coupling element(s) 429.

[00157] In some examples, a portion of the sacrificial layer 427 may remain between the first portion(s) 425 and the MEMS structure 451, so long as the MEMS structure 451 and first portion(s) 425 are released from the surrounding portions of sacrificial layer 427; such as portions of sacrificial layer 427 which may be between the first portion(s) 425 and another part of the PIC layer 401 (such as the optical structure 421 and/or a part on a side of a first gap 423 opposing a first portion 425).

[00158] As discussed elsewhere herein, displacements of the MEMS structure 451 and/or the first portion(s) 425 may affect an optical field characteristic(s) of the optical structure 421, thereby allowing for various functionality. For example, structure 490 may be used in an accelerometer, gyroscope or other inertial sensor. Other uses exist for a chip such as, or incorporating, structure 490; for example, as an optoelectronic or optomechanical pick-up for reading out a MEMS device (such as MEMS structure 451, or a displacement thereof), e.g., in place of solutions that use capacitive read-outs, such as in microphones and timing oscillators. The optical pickup has the significant advantage over traditional capacitive read-outs in that it is immune (at least substantially so) to the effects of spurious electrical noise or interference while being at least as sensitive in detection.

[00159] In an example, the processing may be by an etching process, such as vapor etching. For instance, hydrogen fluoride (HF) vapor etching may be used to etch the sacrificial layer 427 away from the MEMS structure 451. In this case, vapor HF etches isotropically (having similar etch rate in vertical and horizontal direction), which may result in parts of the sacrificial layer 427 over and under parts of the PIC layer 401 (e.g., around an end of optical structure 421 as shown in Fig. 4F) to be removed. In other words, the HF vapor etching may be controlled such that it only partially releases parts of the optical structure 421. MEMS structure 451 may have holes in it to influence the rate of removal of the sacrificial layer underneath and around it. Furthermore, the vapor HF etching may remove part of oxide layer 433, such as around the cavity 435. Additionally, the sacrificial layer 427 around the first portion(s) 425 may also be removed.

[00160] In certain examples, it may be regarded that that processing illustrated in Fig. 4F is to reveal the first gap(s) 423 in the PIC layer 401. This may correspondingly release the MEMS structure 451 and first portion(s) 425.

[00161] Resulting structure 490 may be regarded as chip, circuit or IC comprising a PIC layer 401 (including optical structure(s)/features) and a MEMS layer 405 (including MEMS structure(s)/features). Accordingly, through the steps illustrated in Figs. 4A to 4F, with reference also to Figs. 2A to 2C, 3A to 3D and/or 7, a second method for providing/producing/manufacturing such a structure (i.e., chip, circuit, IC etc.) is given.

[00162] In an optional further step, a cap wafer (not shown) may be bonded over the structure 490. For example, a bond ring included in (e.g., formed on a surface of) a cap wafer may be bonded to the bond ring corresponding to bond ring elements 441, 443. This may seal (e.g., vacuum seal, hermetic seal) a space under the cap wafer, which may include cavity 432, first gap(s) 423 and second gap(s) 453.

[00163] The second method described above provides a number of advantages. Various examples according to the second method allow for the gap between MEMS device feature and PIC device features (e.g., the first gap(s) 423) to be very small, for instance due to being able to leverage smaller lithography node at a PIC foundry processing the PIC layer 401 or providing a wafer with PIC layer 401. Additionally, various examples in accordance with the second method, by utilising a DSOI wafer, allow for all crystalline silicon to be used, providing better layer dimension accuracy and mechanical robustness.

Additionally, various examples in accordance with the second method allow for increased flexibility (relatively speaking) for changes to depths of MEMS features and laser cavities because they are created within a second, bulk wafer.

[00164] A third method for providing a structure comprising a PIC layer (including optical structure(s)/features) and a MEMS layer (including MEMS structure(s)/features) is now given in combination with Figures 5A to 5H, which provide schematics to illustrate progression through the method via cross-sections of a part of a wafer. In the following description of the given example, the structure may at times be non-limitingly referred to as a chip or circuit. It will be appreciated that various features shown in Figs. 5A to 5H may, optionally, share the same or similar properties as corresponding features shown in one of Figs. 2A to 2C, 3A to 3D, 4A to 4F and/or 7.

[00165] Figure 5A illustrates a structure 500 comprising a first layer 501, a second layer 503, a third layer 505, a fourth layer 507 and a fifth layer 509. The first layer 501 is a PIC layer 501, and may be referred to as such from hereon. The third layer 505 is a MEMS layer 505, and may be referred to as such from hereon.

[00166] The PIC layer 501 may include, or be formed of, a photonic capable material. In some examples, the PIC layer 501 may include, or be formed of, a stack of photonic materials, for example the stack including indium phosphate or germanium etc., where one or more material included in the stack may be used to define a laser(s) and/or a photodetector(s). The MEMS layer 505 may include, or be formed of, a crystalline or polycrystalline material such as silicon or glass. If silicon, dopants may be added to achieve semiconducting or conducting capabilities. In various examples, MEMS layer 505 and PIC layer 501 may both be layers of silicon, silicon germanium, germanium, indium phosphide, gallium nitride or silicon carbide. Alternatively, each of MEMS layer 505 and PIC layer 501 may be formed of the same or a different one of: silicon, silicon nitride, polysilicon, silicon germanium, germanium, indium phosphide, gallium nitride or silicon carbide.

[00167] The second layer 503 and the fourth layer 507 may be insulator layers and/or sacrificial layers. In various examples, one or both of the second layer 503 and the fourth layer 507 may be a layer of silicon oxide (i.e., an oxide layer or buried oxide).

[00168] The fifth layer 509 may be a handle layer 509 (e.g., a handle wafer). In an example, the handle layer 509 is formed of crystalline silicon.

[00169] In an exemplary case where the PIC layer 501 and the MEMS layer 505 are silicon layers and the second layer 503 and the fourth layer 507 are buried oxide layers, structure 500 may be provided by a double silicon-on-insulator (SOO wafer (DSOI wafer) having a buried cavity.

[00170] A cavity 511 is shown formed in structure 500, in the handle layer 509. This cavity may be formed in the handle layer 509 (e.g., in the bulk) by conventional methods and may have a similar purpose to that given for other cavities described herein.

[00171] It will be appreciated that the structure 500 illustrated in Fig. 5A may be repeated across/through a wafer a number of times (e.g., a predetermined number, based on manufacturing capabilities and/or designs). As such, a wafer provided via the third method of the present disclosure may comprise a plurality of cavities in bulk layer 509, with structures 500 arranged accordingly. Similar comments apply to the structures shown in Figs. 5B to 5H, in that the structures (of which a cross section is illustrated, from which a full structure (e.g., three dimensional structure) may be derived) may be repeated across a larger wafer.

[00172] A first step includes processing (PIC processing) structure 500 to obtain structure 510, shown in Fig. 5B. In various, non-limiting examples, this processing may be performed using electron-beam lithography or deep ultraviolet lithography, or next-generation lithography methods such as X-ray lithography, focused ion beam lithography, quantum lithography, extreme ultraviolet lithography and nanoimprint lithography, followed by etching.

[00173] In particular, as shown in Fig. 5B, PIC layer 501 may be processed to form: at least one optical structure 521 (where one is shown in the cross-sectional example of Fig. 5B but more may be formed in the structure 510), at least one gap 523 (e.g., first gap(s) 523; these may alternatively be termed first space(s), first opening(s), first trench(es) etc.), at least one portion 525 (e.g., first portion(s) 525 -where one is shown in the cross-sectional example of Fig. 5B but more may be formed in the structure 510; these may alternatively be termed first region(s), first part(s), first section(s) etc.), and other gap(s) (e.g., the gap on the side of optical structure 521 other than the side on which a first gap 523 is defined). Other features which may (optionally) be formed in the PIC layer 501 include other portion 529, grating(s) and/or waveguides(s) (e.g., an input waveguide and/or an output waveguide). According to various examples, these features may be formed by etching the PIC layer 501. Of course, additional photonic features to those described above may also be included in (e.g., formed in) PIC layer 501.

[00174] The first gap(s) 523 may have a size similar to that of distance d as defined in relation to Fig. 1C. For example, the first gap(s) may have a width (i.e., wall to wall) of < 1pm, with the gap being < 500nm in certain examples. The width of the first gap(s) may be dependent on the limits of the lithography performed prior to the etching of the first gaps.

[00175] The first gap(s) 523 may define, at least partly, the first portion(s) 525. It will be appreciated that a single first gap 523 may be defined in PIC layer 501, where this first gap 523 is a closed loop around the at least one first portion 525. In which case, the two first gaps 523 indicated in Fig. 5C illustrate different parts of the same first gap 523, providing cross-sections of this first gap 523. In other examples, a plurality of first gap(s) 523 may be formed to define the at least one first portion(s) 525 in the PIC layer 501. For example, a plurality of first gaps 523 may be defined separately and then joined together to define the at least one first portion(s) 525. Alternatively, separate first gap 523 may be defined to an edge of a wafer or a structure 520, to define the at least one first portion(s) 525.

[00176] The optical structure(s) 521 may have a corresponding optical field, similar to as defined for optical structure 131 in relation to Figs. 1A to 1D. For instance, the optical structure 521 may be a microresonator (e.g., a whispering gallery mode resonator), and the optical field may correspond to the evanescent field deriving from light propagating in the microresonator. Although not shown, the PIC layer 501 may further include an input waveguide arranged to provide light to the optical structure 521 (e.g., via coupling) and an output waveguide arranged to receive light from the optical structure 521 (e.g., via coupling). Alternatively, such waveguides may be provided elsewhere on the structure, if included.

[00177] A second step, as illustrated in Figure 5C through structure 520, is to oxidize to protect the features formed in the PIC layer 501. As a result, structure 520 comprises an oxidized layer 527, or sacrificial layer 527 hereafter, which at least partly surrounds the PIC layer 501 (in particular, covering the optical structure 521, the first gaps 523 and the at least one first portion 525 so as to protect these features). As well as, or as an alternative to, oxidation, in some examples, silicon oxide materials may be deposited and/or planarization is also performed to smooth the surface of the sacrificial layer 527. In various examples, a second processing step may include deposition of silicon oxide materials(s), such as PECVD oxide or Tetraethyl orthosilicate TEOS over the PIC layer 501.

[00178] In various examples, one or more active layers (not shown in the figures) are formed structure 520, such as prior to the oxidization step or deposition step. For example, an active layer (e.g., of germanium or indium phosphide) may be formed on at least part of PIC layer 501, for use in defining one or more lasers and/or one or more photodetectors in a resulting structure/chip/wafer, and oxidization results in the sacrificial layer 527 at least partly surrounding the active layer. Reference is made to Fig. 7 for an example of the formation of such features.

[00179] In certain examples, it may be considered that sacrificial layer 527 and the second layer 503 essentially form a single layer or portion of structure 520 (e.g., sacrificial layer 527 comprises the second layer 503, as well as the protective layer over and around the features). In the following, references to the sacrificial layer 527 may also be considered to refer to at least part of the second layer 503 and/or to at least part of the material resulting from the oxidation step.

[00180] A third step, as illustrated in Figure 5D, is to remove part of the sacrificial layer 527 to reveal the MEMS layer 505 (e.g., a portion of the surface of the MEMS layer 505) through the first gap(s) 523. Optionally, as shown, portions of the sacrificial layer 527 at either end of the structure 530 may also be removed, to expose further portions of the surface of MEMS layer 505. For example, as will be shown later, a laser or laser die may be provided to the right of the optical structure 521 in a space, or recess, from which a portion of the sacrificial layer 527 was removed, while an electrode 531 may be provided to the left of other portion 529. Removal of the sacrificial layer may be performed by a conventional etching process, e.g., an etching process capable of providing the resolution required for etching narrow features, such as within the first gap(s) 523 (which, in some examples, are shown to have a width of 100nm to 500nm ±50nm).

[00181] At this stage, one or more electrodes 531 and bond ring elements 533, 535 may be formed, e.g. metallized, thereby providing structure 530 with these features. In various examples, bond ring elements 533, 535 correspond to a single bond ring surrounding a portion of the surface of sacrificial layer 527. In other words, when viewed from above, structure 530 comprises a bond ring encircling part of the top of structure 530, such as by surrounding the first gap(s) 523 (i.e., the gaps in the sacrificial layer 527 which are defined to reveal a part of the surface of MEMS layer 505 through the first gap(s) 525). Bond ring elements 533, 535 thereby illustrate different parts of the cross section of the bond ring, in this example.

[00182] Optionally, a recess may be formed in the MEMS layer 505 at the side of the optical structure 521, e.g., where a portion of the sacrificial layer 527 has been removed to expose the MEMS layer 505. This recess is illustrated in structure 540 of Figure 5E, where a pad 541 (or support 541) is formed (e.g., from AuSn), optionally with alignment targets. The purpose of such a recess may be for accommodating a laser die (e.g., affixed onto pad 541). Of course, in certain examples such a recess is not needed as etching away the portion of the sacrificial layer may provide enough of a space for mounting a laser die, depending on properties (e.g., size) of the laser. As another alternative, removing this portion of the sacrificial layer (i.e., the portion to the side of the optical structure 521 other than the side on which the first gap 523 is defined) is itself optional, particularly if a laser die is not used for providing light to optical structure 521. It will be appreciated that other methods of coupling light into optical structure 521 are contemplated, which do not involve a laser die mounted adjacent to a sidewall of the optical structure 521. If included, the alignment targets may be for use in aligning the laser die with the optical structure 521.

[00183] Referring to Figure 5F, in structure 550, MEMS structure 551 is defined in MEMS layer 505 by removing a portion(s) of MEMS layer 505 either side of MEMS structure 551, to define at least one second gap 553. For example, a single second gap 553 may be formed around MEMS structure 551 to release it from the remaining part of MEMS layer 505, or a plurality of second gaps 553 may be formed around MEMS structure 551 and then interconnected so as to define MEMS structure 551. In an example, to process the MEMS layer 505 to form MEMS structure 551, DRIE may be used. The second gap(s) 553 may be formed through the first gap(s) 523, constraining a width of the second gap(s) 553.

The second gap(s) 553 may be open to the first gap(s) 523, with part of the sacrificial layer 527 being absent between the first gap(s) 523 and the second gap(s) 553. Further, it will be appreciated that an HF vapor process may be performed to release (at least partly) the MEMS structure 551 (e.g., release MEMS structure 551 from the fourth layer 507 which may also release MEMS structure 551 from the handle layer 509). Although not shown in Figure 5F, it will be understood that some of fourth layer 507 may remain below (e.g. disposed adjacent to) MEMS structure 551 -this is because HF Vapour may cut laterally as well as vertically and so, for example, some of fourth layer 507 may be removed from between MEMS structure 551 and the handle layer 509 but other portion(s) of fourth layer 507 may remain between MEMS structure 551 and the handle layer 509. Even if such portion(s) of fourth layer 507 remain, however, MEMS structure 551 will still be released.

[00184] It can be seen that MEMS structure 551 is effectively coupled (e.g., mechanically coupled) to the first portion(s) 525 of the PIC layer 501, via an interposing portion of sacrificial layer 527. MEMS structure 551 is suspended over cavity 511 and may move freely (e.g., referring to the description of MEMS structure 451 in relation to movement of a MEMS structure), with the coupled first portion(s) 525 moving freely in correspondence with MEMS structure 551. As will be appreciated in view of the previous disclosure, this will affect an optical field characteristic(s) of the optical structure 521, thereby allowing for various functionality.

[00185] It will be appreciated that, in various examples, the portion of sacrificial layer 527 between the first portion(s) 525 and the MEMS structure 551 may be regarded as at least one coupling element mechanically coupling the first portion(s) 525 and the MEMS structure 551. In other words, the portion of the sacrificial layer 527 acts in an analogous role to the coupling element(s) 429 of Figs. 4A and 4D to 4F and so may be regarded as a coupling element.

[00186] For example, in the case of using structure 550 (or later-described structure 560, 570) in an inertial sensor or for inertial sensing where optical structure 521 is an optical microresonator, changes in an optical field characteristic (such as an optical resonance) of the optical microresonator may be measured to identify a corresponding or associated displacement of the MEMS structure 551 (which may be a test mass) and/or first portion 525 (which may be regarded as a part of the test mass), thereby allowing for measurement or determination of a corresponding inertial force acting on the structure 550 or inertial sensor. As such, structure 550 may be used in an accelerometer, gyroscope or other inertial sensor.

[00187] In various examples, an additional optical microresonator (not shown) may be provided on an opposite side of MEMS structure 551 (i.e., on an opposite side of the first portion 525 of the PIC layer 501 coupled to the MEMS structure 551. This may be similar to the example with two optical microresonators described above in relation to Fig. 4E, where movement of the MEMS structure 551 (or first potion 525) towards one optical structure results in a corresponding movement away from the other optical structure.

Further, in various examples four optical microresonators may be provided as locations in the PIC layer 501 which are equally spaced around the MEMS structure 551 or first portion 525. The details of such arrangements of a plurality of optical structures in the PIC layer 501 around the MEMS structure 551 may be the same as the details given for the case of a plurality of optical structures in the PIC layer 401 around MEMS structure 451 described above in relation to Figs. 4A to 4F. As such, the features of such arrangements described above in relation to Figs. 4A to 4F are relevant here also, and incorporated into the description of Figs. 5A to 5H.

[00188] Other uses exist for a chip or circuit such as, or including, that of structure 550; for example, as an optoelectronic or optomechanical pick-up for reading out a MEMS device (such as MEMS structure 551, or a displacement thereof), e.g., in place of solutions that use capacitive read-outs, such as in microphones and timing oscillators.

[00189] In certain examples, MEMS structure 551 is in accordance with any other MEMS structure defined herein -e.g., it may be an inertial test mass (e.g., for use in inertial sensing as indicated above), a thin plate or diaphragm (e.g. for use in a microphone, pressure sensor, or ultrasonic transceiver) or a resonant structure (e.g. for use in an oscillator or clock).

[00190] Although not shown, structure 550 may also comprise one or more electrical couplers for electrically coupling the MEMS structure 551 and a part of PIC layer 501 (such as first portion(s) 525). For example, one or more parts of the PIC layer 501 may be doped to provide electrical routing to the MEMS layer 505 or a part(s) thereof (e.g., MEMS structure 551).

[00191] In a further operation, portions of sacrificial layer 527 are removed from around the sidewall(s) of one or more features in the PIC layer 501. This process may include vapor HF etching to remove the portions of sacrificial layer 527. For example, as illustrated in Fig. 5F, one or more sidewalls of the optical structure 521 (including sidewall 521a, shown to provide an example of a sidewall as referred to here), the first portion(s) 525 and the other portion 529 are revealed by removing at least a portion of the sacrificial layer 527. In this case, a sidewall (such as sidewall 521a of optical structure 521) refers to a surface of a PIC feature which is perpendicular to a longitudinal direction of the PIC layer 501 (i.e., the longitudinal direction being the direction along a wafer comprising structure 550, represented by 'x' in Fig. 5F), or which is parallel to the direction represented by 'y in Fig. 5F. For instance, sidewall 521a of optical structure 521 may be revealed to allow for light to be coupled into the optical structure 521 (e.g., via an input waveguide (not shown) or a laser die mounted adjacent to the optical structure 521 (shown in Fig. 5H)). For instance, a portion of sacrificial layer 527 may be removed to reveal a sidewall of optical structure 521 (on an opposite side to sidewall 521a) and a facing sidewall of first portion 525, thereby enhancing or otherwise effecting interaction between these components. That is, a displacement of first portion 525 may differently affect an optical field characteristic of optical structure 521 depending on whether any sacrificial layer is present between the respective sidewalls of these features in the PIC layer 501.

[00192] Referring now to Figure 5G, the result of a further, optional step of attaching or bonding a cap wafer 561 over structure 550 is shown, illustrated by structure 560. Cap wafer 561 may comprise contacts 563 and 565 for bonding to corresponding contacts on the sacrificial layer 527, e.g., bond ring elements 533, 535. In an example, such as when bond ring elements 533, 535 represent portions of the same bond ring, contacts 563 and 565 correspond to portions of the same bond ring on cap wafer 561. For example, a single bond ring is provided on cap wafer 561 (e.g., along a perimeter of cap wafer 561), with a size and shape corresponding to that of the bond ring provided on the sacrificial layer 527.

Cap wafer 561 is thereby bonded to structure 550 through affixing or bonding the bond ring on cap wafer 561 to the bond ring on sacrificial layer 527. This may be by metal bonding (e.g. eutectic bonding, thermocompression bonding) etc. [00193] The cap wafer 561 is to seal (e.g., in the case of an inertial sensor or resonator, to create a vacuum seal) the space comprising the cavity 511, the first gap(s) 523 and the second gap(s) 553; i.e., the space under the cap wafer 561. In some examples, the vacuum will be created during the bonding step (or the desired operating pressure of the device).

[00194] Optionally, as illustrated in Figure 5H, a laser die 571 may be provided in the recess at the end of the structure 570; such as in a recess formed by removing a portion of the sacrificial layer 527 and/or a portion of MEMS layer 505. It is, however, not essential to include a laser die in the structure 570. Further, in some examples, a laser (e.g., laser die 571) may be placed/located on PIC layer 501, such as on a top layer of PIC layer 501, and this may be an alternative to forming the recess and providing a laser die in the recess. For example, a laser may be provided on part of a surface of PIC layer 501, which is opposite to a surface facing MEMS layer 505, where sacrificial layer 527 has been removed from around this part of the surface of PIC layer 501. In various examples, instead of or separately to laser die 571, a photodetector(s) may be located in the recess, where the photodetector(s) is optically coupled to the optical structure 521 through the surface of the optical structure 521 facing the recess.

[00195] Although not illustrated in Figures 5A to 5H, one or more coupling elements may be provided between the first portion 525 and the MEMS structure 551, to mechanically, and optionally electrically, couple the first portion 525 of the PIC layer 501 and the MEMS structure 551. Said coupling element(s) may be formed at any stage during the method described above, with the possible exception of after a cap wafer 561 has been attached as shown in Fig. 5G. For example, prior to the features in the PIC layer 501 being defined (Fig. 5B), coupling element(s) may be formed by opening a via(s) in the PIC layer 501 (i.e., in the first portion(s) 525) down to (and, optionally, into) the MEMS layer 505 (through sacrificial layer 503), and filling the via with a suitable material for the coupling. The via(s) may be aligned with the region of the MEMS layer 505 where the MEMS structure 551 will be defined. In another example, the coupling element(s) may be formed after oxidization (Fig. 5C) or after removing part of the sacrificial layer 527 (Fig. 5D), with the via(s) being opened in the (upper portion of the) sacrificial layer 527, through the PIC layer 501 and through the (lower portion of the) sacrificial layer 527 down to the MEMS layer 505. In another example, the coupling element(s) may be formed before or after defining the MEMS structure 551 (Fig. 5F). If provided, the coupling element(s) may be provided in a similar manner to any of the coupling element(s) 429 described in relation to Figs. 4A to 4F (e.g., to have any one or more features/details of the coupling element(s) 429 described in relation to Figs. 4A to 4F). For example, the coupling element(s) may provide mechanical and/or electrical coupling between PIC layer 501 (or a part(s) thereof) and MEMS layer 505 (or a part(s) thereof).

[00196] The MEMS structure 551 may be coupled to another part of the structure 570, such as to part of MEMS layer 505, fourth layer 507 or fifth layer 509, such that MEMS structure 551 and the first portion(s) 525 coupled thereto may move. For example, a spring and anchor system such as described elsewhere herein (e.g. referring to Fig. 1D) may be provided to suspend the MEMS structure 551 while allowing for the MEMS structure 551 to be displaced.

[00197] The third method described above provides a number of advantages. Various examples according to the third method, by utilising a DSOI wafer, allow for all crystalline silicon to be used, providing better layer dimension accuracy and mechanical robustness.

[00198] A fourth method for providing a structure (e.g., chip, circuit, IC etc.) comprising a PIC layer (including optical structure(s)/features) and a MEMS layer (including MEMS structure(s)/features) is now given in combination with Figures 6A to 6F, which provide schematic illustrate progression through the method via cross-sections of a part of a wafer. It will be appreciated that various features shown in Figs. 6A to 6F may, optionally, share the same or similar properties as corresponding features shown in one of Figs. 2A to 2C, 3A to 3D, 4A to 4F, 5A to 5H and/or 7.

[00199] Figure 6A illustrates a cross-section of a structure 600 comprising a first layer 601, a second layer 603 and a third layer 609.

[00200] The first layer 601 is a PIC layer 601, and may be referred to as such from hereon. As for PIC layer 201 and 501, the PIC layer 601 of structure 600 may be formed of, or include, a photonic capable material. In some examples, the PIC layer 601 may include, or be formed of, a stack of photonic materials, for example the stack including indium phosphate or germanium etc., where one or more material included in the stack may be used to define a laser(s) and/or a photodetector(s). For example, PIC layer 601 may be formed of silicon, silicon nitride, polysilicon, silicon germanium, germanium, indium phosphide, gallium nitride or silicon carbide.

[00201] The second layer 603 may be an insulator layer and/or sacrificial layer. In various examples, the second layer 603 may be formed of silicon oxide (i.e., may be a buried oxide layer). The third layer 609 may be a handle layer 609 (e.g., a handle wafer), which may, in various examples, be formed of crystalline silicon.

[00202] In an exemplary case where the PIC layer 601 is a silicon layer and the second layer 603 is a buried oxide layer, structure 600 may be provided by a silicon-on-insulator wafer (SOl wafer), particularly a PIC quality SOI wafer.

[00203] A first step includes processing (PIC processing) structure 600 to obtain structure 610, shown in Fig. 6B. In various, non-limiting examples, this processing may be performed using electron-beam lithography or deep ultraviolet lithography, or next-generation lithography methods such as X-ray lithography, focused ion beam lithography, quantum lithography, extreme ultraviolet lithography and nanoimprint lithography, followed by etching.

[00204] In particular, as shown in Fig. 6B, PIC layer 601 may be processed to form: at least one optical structure 621 (where one is shown in the cross-sectional example of Fig. 6B but more may be formed in the structure 610), at least one gap 623 (e.g., first gap(s) 623; these may alternatively be termed first space(s), first opening(s), first trench(es) etc.), at least one portion 625 (e.g., first portion(s) 625 -where one is shown in the cross-sectional example of Fig. 6B but more may be formed in the structure 610; these may alternatively be termed first region(s), first part(s), first section(s) etc.), other gap(s) (e.g., the gap on the side of optical structure 621 other than the side on which a first gap 623 is defined), and, optionally, at least one other portion 611, 613 (which may be used for providing other components, such as will be described later). Other features which may (optionally) be formed in the PIC layer 601 include grating(s) and/or waveguides(s) (e.g., an input waveguide and/or an output waveguide). According to various examples, these features may be formed by etching the PIC layer 601.

[00205] The first gap(s) 623 may have a size similar to that of distance d as defined in relation to Fig. 1C. For example, the first gap(s) may have a width (i.e., wall to wall) of < 1 pm, with the gap being < 500nm in certain examples. The width of the first gap(s) may be dependent on the limits of the lithography performed prior to the etching of the first gaps. An example accuracy of this process is ±50nm, although it will be appreciated that this may change depending on the lithographic (or other) method used. In some examples, the first gap(s) are between 100nm and 200nm wide.

[00206] The first gap(s) 623 may define, at least partly, the first portion(s) 625. It will be appreciated that a single first gap 623 may be defined in PIC layer 601, where this first gap 623 is a closed loop or the like around the at least one first portion 625. In which case, the two first gaps 623 shown in Fig. 6C illustrate different parts of the same first gap 623, providing cross-sections of this first gap 623. In other examples, a plurality of first gap(s) 623 may be formed to define the at least one first portion(s) 625 in the PIC layer 601. For example, a plurality of first gaps 623 may be defined separately and then joined together to define the at least one first portion(s) 625. Alternatively, separate first gap 623 may be defined to an edge of a wafer or a structure 620, to define the at least one first portion(s) 625.

[00207] The optical structure(s) 621 may have a corresponding optical field, similar to as defined for optical structure 131 in relation to Figs. 1A to 1D. For instance, the optical structure 621 may be a microresonator (e.g., a whispering gallery mode resonator), and the optical field may correspond to the evanescent field deriving from light propagating in the microresonator. Although not shown, the PIC layer 601 may further include an input waveguide arranged to provide light to the optical structure 621 (e.g., via coupling) and an output waveguide arranged to receive light from the optical structure 621 (e.g., via coupling). Such waveguides may be provided elsewhere on the structure, if included.

[00208] A second step, as illustrated in Figure 6C, is to oxidize to protect the features formed in the PIC layer 601. As a result, structure 620 comprises an oxidized layer 627, or sacrificial layer 627 hereafter. Following oxidation, sacrificial layer 627 may at least partly surround the PIC layer 601 (in particular, covering the optical structure(s) 621, the first gap(s) 623 and the at least one first portion 625 so as to protect these features). As well as, or as an alternative to, oxidation, in some examples, silicon oxide materials may be deposited and/or planarization is also performed to smooth the surface of the sacrificial layer 627. In various examples, a second processing step may include deposition of silicon oxide materials(s), such as PECVD oxide or Tetraethyl orthosilicate TEOS over the PIC layer 601.

[00209] In certain examples, it may be considered that sacrificial layer 627 and the second layer 603 essentially form a single layer or portion of structure 620 (e.g., sacrificial layer 627 comprises the second layer 603, as well as the protective layer over and around the features). In the following, references to the sacrificial layer 627 may also be considered to refer to at least part of the second layer 603 and/or to at least part of the material resulting from the oxidation step.

[00210] Following oxidation, a step of removing part of the sacrificial layer 627 from over at least one portion of the PIC layer 605 is performed, as illustrated by structure 620 in Fig. 6C. In Fig. 6C, the sacrificial layer 627 is shown to be removed, i.e. absent, from over part of first portion 625, and over other portion 611. It will be appreciated that the sacrificial layer 627 may be removed from over additional portions of the PIC layer 601 or not from over the other portion 611; but is advantageously removed from over the first portion(s) 625.

[00211] Figure 6D illustrates the resulting structure 630 from performing a step of growing or depositing a material(s) over the sacrificial layer and the exposed portions/revealed portions of the PIC layer 601. As seen, a first mass or layer of material is formed on first portion 625 (the combination of which is identified as 651, discussed further below), and a second mass 637 or layer of material is formed on sacrificial layer 627. A third mass or layer of material may also be formed on other portion 611.

[00212] In various examples, it will be appreciated that the growing of the material over the portions of the PIC layer 601 (e.g., on first portion(s) 625) may be considered the providing or forming of at least one coupling element between the first portion(s) 625 and a resulting mass of grown/deposited material. That is, an attachment or coupling (e.g., molecular bond) may exist between the first portion(s) 625 of the PIC layer 601 and the deposited material -and this may be regarded as at least one coupling element (analogous to coupling element(s) 429 of Figs. 4A and 4D to 4F).

[00213] For example, in a case where PIC layer 601 is silicon and sacrificial layer 627 is an oxide (e.g., silicon oxide), epitaxial silicon (or, epi silicon) may be grown or deposited (e.g., via a silicon epitaxy process) over structure 620.

[00214] Where epi silicon is provided over silicon, such as on the exposed portions of PIC layer 601, crystalline silicon (c-Si) is formed/grown. As a result, silicon is formed over/on first portion 625, as shown in Fig. 6D, which from hereon is regarded as MEMS structure 651 (which, in various examples, may be in accordance with any of the MEMS structures described herein). In other words, the combination of first portion 625 and the grown/formed material is regarded as MEMS structure 651 (which has dimensions in the order of MEMS feature as opposed to PIC features).

[00215] It may also be considered that MEMS structure 651 is effectively mechanically coupled to the first portion(s) 625 of the PIC layer 601, regardless of whether the two are considered as a single MEMS structure. In other words, the grown mass and first portion(s) 625 may still be regarded as separate elements which are mechanically coupled, even though they are referred to by a single number 651 in Fig. 6D and by the term MEMS structure 651. For instance, it may be regarded that a coupling element is formed of deposited silicon epitaxy; that is, the provision of epi silicon over the exposed portion(s) of the PIC layer 601 forms a coupling element between these exposed portion(s) and what will be the MEMS structure 651.

[00216] Optionally, if other portion 611 of PIC layer 601 is also exposed, crystalline silicon may be formed here also, as shown in Fig. 6D, effectively resulting in other portion 611 being enlarged.

[00217] Where the epi silicon is provided over oxide, such as on the sacrificial layer 627, polysilicon is formed/grown. As mentioned previously, polysilicon has similar material properties to silicon, which may provide advantages in structure 630.

[00218] Following growth or deposition of the material (e.g., epi silicon), structure 630 may be planarized to smooth a top surface of the structure 630 (e.g., smooth the top of silicon (c-Si) and polysilicon regions).

[00219] In various examples, instead of silicon epitaxial deposition, other epitaxial material may be deposited to grow MEMS features, such as MEMS structure 651. For example, SiGe (silicon-germanium) or GaN (Gallium nitride) may be deposited -these being other examples of epitaxial material. Accordingly, although Figs. 6A to 6F are described using the example of silicon epitaxial deposition, it will be appreciated that other epitaxial material may be deposited instead, such as SiGe or GaN, to achieve a similar result.

[00220] Further, one or more electrodes 631 and bond ring elements 633, 635 may be formed, e.g. metallized, thereby providing structure 630 with these features. In various examples, bond ring elements 633, 635 correspond to a single bond ring surrounding a portion of the surface of structure 640, such as surrounding the surface of MEMS structure 651. In other words, when viewed from above, structure 630 comprises a bond ring encircling part of the top of structure 630, such as by surrounding the MEMS structure 651 and the first gap(s) 623 (i.e., the material grown/formed on top of the part of sacrificial layer 627 which fills the first gap(s) 623). Bond ring elements 633, 635 thereby illustrate different parts of the cross section of the bond ring, in this example.

[00221] Following this, as indicated in Figure 6E, the structure 630 is processed to further reveal MEMS structure 651. For example, second gap(s) 643 may be formed, e.g., by etching to remove the formed material (e.g., polysilicon) and portions of sacrificial layer 627 from the places shown in Fig. 6E. For example, DRIE may be used to remove the polysilicon while reactive ion etching (RIE) may be used to remove the portions of sacrificial layer 627.

[00222] In certain examples, MEMS structure 651 may be provided or formed through processing the formed material to define at least one second gap 643, e.g., above the first gap(s) 623. For example, a single second gap 643 may be formed around MEMS structure 651 to release it from the surrounding material (e.g., the polysilicon), or a plurality of second gaps 643 may be formed around MEMS structure 651 and then interconnected so as to release MEMS structure 651. The second gap(s) 643 may be open to the first gap(s) 623, which may at least partly release the MEMS structure 651 from surrounding features such as the second mass 637, other portion 611 of the PIC layer and/or the optical structure 621.

[00223] Optionally, a recess may be formed in structure 630 at the side of the optical structure 621. This recess is illustrated in structure 640 of Figure 6E, where a pad 641 (or support 641) is formed (e.g., from AuSn). Forming the recess may involve etching the polysilicon above the area where pad 641 is provided, and etching the sacrificial layer 627 from above this area also. The pad 641 may be formed on the handle layer 609. The purpose of such a recess may be for accommodating a laser die (e.g., affixed onto pad 641). Of course, in certain examples such a recess is not needed as etching away the portion of the sacrificial layer may provide enough of a space for mounting a laser die. If a laser is not used for (directly) providing light to optical structure 621, formation of a recess is unnecessary. It will be appreciated that other methods of coupling light into optical structure 621 are contemplated, which do not involve a laser mounted adjacent to a sidewall of the optical structure 621. Optionally, alignment targets for the laser may be formed on other portion 613 for use in aligning the laser die with optical structure 621, if exposed by etching the covering polysilicon and sacrificial layer 627.

[00224] Electrical coupling between the MEMS structure 651 and the PIC layer 601 (i.e., a part of PIC layer 601, such as first portion 625) is achieved by the growth of c-Si directly on the PIC layer 601.

[00225] Further processing may be performed on structure 640 to remove portions of sacrificial layer 627 from around the sidewall(s) of one or more features in the PIC layer 601 and to release MEMS structure 651. This process may include vapor HF etching.

[00226] For example, as illustrated in Fig. 6F, sidewalls of the optical structure 621 (including sidewall 621a, which is identified to provide an indication of a sidewall as referred to here) are revealed by removing at least a portion of the sacrificial layer 527. In this case, a sidewall (such as optical structure 621 sidewall 621a) refers to a surface of a PIC feature which is perpendicular to a longitudinal direction of the PIC layer 601 (i.e., the longitudinal direction being the direction along a wafer comprising structure 650, represented by 'x' in Fig. 6F), or which is parallel to the direction represented by 'y' in Fig. 6F. For instance, sidewall 621a of optical structure 621 may be revealed to allow for light to be coupled into the optical structure 621 (e.g., via an input waveguide (not shown) or a laser mounted adjacent to the optical structure 621 (shown in Fig. 6F)). For instance, a portion of sacrificial layer 627 may be removed to reveal a sidewall of optical structure 621 (on an opposite side of optical structure 621 to sidewall 621a) and a facing sidewall of MEMS structure 651, thereby enhancing or otherwise effecting interaction between these components (e.g., a displacement of MEMS structure 651 may differently affect an optical field characteristic of optical structure 621 depending on whether any sacrificial layer is present between the respective sidewalls of these features in the PIC layer 601).

[00227] Additionally, as mentioned above, MEMS structure 651 is released by removing the sacrificial layer 627 from around MEMS structure 651 (e.g., by vapor HF etch). MEMS structure 651 is thereby suspended over a space and may move freely (e.g., similar to the case of MEMS structure 451 and 551). As will be appreciated in view of the previous disclosure, this will affect an optical field characteristic(s) of the optical structure 621, thereby allowing for various functionality. For example, in the case of using structure 640 (or later-described structure 650) in an inertial sensor or for inertial sensing where optical structure 621 is a microresonator, changes in an optical field characteristic (such as an optical resonance) of the microresonator may be measured to identify a corresponding or associated displacement of the MEMS structure 651 (which may be a test mass), thereby allowing for measurement or determination of a corresponding inertial force acting on the structure 640 or inertial sensor. Accordingly, structure 640 may be used in an accelerometer, gyroscope or other inertial sensor. Other uses exist for a chip such as that of, or including, structure 640; for example, as an optoelectronic or optomechanical pick-up for reading out a MEMS device (such as MEMS structure 651, or a displacement thereof), e.g., in place of solutions that use capacitive read-outs, such as in microphones and timing oscillators.

[00228] The MEMS structure 651 may be coupled to another part of the structure 650, such as to part of sacrificial layer 627, part of first layer 601 such as other portion 611 or part of third layer 609, such that MEMS structure 651 may move. For example, a spring and anchor system such as described elsewhere herein may be provided to suspend the MEMS structure 651 while allowing for the MEMS structure 651 to be displaced.

[00229] In certain examples, MEMS structure 651 is in accordance with any other MEMS structure defined herein -e.g., it may be an inertial test mass as mentioned above (e.g., for use in inertial sensing as indicated above), a thin plate or diaphragm (e.g. for use in a microphone, pressure sensor, or ultrasonic transceiver) or a resonant structure (e.g. for use in an oscillator or clock).

[00230] For example, an anchor and spring system may be provided to suspend the MEMS structure 651 in the structure. Here, springs and anchors (e.g., formed of crystalline silicon) may also be grown (e.g. as part of growing the MEMS structure 651 or in a separate growing/deposition process); the anchors may be grown with a large surrounding mass (e.g. forming a frame around the MEMS structure 651, in-plane and/or extending above and/or below the MEMS structure 651), whereas the springs may be grown with the spring shape already defined by the underlying PIC portion (e.g. part of PIC layer 601). Alternatively, the springs may be grown in a block (e.g., on PIC layer 601) and then the shapes of the springs may be etched/defined with DRIE afterwards (e.g. the DRIE would eat through the grown silicon and the underlying PIC silicon, thereby forming the shape of the springs). It will be appreciated that all parts of any/the grown MEMS feature(s) may have a foundation in/on a part(s) of the PIC layer 601 that the MEMS feature(s) is/are grown from. Growing MEMS features from a pre-existing portion of the PIC layer 601 (such as may be formed of silicon) allows for the formation of thick MEMS structures/features (such as may be formed of silicon). Etching may then be used after the epi growth to define more sophisticated shapes in the grown MEMS structures/features, such as a spring shape. Etching may also be used to define vent holes in the structure (e.g., in the created MEMS feature(s)), which may facilitate the vapor HF in releasing the MEMS structure 651 by allowing the vapor HF to pass through the grown MEMS feature(s). As such, the MEMS structure 651 may be coupled with the springs and anchors, suspending the MEMS structure 651 and allowing for it to be displaced as discussed elsewhere herein.

[00231] Fig. 6F also shows the result of a further, optional step of attaching or bonding a cap wafer 661 over structure 640, illustrated by structure 650. Cap wafer 661 may comprise contacts 663 and 665 for bonding to corresponding contacts on structure 640, e.g., bond ring elements 633, 635. In an example, such as when bond ring elements 633, 635 represent portions of the same bond ring, contacts 663 and 665 correspond to portions of the same bond ring on cap wafer 661. For example, a single bond ring is provided on cap wafer 661 (e.g., along a perimeter of cap wafer 661), with a size and shape corresponding to that of the bond ring provided on the sacrificial layer 627. Cap wafer 661 is thereby bonded to structure 640 through affixing or bonding the bond ring on cap wafer 661 to the bond ring on sacrificial layer 627. This may be by metal bonding (e.g., eutectic bonding, thermocompression bonding) etc. [00232] The cap wafer 661 is to seal (e.g., in the case of an inertial sensor or resonator, to create a vacuum seal, or a hermetic seal) the space comprising a volume under the MEMS structure 651, the first gap(s) 623 and the second gap(s) 653; i.e., the space under the cap wafer 661. In some examples, the vacuum will be created during the bonding step (or set to the operating pressure desired for the device).

[00233] Optionally, as also illustrated in Figure 6F, a laser die 667 may be provided in the recess at the end of the structure 650; such as in a recess formed as described above. It is, however, not essential to include a laser in the structure 650. In various examples, instead of or separately to laser die 667, a photodetector(s) may be located in the recess, where the photodetector(s) is optically coupled to the optical structure 621 through surface 621a.

[00234] The fourth method described above provides a number of advantages. Various examples according to the fourth method allow for the gap between MEMS device feature and PIC device features (e.g., the first gap(s) 623) to be very small, for instance due to being able to leverage smaller lithography dimensional capabilities at a PIC foundry processing the PIC layer 601 or providing a wafer with PIC layer 601. Additionally, various examples in accordance with the second method may have a lower cost that other methods disclosed herein. Relatedly, an epi silicon additive process is well-established, for example in volume production of inertial sensors such as structure 650, according to various examples, may be suitable for use in (as indicated above).

[00235] Accordingly, four methods of manufacturing (producing, providing etc.) a structure, chip, circuit etc. comprising a PIC layer including a PIC feature and a MEMS layer comprising a MEMS feature capable of interacting with the PIC feature are disclosed herein. As mentioned previously, the scope of the present disclosure covers these methods (including an equivalents to the features or operations disclosed therein), the various structures described throughout the methods (e.g., the individual structures illustrated in Figs. 1A to 1 D, 2A to 2C, 3A to 3D, 4A to 4F, 5A to 5H, 6A to 6F and 7), and the various structures obtained through the methods.

[00236] Many variations of the methods described herein will be apparent to the skilled person.

[00237] Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

[00238] Features, integers, characteristics, compounds, or groups described in conjunction with a particular aspect, embodiment or example of the present disclosure are to be understood to be applicable to any other aspect, embodiment or example described herein unless incompatible therewith. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

The present disclosure is not restricted to the details of any foregoing embodiments. The disclosure extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

[00239] Various functions described herein (e.g., in combination with any embodiment or example of the present disclosure) can be implemented or supported by one or more computer programs, each of which is formed from computer readable program code and embodied in a computer readable medium. The terms "application" and "program" refer to one or more computer programs, software components, sets of instructions, procedures, functions, objects, classes, instances, related data, or a portion thereof adapted for implementation in a suitable computer readable program code. To give an example in relation to the present disclosure, an operation of detecting or measuring a change in an optical field characteristic of an optical structure may be performed by, or in combination with, a computer (e.g., a processor in a computer) executing appropriate instructions stored in a computer readable medium (e.g., on a memory of the computer, such as read only memory (ROM), random access memory (RAM), or a hard disk drive, or on a compact disc (CD), a digital video disc (DVD), could storage, or any other type of memory).

[00240] The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

Claims

CLAIMS1. A structure comprising: a photonic integrated circuit (PIC) layer, wherein at least one first gap is formed in the PIC layer to define at least one first portion, and the PIC layer comprises one or more optical structures each having a corresponding optical field and being located on an opposite side of one of the at least one first gap to one of the at least one first portion of the PIC layer; a micro-electro-mechanical system (MEMS) structural layer comprising a MEMS structure suspended adjacent to the at least one first portion of the PIC layer and defined by at least one second gap in the MEMS structural layer, the MEMS structure deflectable under the application of a force or a perturbation; and a sacrificial layer arranged to separate at least a first part of the PIC layer from at least a first part of the MEMS structural layer, wherein a first part of the sacrificial layer is absent such that the at least one first gap is open to the at least one second gap; wherein the at least one first portion of the PIC layer is mechanically coupled to the MEMS structure so as to move according to a deflection of the MEMS structure; and wherein a change in a spacing between the at least one first portion and an optical structure of the one or more optical structures causes a change in an optical field characteristic of that optical structure.
2. The structure of claim 1, wherein the at least one first portion is electrically coupled to the MEMS structure.
3. The structure of claim 1 or claim 2, wherein the structure comprises at least one coupling element, and the mechanical coupling between the at least one first portion of the PIC layer and the MEMS structure is provided by the at least one coupling element.
4. The structure of claim 3, wherein the at least one coupling element is configured to electrically couple the at least one first portion to the MEMS structure; or wherein the structure further comprises at least one coupler configured to electrically couple the PIC layer to the MEMS structure.
5. The structure of claim 3 or claim 4, wherein the at least one coupling element comprises polysilicon, doped polysilicon, crystalline silicon, doped crystalline silicon, an electrically conducting material or a semiconducting material.
6. The structure of any of claim 3 to 5, wherein each of the at least one coupling element is formed in a via through a part of one of the at least one first portion to a part of the MEMS structure, wherein the MEMS structure is non-contiguous with the at least one first portion.
7. The structure of claim 6, further comprising a cavity provided under the at least one first portion on a side of the at least one first portion opposite to a side of the at least one first portion on which the MEMS structure is located.
8. The structure of any of claim 3 to 5, wherein the at least one coupling element is provided by a second part of the sacrificial layer between the MEMS structure and the at least one first portion, wherein the MEMS structure is non-contiguous with the at least one first portion.
9. The structure of claim 8, further comprising a cavity provided under the MEMS structure on a side of the MEMS structure opposite to a side of the MEMS structure on which the at least one first portion is located.
10. The structure of any of claims 6 to 9, wherein the MEMS structure is defined by the at least one second gap opened in the MEMS structural layer around the MEMS structure, to separate the MEMS structure from the remaining part of the MEMS structural layer.
11. The structure of any of claim 3 to 5, wherein the at least on coupling element is formed through depositing material on the at least one first portion to provide the MEMS structure contiguous with, and mechanically coupled to, the at least one first portion.
12. The structure of claim 11, wherein the at least one coupling element is formed by epitaxial deposition on the at least one first portion and on at least part of the sacrificial layer to grow a first mass of first material on the at least one first portion and a second mass of second material on the sacrificial layer; wherein the first mass and the second mass correspond to the MEMS structural layer and the first layer comprises the MEMS structure; and wherein the at least one coupling element corresponds to a bonding region between the at least one first portion and the first mass.
13. The structure of claim 12, wherein: the PIC layer is formed of silicon; the sacrificial layer is formed of an oxide; the first material is crystalline silicon formed by silicon epitaxial deposition onto the PIC layer; and the second material is polysilicon formed by silicon epitaxial deposition onto the sacrificial layer.
14. The structure of any of claims 11 to 13, wherein the at least one second gap is formed in the second mass around the first mass, and the at least one second gap is arranged to connect or align with the at least one first gap.
15. The structure of claim 10 or claim 14, wherein each of the at least one first gap is a gap of between 100nm to 500nm; and/or wherein each of the at least one second gap around the MEMS structure is larger than each of the at least one first gap.
16. The structure of any previous claim, wherein the PIC layer further comprises: one or more input waveguides each configured to provide input light to one of the one or more optical structures; and one or more output waveguides each configured to receive output light from one of the one or more optical structures.
17. The structure of any previous claim, wherein the one or more optical structures are optical resonators and the optical field characteristic is an optical resonance characteristic.
18. The structure of claim 17, wherein the change in the optical field characteristic is a shift in the optical resonance and/or a broadening or deepening of the curve of the optical resonance.
19. The structure of any previous claim, wherein the structure comprises two optical structures; and wherein a change in a first spacing between a first of the at least one first portion and a first of the optical structures and a change in a second spacing between a second of the at least one first portion and a second of the optical structures causes a differential change in the optical field characteristic of the first and the second of the at least two optical structures.
20. The structure of any previous claim, wherein at least one active optical structure is formed on the PIC layer.
21. A method of manufacturing a structure, the method comprising: preparing a stacked structure comprising a photonic integrated circuit (PIC) layer by: forming, in the PIC layer, at least one first gap to define at least one first portion; and forming, in the PIC layer, one or more optical structures, each having a corresponding optical field, wherein each of the one or more optical structures is located on an opposite side of one of the at least one first gap to one of the at least one first portion, wherein the stacked structure further comprises a sacrificial layer adjacent to the PIC layer; and providing, in a micro-electro-mechanical system (MEMS) structural layer, a MEMS structure mechanically coupled to and suspended adjacent to the at least one first portion, such that the MEMS structure is deflectable under the application of a force or a perturbation, and a deflection of the MEMS structure moves the at least one first portion; wherein the MEMS structure is defined in the MEMS structural layer by at least one second gap; wherein the sacrificial layer is arranged to separate at least a first part of the PIC layer from at least a first part of the MEMS structural layer, wherein a first part of the sacrificial layer is absent such that the at least one first gap is open to the second gap; and wherein a change in a spacing between the at least one first portion and an optical structure of the one or more optical structures causes a change in an optical field characteristic of that optical structure.
22. An apparatus comprising: a structure according to any one of claim 1 to 20, wherein light is coupled into and out of each of the one or more optical structures; one or more detectors configured to detect light received from one or more optical structures; and one or more processor configured to: receive an output of the one or more detectors, and determine the change in the spacing between the at least one first portion and an optical structure of the one or more optical structures by detecting the change in the optical field characteristic of that optical structure.
23. The apparatus of claim 22, wherein the apparatus is, or is included in, an inertial sensor, a microphone, a timing oscillator, a pressure sensor, an ultrasound transceiver, a micro-mirror or a micro-structure configured to change a spacing of the micro-structure in response to an applied force or perturbation.
24. A wafer comprising a plurality of structures according to any one of claims 1 to 20.