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HK1040824A1 - Data storage and processing apparatus, and method for fabricating the same - Google Patents

Data storage and processing apparatus, and method for fabricating the same Download PDF

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Publication number
HK1040824A1
HK1040824A1 HK02102367A HK02102367A HK1040824A1 HK 1040824 A1 HK1040824 A1 HK 1040824A1 HK 02102367 A HK02102367 A HK 02102367A HK 02102367 A HK02102367 A HK 02102367A HK 1040824 A1 HK1040824 A1 HK 1040824A1
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Hong Kong
Prior art keywords
memory
layer
layers
substrate
diodes
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HK02102367A
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Chinese (zh)
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HK1040824B (en
Inventor
Gude Gudesen Hans
Nordal Per-Erik
I. Leistad Geirr
Carlsson Johan
Gustafsson Goran
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薄膜电子有限公司
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Application filed by 薄膜电子有限公司 filed Critical 薄膜电子有限公司
Publication of HK1040824A1 publication Critical patent/HK1040824A1/en
Publication of HK1040824B publication Critical patent/HK1040824B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02686—Pulsed laser beam
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/06—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using diode elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/10—ROM devices comprising bipolar components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H10D88/01—Manufacture or treatment
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/50—Forming devices by joining two substrates together, e.g. lamination techniques
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
    • H01L21/76894—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern using a laser, e.g. laser cutting, laser direct writing, laser repair
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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    • H10B—ELECTRONIC MEMORY DEVICES
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

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  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Read Only Memory (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

A scaleable integrated data processing device, particularly a microcomputer, comprises a processing unit with one or more processors and a storage unit with one or more memories. The data processing device is provided on a carrier substrate (S) and comprises mutually adjacent substantially parallel layers (P, M, MP) stacked up on each other, the processing unit and the storage unit being provided in one or more such layers and the separate layers formed with a selected number of processors and memories in selected combinations. In each layer are provided horizontal electrical conducting structures which constitute electrical internal connections in the layer and besides each layer comprises further electrical conducting structures which provide electrical connections to other layers and to the exterior of the data processing device. The integrated data processing device has a scaleable architecture, such that it in principle can be configured with an almost unlimited processor and memory capacity. Particularly can the data processing device implement various forms of scaleable parallel architectures integrated with optimal interconnectivity in three dimensions.

Description

Data storage and processing device and method of manufacturing the same
Technical Field
The invention relates to a data storage and processing device comprising ROM and/or WORM and/or REWRITABLE memory modules and data processing modules, wherein the device is provided on a substrate, wherein the storage and processing modules are provided as a single main layer or a plurality of stacked main layers above the substrate, wherein the memory modules and data processing modules in each main layer communicate with other main layers and circuits provided on or in the substrate via vias, surfaces or edge contacts, wherein the device comprises active circuits with transistors and/or diodes for operating the device. The invention also relates to a method of manufacturing a data storage and processing device comprising ROM and/or WORM and/or rewriteable memory modules and data processing modules, wherein the device is provided on a substrate, wherein the storage and processing modules are provided as a single main layer or a plurality of stacked main layers on top of the substrate, wherein the memory modules and data processing modules in each main layer communicate with the other main layers and circuits provided on or in the substrate via vias, surfaces or edge contacts, wherein the device comprises active elements in the form of transistors and/or diodes for operating the device, wherein the storage and data processing modules are provided by depositing their respective main layers and functional sub-layers in successive steps.
The invention relates in particular to data storage and processing devices, such as 3D scalable single-layer and multi-layer memory and data processing modules and devices, and more particularly to such devices based on ROM and/or WORM and/or REWRITABLR blocks that are addressed in a passive matrix design.
The present application claims priority from norwegian patent application NO982518 entitled "Scalable integrated data-processing device", which is assigned to the applicant of the present invention and is hereby incorporated by reference. Such a scalable integrated data processing device, in particular a microcomputer, comprises a processing unit with more than one processor and a memory unit with more than one memory. The data processing device is arranged on a carrier substrate and comprises mutually adjacent layers lying substantially parallel to each other. The processing unit and the memory unit are each provided in more than one such layer and/or in layers formed according to a selected number of processors and memories in a selected combination. Each layer is provided with lateral conductive structures that constitute internal electrical connections to the layer, and in addition to this, each layer includes conductive structures that provide electrical connections to other layers and to the exterior of the data processing device. These further electrical structures in one layer are provided on at least one lateral edge of the layer as electrical edge connections and/or preferably as longitudinal conductive structures constituting electrical connections in the cross-section of the layer and perpendicular to its plane for contacting the conductive structures of the other layer. Each layer may in particular be composed of a plurality of sublayers, each sublayer being composed of an organic thin-film material. Some of all layers or sublayers may also be composed of organic or inorganic thin film materials. Fig. 1 shows a preferred embodiment of a data processing device according to the priority application. It is advantageous here that the processor and the memory (the latter for example belonging to RAMs of the processor) are arranged in the same layer. A processor interface 3 with an I/O interface 8 is provided on the substrate S, on which processor interface 3 is a processing layer P1 with more than one processor. The processor interface 3 and the processing layer P1 may serve as the lowermost layer of the data processing device, adjacent to the substrate, and may be implemented in conventional technology, e.g. silicon technology. On the processed layer P1, a first memory layer M1 is provided, which layer may be configured with more than one RAMs 6 belonging to the processors 5 in the lower processed layer P1. However, in fig. 1, the isolation RAMs 6 in the memory layer M1 are particularly emphasized. On the other hand, it is shown how the memory in the memory layer M1 is directly connected to the underlying process layer P1 via a bus 7, which stacked structure allows a large number of such bus 7 to be provided by implementing a vertical conductive structure, while the structure of the upper layer allows a large number of such bus connections to be provided between the process layer P1 and the memory M1, in addition to short signal paths. It will be appreciated that such a juxtaposition on one surface would instead require a longer connection and therefore a longer transmission time. In addition, the data processing device shown comprises combined storage and processing layers MP1, MP2, MP3, which layers are provided with processors, which are connected to each other and to the processor interface 3 by means of the same processor bus 4. All combined storage and processing layers MP comprise more than one processor 5 and more than one memory RAMs 6. The combined storage and processing layer MP is provided with a memory interface 1 with an I/O interface 9 to external units, and the memory interface 1 is provided with a large number of memory layers M2, M3. These memory layers M2, M3, etc. are in turn connected to the memory interface 1 via memory buses, which are formed as longitudinal conductive structures 2 by the layers M2, M3.
Such an integrated data processing device has a scalable architecture and can, in principle, be constructed with an almost infinite processing and storage capacity. In particular such data processing devices may implement various scalable parallel architectures for three-dimensional optimal interconnect integration.
In addition to random access memory, the memory unit of such data processing devices may also include memory in the form of ROM, WORA or REWRITEABLE, or a combination thereof.
The present invention specifically discloses how to implement three-dimensional scalable single-layer and multi-layer memories and data processing modules using structures and processing methods suitable for, but not limited to, scalable integrated data processing devices of the type described above.
Background
The background art will be briefly described below.
Published international patent application WO95/09438(Zawracky & al, assigned to Kopin Corp.) discloses an integrated circuit device in the form of a multilayer structure, in particular a microprocessor divided into functional blocks, such as computation units, controllers, memory elements, etc., which are manufactured on the same or separate semiconductor wafers and then stacked. The functional blocks of the circuit device are divided into regions, one region being provided on the bulk chip and the remaining regions being provided on the upper base film with elements electrically connected through an intermediate isolation layer. The circuit device includes a bulk and a thin film semiconductor layer, and the circuit elements may be formed in a bulk inorganic semiconductor material or as a composite structure including a bulk silicon material and/or a thin film gallium arsenide. The layers of the circuit device may be fabricated by fabricating each circuit layer in separate wafers of thin film material, then transferring the layers onto a laminate and employing separate interconnects extending longitudinally through the spacer layer that separates each circuit layer in the laminate. In a preferred embodiment, the circuit device is configured as a volumetric processing device with separate microprocessor and RAM and with longitudinally connected internal separate laminated layers formed with metal vias extending through the layers. However, Zawracky et al do not give any indication of implementation of memory modules, for example of the ROM or WORM type, the envisaged structure of such circuit devices not being suitable for implementation of memory modules with passive matrix-addressable memory elements.
United states patent 5714768(Ovshinsky & al.) generally discloses a combination of a memory and a logic processing device, the memory being provided as more than one memory array deposited on the logic processing device. Each memory array is made up of memory cells arranged in a matrix and addressable by bit lines, word lines, which constitute the addressing electrodes of the memory cells disclosed as separate functional units.
In particular, the memory cells may be implemented using electrically phase-shifting memory materials based on chalcogenide-type inorganic compounds, which may be deposited using a low temperature deposition process.
Advanced DRAM typical die are currently availableAt 570mm21 gigabit (Gbit) module based on 0.18 micron processing technology on chip area. Although the process recipe can be significantly reduced (40%), conventional one-transistor DRAM cells typically require 10 λ2Where λ is the minimum feature size. However, the row and column decoders, drivers, sense amplifiers, and error correction logic cannot share the same silicon area and can occupy a significant percentage of the area of the DRAM die. More importantly, the existing DRAM designs to date have not proven to be scalable to 3D stack architectures. With their design, high density RAM is not yet suitable as ROM memory. Even under the most advanced lithographic hypothesis, conventional NOR-gate based ROMs require 70 λ2Nominal cell (although the processing recipe may be reduced) limits the density to < 108Bit/cm2. Higher densities can only be achieved by using dense metal designs (minimum metal spacing) associated with 3D integration. Despite the enormous economic potential that has led the electronics industry to develop a great deal for this, such technically and economically reliable devices have not yet become a reality.
3D data storage: attempts have been made to stack memory layers on top of each other to achieve high volume and area density using, for example, lift-off techniques for inorganic thin film circuits. However, the background art has resulted in designs that have proven to be too complex or costly for commercial applications. In us patent 5375085 "Three dimensional ferroelectric integrated circuit with out insulation layer between memory layers" to b.e. gnade et al, a layered passive addressed memory stack based on ferroelectric memory substances is disclosed. However, no specific information is given, in particular information about the processability of the multilevel, but only how to complete the memory device including all the required auxiliary active circuits. The applicant has filed several patent applications relating to the stacking of thin film memory layers and the like in connection with the present invention. These applications include norwegian patent applications NO973993, NO980781, NO982518, NO980602 and NO990867 mentioned above.
Compact metal deviceCounting: passive matrix addressing provides a response equivalent to about 4 λ2The density of the cell area of (a).
There are a number of patents which use passive matrix addressing for ROM devices, for example, U.S. Pat. No. US4099260 "Bipolar read-only-memory cell-isolating bit-lines" to d.n. lynes et al; U.S. Pat. No. 5,220,220,220,220 to k, g, bauge and P, b, mollier, "Matrix array of semiconducting elements"; U.S. Pat. No. 5,5170227 to M.Kaneko and K.Noguchi et al, "Mask ROMhaving monocrystailine silicon semiconductors (Mask ROM with single crystal silicon conductor)"; U.S. Pat. No. 5,5464989 to Mori et al, "Mask ROM using tunnel current detection to storage data and a method of manufacturing the same"; U.S. Pat. No. 5,5811337 to Wen, U.S. Pat. No. 5,583,37, "Method of manufacturing semiconductor read-only memory device for permanent storage of multilevel encoded data," and PCT application WO96/41381 to Gonzalez et al, "A stack/trench diode for use with a multilevel material in a nonvolatile memory cell. However, these approaches are clearly dependent on conventional silicon wafer processing techniques involving, for example, heat treatment, implantation and etching procedures that are incompatible with the present invention, i.e., low cost and arbitrary multi-level data storage as a whole.
The above-mentioned us patent 5375085 discloses devices based on passive matrix addressing, but is limited to the special case of ferroelectric memory materials. However, ferroelectric materials are given as examples where these patents have proven to be unsuitable for single passive matrix addressed memory schemes due to polarization loss in the unselected cells where repeated local switching is performed. Single and two transistor ferroelectric ram (feram) devices avoid this problem but are not useful for simple 3D scaling.
In US patent 5441907 "Process for manufacturing plug-in diode mask ROM" by H-c.sung and l.chen, a passive matrix addressed ROM is disclosed, in which binary data is encoded at each matrix crossing point by the presence or absence of diode contacts. However, the manufacturing method according to this patent involves several high temperature steps, including a final anneal, which prevents the multilayer structure and the use of low cost, low temperature compatible materials.
Thin-film ROM device: in GB patent GB2066566 "Amorphous diode and ROM or EEPROM device utilizing same" in s.h. holmberg and r.a. flash, a thin film memory device based on fluorine-containing Amorphous silicon is disclosed. In US patent US5272370 "Thin-film ROM device and the manufacture thereof", i.d. french, a ROM device based on Thin-film memory cells in a passive matrix addressing scheme is disclosed. It is emphasized that by providing a multi-layer structure in which each memory cell can be individually selected, multi-level (i.e., multi-bit) data storage is performed in each memory cell.
Disclosure of Invention
The main object of the present invention is to provide a structure and a technical solution that can introduce 3D (three-dimensional) memory structures in 2D (two-dimensional) dense bit cell patterns, easily using implementable low-cost manufacturing techniques.
It is a further object of the present invention to provide ROM, WORM and REWRITABLEs memory devices having short random access times, high data transfer rates and low power consumption. In this document, the term "rewrite" is used for memory cells where stored information can be interchanged with new information by erase/write or direct overwrite operations. This operation may be performed only once, or repeated, depending on the application.
It is a further object of the present invention to provide an integrated data storage and processing device in which the storage structures and device structures can be built in a very compact structure characterized by short and highly parallel interconnection paths in two and three dimensions.
Finally, it is a further object of the present invention to provide a method of manufacturing a data storage and processing device based on a low temperature compatible process and materials suitable for use in such a process.
The above objects and advantages are achieved by a data storage and processing device according to the invention, which is characterized in that each main layer of the storage module and/or the data processing module comprises a stack of functional sub-layers, each functional sub-layer implementing more than one specific circuit function, at least some active circuits being provided in each main layer, said at least some functional layers comprising a combination of organic thin-film materials and low-temperature-compatibly processed inorganic thin-film materials.
In a preferred embodiment of the device according to the invention at least one of the main layers comprises a memory module with passive matrix-addressable memory elements defined by memory material at intersections between electrodes of a first set of parallel electrodes on one surface of the memory material and a second set of parallel electrodes intersecting the first set of electrodes and on the opposite surface of the memory material, the memory elements being implemented as non-linear impedance elements at the intersections, each element being provided with a logical value given by an electrical impedance parameter of the memory material between the intersecting electrodes for improving its addressability. The nonlinear impedance element is preferably a rectifier diode composed of one or more of amorphous, polycrystalline, microcrystalline, bulk or process-defined single crystal forms of silicon, gallium arsenide and germanium, or organic semiconductor materials including molecules, oligomers or polymers or combinations thereof; or a transistor composed of one or more of amorphous, polycrystalline, microcrystalline, bulk or process-defined single crystal forms of silicon, gallium arsenide and germanium, or organic semiconductor materials including molecules, oligomers or polymers, or combinations thereof; or a thin film transistor composed of one of amorphous, polycrystalline, microcrystalline, bulk or process-defined single crystal forms of silicon, gallium arsenide and germanium, or an organic semiconductor material comprising molecules, oligomers or polymers or combinations thereof.
In another preferred embodiment of the device according to the invention, wherein more than one main layer is used, each main layer comprising more than one memory module, said memory modules are provided in the form of juxtaposed sections stacked above similar sections in the underlying main layer, so as to form more than two juxtaposed stacks on a common substrate, a portion of each section in each stack being connected to a portion of the substrate and being in electrical communication with said circuitry disposed thereon or therein.
In another preferred embodiment of the device according to the invention, wherein more than one main layer is used, each main layer comprising more than one memory module, said memory modules are provided in the form of juxtaposed segments stacked in a staggered manner on top of similar segments in the underlying main layer, so as to provide each memory module in a stack in staggered relationship to an adjacent module, a portion of each segment in each stack being connected to a portion of the substrate and being in electrical communication with said circuitry disposed thereon or therein.
In the device according to the invention, a plurality of through-going electrical conductors or vias providing power and signal connections between the main layers and the substrate are preferably distributed laterally in a staggered manner.
In the arrangement according to the invention at least one main layer is preferably a dual passive matrix-addressable memory module comprised in a separate sub-layer, one upper memory module and one lower memory module sharing a set of row or column electrodes.
In the device according to the invention, wherein more than one layer, preferably at least two of the main layers, are provided, comprises common row or column drive electronics and optionally readout electronics connected thereto by common wiring.
In various preferred different embodiments of the device according to the invention at least one of the memory modules is a masked ROM or a patterned ROM, or a WORM or comprises a rewriteable type memory cell.
According to the device of the invention, one or more memory modules comprise a combination of two different memory types in the form of ROM, WORM and REWRITABLEs integrated into at least one main layer in one stack.
In yet another preferred embodiment according to an embodiment of the present invention, at least a portion of the substrate underlying the one or more primary layers thereon comprises circuitry electrically connected to the one or more primary layers. The part of the substrate comprising said circuitry preferably comprises doped or undoped semiconductor material provided as bulk or as a thin film on a passive carrier, the semiconductor material being selected from one or more of the following materials: amorphous, polycrystalline, microcrystalline, bulk or process-defined single crystal forms of silicon, gallium arsenide and germanium, or organic semiconductor materials including molecules, oligomers or polymers, or combinations thereof.
The inorganic film material is preferably silicon, a silicon compound, a metal or a metal compound or a combination thereof.
The circuitry disposed on the substrate is preferably implemented using one or more of the following technologies, i.e., CMOS, NMOS or PMOS, and said circuitry disposed on or in the substrate preferably further includes one or more caches in the form of SRAM, DRAM and/or ferroelectric ram (feram).
Advantageously, said circuitry provided on or in the substrate may comprise, separately or in combination, a processor for detecting and correcting errors and defects in memory blocks in the main layer, and/or a processor for remapping defective memory modules in the main layer, and/or a processor for dynamically remapping memory modules in the main layer in order to optimize the performance and lifetime of said modules.
In the device according to the invention, the circuits in the main layers are preferably all realized in thin-film technology.
The above objects and advantages are also achieved according to the invention by a method of manufacturing a data storage and processing device, said method being characterized in that said layers are deposited and processed under thermal conditions avoiding subjecting an already deposited and processed underlying layer to static temperatures at values exceeding the temperature range of 150-, conventional semiconductor layer processing selected from, but not limited to, photolithography, wet etching, dry etching including reactive ion or plasma etching, chemical mechanical polishing, ion implantation, and/or combinations thereof, using a transient heat treatment using a pulsed laser or particle beam to crystallize the deposited amorphous film, refine the grains of the deposited film, introduce and activate dopants thereon; the molecular, oligomeric or polymeric material for each layer is deposited using one of the following processes, namely solvent techniques, evaporation, sputtering, or other vacuum techniques, or thin film transfer techniques, or a combination thereof.
In a preferred embodiment according to the present invention, thin film silicon circuits and transistors are fabricated using low temperature compatible processes using laser induced crystallization of thin film transistors and dopant activation.
To implement the memory module as a matrix-addressable memory with isolated diodes, this can be done in other preferred embodiments of the inventive method by directly depositing amorphous, microcrystalline or polycrystalline n-and p-type silicon or germanium films and directly depositing oligomeric or polymeric semiconducting organic films to form isolated diodes in a longitudinal or planar configuration; the isolated diode is formed by utilizing laser-induced melting and solidification of n-and p-type amorphous or microcrystalline inorganic semiconductor materials deposited directly on the underlying low temperature compatible layer. In the latter case, it is preferred to prevent the underlayer from reacting with the molten semiconductor material during laser-induced crystallization by providing a thin film diffusion barrier layer, and it is preferred to design the reaction between the molten semiconductor material and the underlayer to form a stable conductive compound such as a silicide.
To realize the memory module as a matrix-addressable memory with isolated diodes, according to a further preferred embodiment of the method of the invention the isolated diodes are formed by laser-induced melting and solidification of the deposited amorphous or microcrystalline inorganic film and by forming the pn-junction of the diode by means of compensated doping, said pn-junction being formed by a layer deposited on the underlying metallization layer or by so-called autodoping by means of alloying elements in the passive matrix metal layer; or by forming a schottky barrier diode using laser-induced melting and solidification of the deposited amorphous or microcrystalline inorganic film and using the underlying metal structure or a compound formed by reaction with the underlying metal structure, thereby forming an isolation diode.
In a further preferred embodiment according to the invention, the laser induced crystallization in the explosive crystallization zone is limited, whereupon only a momentary melting of the film surface is required, a self-generating liquid film is formed to crystallize the rest of the crystallized film, an isolation structure serving as a longitudinal isolation diode is formed from a high resistance or anisotropic contact material, and a non-conductive interlayer dielectric is formed in a horizontal direction with respect to the layers.
In the latter case, the isolation diode and the non-conductive interlayer dielectric are formed by chemical or thermally induced modification of the contact material, which may be achieved by self-doping of high-resistance amorphous silicon and laser-induced crystallization of high-resistance amorphous silicon.
Finally, in yet another preferred embodiment according to the present invention, a process is utilized in which the absorbed laser energy is modulated by the underlying layer or structure, modulated by the antireflective or reflective film, utilizing a self-alignment process that limits the formation of diode junctions to only locally limited regions, the diodes are formed in locally confined areas, such as the intersections of the matrix, while providing lateral isolation between the diodes, by using the bottom layer or underlying structure as a dopant source for forming the diode junction by explosive crystallization, or selective chemical or physical vapor deposition of amorphous or microcrystalline films by surface modification of the interlayer dielectric surface, controlling the interlayer dielectric surface, thereby confining the nuclei to the metal region during laser induced crystallization and the memory module is implemented as a matrix-addressable memory with isolated diodes.
In the method according to the invention it is quite advantageous to isolate the functional sub-layers by means of a planarized dielectric layer formed by spin coating or other deposition methods, said dielectric layer being made of an oligomer, polymer or inorganic material, and by means of chemical mechanical polishing, and it is also quite advantageous to initiate the induced crystallisation by means of a direct energy source other than a laser, including pulsed ions and electron beams.
The objects of the invention are achieved by using new materials and processes that can create devices using new structures, both two-dimensional and three-dimensional. The outstanding characteristics related to it are:
1) the memory module is manufactured using low temperature compatible processes and low temperature processing techniques of materials, i.e. polymers or polycrystalline or microcrystalline or amorphous silicon. Low temperature compatibility in this document refers to processes that do not exceed a static temperature compatible with polymer based substrates, or to transient heating processes that are limited to a time sufficiently shortened to be similarly compatible. As an example: in laser crystallization of thin film silicon, the temperature of the uppermost layer is actually quite high, but due to the short heat pulse and the total energy density, heat is quickly redistributed in the support layer. Except for a certain depth, the latter does not reach high temperatures due to calorimetric effects. For simplicity, the above-described low temperature compatible processes and materials may be referred to hereinafter as "low temperature processing techniques" and "low temperature materials".
2) Low temperature processing techniques can build memory modules in one or many higher levels without damaging underlying circuitry or other memory layers that are stacked. This applies both to devices based on conventional monocrystalline silicon substrates and to plastic substrates with thin-film active circuits. (in the latter case, damage to the plastic by short durations of the heat pulse typically used in laser recrystallization can be prevented even at temperatures where sustained thermal loading can cause damage).
3) The following advantageous effects can be obtained from 1) and 2):
-a plurality of layers can be stacked, resulting in:
high volumetric data density, and
high density, short vertical interconnects, yielding high data output:
due to the short distance, low capacitive and resistive interconnects are formed
High parallelism of the width of the larger letter (many longitudinal connections)
Such regions are employed, as required, in sub-layer single crystals or high performance polycrystalline, amorphous or microcrystalline layers underneath memory modules requiring high speed active circuitry. Example (c):
-an integrated SRAM data cache
Driver and interface electronics
On-board error detection and correction of block orientation circuits to improve reliability of memory layers
Due to passive matrix addressing, each layer has a high areal data density, and the driver circuit layers are arbitrarily arranged below and/or above and within the same layer.
Drawings
The present invention will be discussed in more detail below in connection with illustrative embodiments and the attached drawings, wherein:
figure 1 shows an embodiment of a scalable integrated data processing device in which the invention is applicable,
figure 2 shows a schematic layout of a 1GB ROM device according to one embodiment of the present invention,
figure 3 is a layout of row/column addressing lines of a pair of memory planes of the ROM of figure 2,
figure 4 is a staggered stack design of the ROM storage planes in figure 2,
figure 5 is a combination of several of the staggered stack designs shown in figure 4 and a multi-sector staggered stack design of the ROM storage plane shown in figure 2,
figure 6 is a staggered longitudinal or lateral path for connecting and connecting the latter to underlying circuitry across or across the storage plane,
figure 7 is a graph of access time versus memory block segment,
figure 8 is a graph of average addressing power requirement versus average block (read) addressing size,
figure 9 is a vertical diode in the "on" and "off elements of the ROM,
fig. 10 is the vertical diode shown in fig. 9 but fabricated using a self-alignment and planarization process.
Detailed Description
The preferred design of the present invention is implemented as a layered structure built on a single crystalline silicon substrate containing all active electronic circuitry. Which communicates with one or more upper storage layers through vias. Each memory layer contains a low temperature processed diode ROM and/or WORM and/or REWRITABLEs array where high areal bit density is achieved by using passive matrix addressing. Each memory layer is self-contained as a self-consistent entity, without the need for high temperature or chemically damaging processes that can damage the underlying layers during fabrication. The memory module can be positioned above the active electronic circuitry in the substrate, saving substrate real estate and providing a short-circuited electronic path between the active circuitry and the memory module. In addition, by adding more memory layers on the first layer, a 3D stacked structure having a very high volume bit density is formed, and the memory capacity can be enlarged.
The above-described device can adapt itself to "post-processing" of a memory module, where all circuits on a monocrystalline silicon substrate are first prepared using conventional silicon-based processing techniques. The deposition of the memory layer may then be performed in a separate apparatus, for example, if it is desired to employ materials and processes in this step that may present contamination issues for silicon processing.
The driver and readout circuitry are preferably fabricated in a standard CMOS process on a single crystal silicon substrate to reduce cost and achieve the required high data transfer rates. Then, on the last metallization layer coupled to the underlying driver by vias, a ROM/WORM/REWRITABLE array is built. The diodes may be inorganic, such as amorphous silicon, polycrystalline silicon or microcrystalline silicon, or they may be based on organic materials, such as conjugated polymers or oligomers. Passive matrix addressing designs and 3D architectures employing low temperature diodes can provide enhanced dynamic memory functionality at only marginal cost, on all existing ROM/WORM/rewrite designs, on the underlying CMOS circuitry.
The longitudinal interconnections may take many forms: one is a through-via conductor, where the short distance and large area available for stacking ideas allows the high data transfer speed and flexible structure described above, and relates to via staggering designs such as those described in more detail below in connection with the preferred embodiments. Longitudinal interconnections may also be made through the electrical conductors in each layer described above leading to the edge of that layer where they are exposed and may be electrically connected to similarly exposed conductors in other layers. This can be made, for example, by a step-like extension of the lower layer edge. Another type of vertical interconnect relies on contactless (no current) communication through these layers. This is possible due to capacitive, inductive or optical coupling between the layered structures, i.e. the circuits in the different layers.
For clarity and specificity, a detailed description of the invention is provided below in terms of a preferred embodiment of a cryogenically processed polysilicon diode ROM array having a stack of four bilayers. The design can be easily extended to WORM memory applications, using induced explosive crystallization of amorphous diodes or conduction modulation of interlayer organic films, and to REWRITABLEs memories by introducing highly functional memory materials in the memory matrix; to other patent applications belonging to the applicant mentioned above in this document.
A schematic layer layout for a 1 Gigabit (GB) setup according to the present invention is shown in fig. 2. The row demultiplexer and driver, the sense amplifier and the column multiplexer are implemented as a conventional VLSI CMOS single crystal chip forming the basis of the structure. All diode ROM layers are fabricated on the final dielectric deposition and CMP planarization layers after completion of the VLSI circuits.
The details of VLSI CMOS circuits are not discussed except as they relate specifically to the storage plane. The drivers and sense amplifiers are essentially the same as for a conventional DRAM module, and the design can be handled almost as is. The row drive inverters must be resized to accommodate the high capacity of the diode ROM structure and the sense amplifiers need to be modified to reduce the charge rate.
The memory plane is a laminated layer structure, each ROM layer consisting of simple row/column lines possibly cross-connected by a longitudinal diode structure, a binary 0 (or 1) indicating the presence of the diode. Eight planes of memory, 10 for each lead-in9Bits, the gigabit module needs to be generated. To reduce the total number of mask levels, the row lines are shared between the two memory planes, reducing speed, but simplifying overall fabrication.
Fig. 3 shows an electrical schematic of each pair of storage planes. After latching the Row Address (RAS), the last inverter drives one row line to ground. Current flows from each column line (the two column pairs are symmetric) through the diode and the voltage drop on the column line is read out in parallel with all column lines. After read-out, the row and column are restored to VDDPotential, the column lines return to their quiescent potentials (ground and V)DD-0.7). The power and speed penalty of this diode-defined (compared to NOR MOS designs) memory is more shifted due to the increased density allowed by the row/column dense metal crossbar layout. In a block oriented data access device, driving a single row of inverters provides data reading of two columns. Although the speed of each row access is limited by the charging of the capacitor, the overall data transfer rate is "scaled up" by twice the column length. Such asAs discussed further below, the random data access time may also be adjusted by appropriate sections of memory, some of which are described in more detail below in connection with FIG. 5.
Independent of this sector, the fig. 3D memory layer layout requires stacked memory planes staggered on the Si die to provide area for row drivers, sense amplifiers, and peripheral circuitry. Fig. 4 shows such a staggered stack design, where the storage plane is represented by light grey and the single crystal silicon block is defined by dark grey. Each pair of storage planes is offset both horizontally and vertically to provide a single crystal silicon real floor for the row drivers (large inverters) and sense amplifiers. All row drivers are fed from a common row decoder (with the last plane pair selecting NAND) logic circuits. The figures are not drawn to scale and in particular the ratio of area required for the row drivers and sense amplifiers is reduced roughly by the root mean square of the memory size. Sense amplifiers, assume that a 4096 x 4096 sector will account for less than 10% of the die real estate. For a 256 megabit array, this area is less than 1% of the total die area.
In stacked designs where the memory array is on top of a single crystalline logic circuit, a significant proportion of the die is unused. A proportion of this is needed for the bad cell mapping and error correction logic, but the rest should constitute the SRAM data cache in order to make multiple accesses rock as small as the storage plane. The initial power consumption that occurs during memory access-reducing the amount needed to meet cache memory requirements-has the potential to dynamically reduce the overall power even in random access mode is considered. For ram accesses, the cache still needs to provide some look-ahead reads from memory to compensate for the power and rate limitations of direct access. For high block oriented memory applications, the cache memory becomes lower than a critical value, and instead the region is dedicated to higher level error correction algorithms to improve die yield and reduce cost.
An optimized memory structure for an 8-plane 1 gigabit plane would not be a 32,768 x 32,768 array due to capacitive loading from the diode elements. The row line capacitance (from the dielectric and diode elements) and the column line capacitance increase linearly with array size. The row charge and diode current transfer set the power consumption and the column row capacitance directly determines the charge accumulation time required by the sense amplifier. To increase speed, the 1 gigabit memory block can be segmented as in FIG. 5, where the stacked design shown in FIG. 4 is used to incorporate several planes of readout circuitry stacked alternately between isolated blocks, at the expense of increasing the real estate of the driver electronics. But this cost is not significant since the larger area of the Si substrate is unused in this design (the rest belonging to the cache). The optimized section depends strongly on the application, in particular the average size of the memory block accesses. In general, smaller sections are important in terms of power consumption as block sizes decrease. The minimum random access speed can also be dynamically increased by increasing the number of memory sectors. (these issues are considered further below.)
It is also possible to implement a multi-array block using only a pair of sense amplifiers using a common column path with diode isolation between the two planes. However, this design suffers from a severe speed penalty due to the time required to turn on the planar isolation diodes. In the future, where active MOS isolation transistors may be implemented on the storage plane, certain applications may employ a single sense amplifier design. But is not physically constrained by the underlying substrate so die size increase is minimal.
To achieve the desired data transfer speed, all sense amplifiers must be latched during the data strobe, providing a block transfer to the column decode logic. This naturally occurs in the SRAM cache as part of the design. Assuming a CD-ROM based replacement, most of the data accesses are resolved from the column latch cache, there is no additional row data strobe.
The limitations caused by dense vias between the device level and the upper memory block may be involved, but since the vias may be staggered, meet the fixed design rules of conventional vias, and enable dense metal wiring density for memory arrays, this is not a problem. A simple staggered arrangement of the vias, as shown in fig. 6, illustrates one possible solution. Vias are staggered on (or across) the die to strictly meet the 2 x 2 λ via size, 1 λ metal on all sides of the via, 3 λ minimum via pitch, yet maintain a reasonably tight metal routing within the memory array itself. The vias are typically spaced apart rather than as shown to accommodate the spacing actually required by the sense amplifiers or row drivers. In this layout, one line in N is lost. To maintain consistent metal density and optimum processing (requiring the metal spacing to be pushed out of the random logic design rules) and replace the lost lines with dummy metal lines (no contacts). The row/column density reduction caused by this staggering method is introduced into the calculations given by the design analysis below. Although shown for a 2 lambda via, it is apparent that any size via for connecting the memory array to metal 1 or 2 may be extended.
With the general layout defined above, the desired die size can now be determined. The memory plane density is limited by the metal wiring pitch of the memory, and the overall density of the memory is set. The economical design requires metal spacing based on minimum via overlap and metal-to-metal spacing. The overall die size is approximately 20% larger than the memory plane itself (for staggered layouts and peripheral drivers). However, the metal need not be limited to random logic limits. Line widths and spacings can be greatly reduced as a result of the development to very dense metal arrays with uniform spacing and density. Photolithography and etching can be optimized for dense metal spacing, allowing poly or metal 1 line widths to be used even in the upper layers, as long as random routing on the memory plane can be minimized. This does not apply to vias, but as mentioned above, they can be manufactured within the limits of the design rules.
Furthermore, the simple design of the memory cell does not require via metal overlap within the memory cell, and lithographic misalignment can reduce the contact area (one axis), but the subsequent interlayer dielectric will passivate the exposed diode elements. These two process improvements allow for maximum metal spacing, resulting in 4 λ2Where λ is approximately the metal width/spacing.
Table 1 compares well three techniques on a 0.35, 0.25 and 0.18 micron lithography basis (design rules taken from TSMC and MOSIS scalable design). The following table summarizes the results of a 1GB design assuming design requirements for 512-bit average block transmission and 1000MB/s total data transmission. The sector is of a suggested size to balance access time, with a maximum requirement of 100 ns.
TABLE 1
0.35 micron 0.25 micron 0.18 micron
Via size/spacing 0.50/0.45 0.36/0.38 0.24/0.28
Metal width/spacing 0.60/0.50 0.40/0.40 0.28/0.28
Metal via overlap 0.20 0.15 0.10
Dense metal (cell) width 0.40 0.30 0.24
Dense metal (unit) spacing 0.40 0.30 0.24
Minimum unit size 0.8X 0.8 micron 0.6X 0.6 micron 0.48X 0.48 μm
Area of cell 0.64 square micron 0.36 square micron 0.23 square micron
Storage density/layer 0.156Gb/cm2 0.278Gb/cm2 0.435Gb/cm2
Optimization segment (#) 16 4 4
Die area 742mm2 402mm2 257mm2
Random access time 52ns 76ns 68ns
Power consumption (array) 25mW 22mW 9mW
1GB memory-with die sizes (< 500 mm) within reasonable limits-is easily achieved with existing 0.25 micron technology2). For a 0.35 micron design rule, the individual chip size may be too large for fabrication, but a 0.5GB array is reasonable. With respect to the 0.35 micron technology only caveat is that the upper level metal planarization must be performed as a CMP process to provide the required flatness of the dense metal on the upper layer.
Memory speed and power consumption are now considered relative to design and operating parameters.
Designing parameters: for the purpose of this design example, the following approximation is used:
the row and column line parasitic capacitances are taken to be equal to the direct capacitance
SiO with an interlayer dielectric of 300nm2Equivalent value
The conductivity of the metal wire is 0.07 omega/□
The minimum threshold of the sense amplifier is 10mV
The diode transconductance is 10 for 1V forward bias3A/cm2
The diode is a side junction at zero bias, with a depletion layer of 400nmWidth (10)17Doping)
Data transmission rate: after the column latches are full, the desired continuous data transfer rate of 1 gigabit/s is easily achieved. Even in 4096 sectors, 8192 latches are satisfied per row access, with an actual data access time of sub-1 microsecond. However, this assumes that the data transmission is highly corrected and that all 8192 column bits are useful. Since this is not normal, power is lost.
Access time: the instantaneous data access speed (from RAS to data active for CAS latch) is determined by the charging time of the column capacitor through the diode. This is a more difficult parameter to implement in a diode based ROM cell. This time is a complex function of array size (sector), diode conductance, diode capacitance (dominant), row driver line resistance, and sense amplifier minimum voltage sensitivity.
The access time is a row charge time (R)rowCrow) Column readout integration time (C) with respect to minimum specific voltage swingcolΔV/Idiode) And the sum of the estimates of the random logic delays for row/column addressing.
As can be seen from the graph of fig. 7, the access speed is only slightly related to the lithography rules, but is very related to the sector size. The round trips over 16 sectors of the array are reduced.
Power consumption: the initial design parameter that affects power consumption is the average size of the block transferred at each read, the power required by the charge and sense amplifiers to average out a large number of read cycles as long as the read needs can be met by the row read cache. But if the accesses become random, each access requires a row charge cycle and the power requirements will increase significantly. The graph of fig. 8 shows the estimated power requirement as a function of the average block read size and the continuous data transfer rate of 1000 GB/s. For this purpose, a 0.25 micron design divided into four segments was used. Note that the scale is logarithmic. As long as the average block size remains above a few hundred, power consumption is determined by the intrinsic transmission. As the size decreases, additional row reads are required, with the opposite power rise due to the block size.
Manufacturing a storage plane: for example, a multi-planar implementation of a ROM memory according to the present invention requires superior processing to maintain a planar structure (more than 12 metal layers) with minimal topographic growth. The process must be compatible with the metal lines exposed on the row/column vias-effectively limiting the process to 250 ℃. The diode is preferably fabricated also self-aligned to the contact via in order to reduce the number of masks.
Two convenient approaches will be described below based on inorganic semiconducting materials:
selective deposition of microcrystalline Si over a metal/Si seed layer by via (or blanket deposition and CMP etching)
Explosive crystallization of felted a-Si-leaving high resistivity a-Si for planarization-using a via medium with high modulation of laser intensity
4f2The storage density requires isolated diodes that will be more fully processed and contacted in a vertical configuration-as opposed to the conventional planar configuration as per the current art. The isolation diodes in a ROM or impedance controlled RAM device are fabricated directly on the row/column metal as shown in fig. 9. For a ROM, the memory cell on the left side is "on" while the memory cell on the right side remains "off. In the simplest structure, there is or is not a difference between memory cells in terms of the division of the interlayer medium patterned on the diode material. Several specific fabrication techniques will be discussed below, starting from the most sophisticated techniques that utilize the present fabrication techniques, to processes that involve only more sophistication.
The fabrication of vertical diodes using direct energy processing techniques will be discussed below in conjunction with specific processing examples.
EXAMPLE A fabrication of a diode directly on metallization Using a Polymer/Low temperature substrate
Common to all fabrication strategies is the formation of longitudinal p-n junction diodes directly on the dense metal line arrays that make up the row or column lines of the memory. Transient thermal processing, particularly optical pulses or ion beams, is the preferred method of fabrication due to its compatibility with other low temperature materials used for WORM/RAM applications. The method comprises the following steps:
i. a metal film for the bottom matrix of rows/columns is deposited. The selection of the underlying metal depends in part on the following method, discussed below. The metal film may be a multilayer structure composed of a highly conductive underlayer (Al) and an intermediate barrier layer (e.g., tungsten) in contact with Si.
Depositing thin amorphous donor (n-type) doped silicon, for example, by sputtering, e-beam evaporation, or PECVD and the like.
in-situ depositing a second layer consisting of acceptor (p-type) doped silicon or germanium.
Laser-induced crystallization of the amorphous silicon film to form a polycrystalline pn-junction diode. The energy density is selected to achieve sufficient or nearly sufficient melting of the silicon film to form a core from the metal layer. Larger grain (> 50nm) polycrystalline diodes will then be produced with junctions near the original p-n deposition boundary.
v. masking and etching of lower level row lines, followed by an interlayer dielectric (SiO)2) By conformal deposition.
Patterning the contact level to define "on" and "off" memory cells.
Column metal deposition and patterning/etching.
Example B-improvement with explosive crystallization
The flux required for crystallization in (iv) above is determined by the film thickness. Crystallization may be alternated by explosive crystallization (m.o. thompson.phys.rev.lett.52: 2360(1984)) which requires only minimal melting surface formation. The difference in enthalpy between amorphous and crystalline will cause the melt to pass through the film with minimal net thermal impact on the underlying metal layer. The resulting diode layer is a mixed amorphous/polycrystalline phase, but maintains sufficient current density (100A/cm) for memory isolation applications2)。
Example C-improvement relating to the use of Schottky diodes
The process can be carried out without depositing the p and n type films for the junction diode, and the schottky barrier diode can be fabricated directly from the lower metal film. Such improvements include deposition of only n-type films, crystallization and formation of schottky barriers with silicide phases formed either directly from the metal (minimal liquid interaction) or by local melting of the metal contacts, which is best suited for explosive crystallization to reduce the thermal energy dissipated in the metal layer.
Example D-improvement relating to auto-doping from Metal contacts
Electrically active dopants can be introduced into the metal film, avoiding the need for n-and p-type Si isolation films (steps ii and iii above). A thin coating of arsenic or boron or an alloy containing silicon or arsenic on a tungsten metallization may provide compensation doping to the single film deposition, local melting and introduction of impurities from the metal or metal coating followed by liquid phase diffusion and possibly segregation during crystallization to form a p-n junction. The position of the interface is controlled by the crystallization dynamics and can be controlled by the change in flow rate, again primarily in the explosive crystallization zone.
Example E-improvements relating to the use of germanium
All of the above methods are essentially the same for germanium as for silicon. Although germanium poly diodes may exhibit higher leakage, this can be compensated by lowering the overall liquid process temperature by 450K. Although the instantaneously molten phase need not be said to be very reactive.
Example F-Metal selection
In addition to the improvements disclosed in example C above, the main requirement for the metal is to reduce the interaction with the molten semiconductor during solidification. Candidate metals include refractory metals such as tantalum, tungsten and platinum, intermediate transient metals including Pd, Mo, Ni, Co or Cr, current diffusion barriers such as TiN, terminating silicide phases such as NiSi2. All elemental metals form stable silicide phases, which are expected to react moderately with liquid Si or Ge. This reaction can be mitigated by using a stable silicide, however, since the silicide is alsoIs a suitable conductor so forming thin silicide is not a problem. For an improvement like example C, a well defined silicide needs to be formed.
For self-alignment and planarization of the diode, some processing technique may be introduced.
The process described in example a above is a conventional semiconductor processing technique involving the precise overlay of the contact mask with the underlying row metal. In addition, the etching process produces increased roughness topography that must be planarized for stacked 3D integration. However, the conductivity between polycrystalline and amorphous phases 103-105The difference in (2) can be used to develop a self-aligned diode definition pattern that can also address planarization issues. The main improvement of this mode is to leave amorphous material in the inner diode region and to reduce the structure height. The process flow in this case is as follows:
i. metal for the row lines is deposited and patterned. The metal is sufficiently etched and planarized with a dielectric between the metal lines.
ii. The n-and p-type amorphous films (or monolayers modified by the above) are deposited uniformly.
iii, depositing a contact medium plus a thin refractory metal layer (Cr or Al). The pattern etch leaves a via where the diode will be formed.
iv, laser irradiation through the patterned film. Energy is absorbed sufficiently only in the path, stimulating crystallization of the silicon (explosive or fully melted).
v, depositing column line metal. (the refractory film, if a compatible metal, need not be removed prior to deposition-the etching can be done simultaneously.
vi, dielectric deposition and planarization.
In this process, the alignment of the column metal to the vias can be relaxed. Since the underlying metal is fully coated with amorphous silicon, misalignment does not cause column-to-row shorting. The conductivity of the amorphous silicon must be kept relatively low so that cross talk between row lines is not significant. This effect is readily achieved with a very lightly doped a-Si film with the diode formed by introducing dopants from the underlying metal (example D above). For the resulting diode structure, reference may be made to fig. 10.
In another improvement, a long wavelength laser is used to excite the crystal, and a short wavelength laser (excimer laser) is used as the excitation source. At 1.06 microns (Nd: YAG wavelength), the amorphous silicon is sufficiently transparent that energy can be transmitted through the amorphous silicon film and absorbed only by the underlying metal film. This metal then initiates explosive crystallization or (melting to a sufficient degree). The advantage of this mode is that the diodes are formed only in the row metal regions.
Finally, instead of patterning the wafer, a patterned diode array can be patterned (imaged through a mask) using a patterned laser beam. This is limited to larger feature sizes (1 micron), but several photolithography steps are avoided.
The present invention is not intended to be limited to ROM devices but may implement various memory and data processing devices and modules as described above. A brief description of alternative preferred embodiments is given below.
The basic design described above is also applicable to WORM applications. This may start with a passive matrix array where all cross-points behave as rectifier diodes at the beginning. Writing to a given cross-point is accomplished by creating an open circuit, i.e., breaking the forward conduction of the diode.
In one embodiment, the matrix array is fabricated by sandwiching a conjugated polymer between two sets of parallel electrodes that form a passive matrix, the electrode and interlayer materials being selected to spontaneously establish a rectifying diode at each intersection. The physical mechanisms involved are well studied and described in this technical literature. Writing to a given intersection is accomplished using one of several methods. The most intuitive one, but not the only one, is that thermal damage is produced by a short circuit, but a strong current pulse passes through the polymer at the intersection, causing a locally controlled decrease in conductivity, or an open circuit. Suitable materials and geometries are described in the following patent applications under the control of the applicant, norwegian patent applications NO972803 and NO973390 and applications derived therefrom.
Although the preferred embodiment discussed in section 4 above performs approximately analog sensing at low bias, writing still requires higher current and a different pulse protocol. Therefore, the thermal profile of the energy dissipation at the intersection must be closely controlled in order to achieve the desired thermal history at the diode junction and to define the region of current induced impedance change (e.g., thermal damage) to the intersection being written. These aspects show that the electronic circuit complexity of WORM memories is higher compared to ROM types, which together with the higher current requirements during writing results in a certain degree of low bit density. On the other hand, the all-electronic writing process shows that the basic processing steps involved in manufacturing, such as masked ROMs, are avoided.
It is readily understood by those skilled in the art that the above basic design opens the way to integrating ROM, WORM and REWRITABLEs arrays in a single device or in separate ROM, WORM and REWRITABLEs layers in the same layer or as one stack. This type of combined memory is particularly proposed among the many possible consequences that may result therefrom.
The self-detection yield is improved: the ROM self test program is effective to identify faults in memory as part of the post-manufacturing test and qualification procedure. The results are stored in WORM and linked to instructions generated by ROM, causing the failure in the storage device to be bypassed or corrected. This may be done in a pattern that is obvious to the user rather than potential. In this way, manufacturing yields may be improved.
The above-described direct extension of devices, which may or may not incorporate different types of memory, includes the processing capabilities for 2 and 3 dimensional structures. Therefore, a distributed processor (including but not limited to a microprocessor) that is fast and has direct access to a given memory in close physical proximity will provide speed and flexibility not achievable with processor/microprocessor architectures based on conventional silicon wafer technology. For a more complete description of these relevant aspects, in particular the integrated memory and processing architecture of a scalable architecture, reference may be made to norwegian patent application NO982518, from which this application takes precedence, generally to computer files.
It is clear that the invention above provides an ideal and specific embodiment extension by adopting new structural solutions and by adopting materials and processes that facilitate the implementation of high density 2-and 3-dimensional structures.

Claims (39)

1. A data storage and processing device comprising a ROM and/or write-once read-many and/or rewritable memory module and a data processing module, wherein the device is provided on a substrate, wherein the storage and processing module is provided as a single main layer or a plurality of stacked main layers on top of the substrate, wherein the memory module and the data processing module in each main layer communicate with the other main layers and circuits provided on or in the substrate via vias, surface or edge contacts, wherein the device comprises active circuits with transistors and/or diodes for operation of the device, characterized in that each main layer of the memory module and/or the data processing module comprises a stack of functional sub-layers, each functional sub-layer implementing one or more specific circuit functions, at least some of said active circuits being provided in a main layer, and at least some of the functional layers comprising a combination of an organic thin film material and a low temperature compatible processed inorganic thin film material.
2. A device according to claim 1, characterized in that at least one of the main layers comprises a memory module with passive matrix-addressable memory elements defined by memory material at the intersections between electrodes of a first set of parallel electrodes on one surface of the memory material and a second set of parallel electrodes on the opposite surface of the memory material intersecting the first set of electrodes, the memory elements being implemented as non-linear impedance elements at the intersections, each element having a logical value given by the electrical impedance parameter of the memory material between the intersecting electrodes for improving its addressability.
3. A device according to claim 2, characterized in that the non-linear impedance element is a rectifying diode composed of a material of amorphous, polycrystalline, microcrystalline, bulk or process-defined monocrystalline form of silicon, gallium arsenide and germanium, or an organic semiconductor material comprising molecules, oligomers or polymers or a combination thereof.
4. A device according to claim 2, characterized in that the non-linear impedance element is a thin film transistor of a material, i.e. silicon, gallium arsenide and germanium in amorphous, polycrystalline, microcrystalline, bulk or process defined single crystal form, or an organic semiconductor material comprising molecules, oligomers or polymers or a combination thereof.
5. The device of claim 1 wherein more than one primary layer is provided, characterized in that each primary layer comprises more than one memory module, said memory modules being provided in the form of side-by-side sections stacked above similar sections in the underlying primary layer to form two or more side-by-side stacks stacked on a common substrate, a portion of each section in each stack being connected to a portion of the substrate and being in electrical communication with said circuitry disposed thereon or therein.
6. The apparatus of claim 1 wherein more than one primary layer is provided, wherein each primary layer comprises more than one memory module, said memory modules being provided in a staggered formation in side-by-side sections stacked above like sections in the underlying primary layer, so as to provide each memory module in a stack in a staggered relationship with adjacent modules, a portion of each section in each stack being connected to a portion of the substrate and in electrical communication with said circuitry disposed thereon or therein.
7. A device according to claim 1, characterized in that a plurality of through-going electrical conductors or vias providing power and signal connections between the main layers and the substrate are distributed laterally in a staggered manner.
8. A device according to claim 2, characterized in that at least one main layer comprises dual passive matrix-addressable memory modules in separate sub-layers, one upper memory module and one lower memory module sharing a set of row or column electrodes.
9. A device according to claim 2, wherein more than one layer is provided, characterized in that at least two of the main layers comprise common row or column drive electronics and optionally read-out electronics connected thereto by common wiring.
10. The apparatus of claim 1, wherein at least one of the memory modules is a mask ROM or a patterned ROM.
11. The apparatus of claim 1, wherein at least one of the memory modules is of a write-once read-many type.
12. The apparatus of claim 1, wherein at least one of the memory modules comprises a rewritable memory cell.
13. The apparatus of claim 1, wherein the one or more memory modules comprise a combination of two different memory types in the form of ROM, write-once read-many, and rewritable integrated into at least one main layer in a stack.
14. The device of claim 1, wherein at least a portion of the substrate underlying the one or more primary layers thereon comprises circuitry electrically connected to the one or more primary layers.
15. A device according to claim 14, characterized in that the part of the substrate comprising said circuit contains a doped or undoped semiconductor material provided in bulk or as a thin film on a passive carrier, the semiconductor material being selected from one or more of the following materials, i.e. silicon, gallium arsenide and germanium in amorphous, polycrystalline, microcrystalline, bulk or process-defined monocrystalline form, or an organic semiconductor material comprising molecules, oligomers or polymers or combinations thereof.
16. A device according to claim 14, characterized in that the circuitry provided on or in the substrate is implemented using one or more of the following technologies, CMOS, NMOS or PMOS.
17. Apparatus according to claim 14, wherein said circuitry provided on or in the substrate further comprises one or more cache memories in the form of SRAM, DRAM and/or ferroelectric ram (feram).
18. The apparatus of claim 14, wherein said circuitry disposed on or in the substrate includes a processor for detecting and correcting errors and defects in the memory modules in the main layer.
19. Apparatus according to claim 14, wherein said circuitry disposed on or in the substrate includes a processor for remapping defective memory modules in the main layer.
20. Apparatus according to claim 14, wherein said circuitry disposed on or in the substrate includes a processor for dynamically remapping memory modules in the main layer to optimize performance and lifetime of said modules.
21. The device of claim 1, wherein said inorganic material is silicon, a silicon compound, a metal or a metal compound, or a combination thereof.
22. A device according to claim 1, characterized in that the circuits in the main layers are all realized in thin-film technology.
23. A method of manufacturing a data storage and processing device comprising a ROM and/or write-once read-many and/or rewritable memory module and a data processing module, wherein the device is arranged on a substrate, wherein the storage and processing module is provided as a single main layer or as a plurality of stacked main layers on top of the substrate, wherein the memory module and the data processing module in each main layer communicate with the other main layers and circuits arranged on or in the substrate via vias, surface or edge contacts, wherein the device comprises an active circuit with transistors and/or diodes for operating the device, wherein the storage and data processing module is arranged by depositing the main layers and functional sub-layers of the storage and data processing module in successive steps, said method being characterized in that the storage and data processing module is instantaneously stable at static temperatures avoiding subjecting the deposited and processed bottom layer to temperature range values exceeding 150 ℃. 450 ℃ or exceeding the instantaneous stability of the polymer material Depositing and processing said layers under thermal conditions of limited dynamic temperature, or avoiding process induced chemical damage, said transient stability limit being defined as below 500 ℃ in a time not exceeding 10ms, the material for each layer being selected from the group consisting of amorphous, polycrystalline or microcrystalline silicon or germanium, thin films of oxides and other dielectric materials and metals or combinations thereof, and the deposition being carried out by one of the following processes, namely sputtering, evaporation, chemical vapour deposition or plasma assisted chemical vapour deposition, spin coating, processing the deposited layer by conventional semiconductor processes compatible with said thermal conditions selected from but not limited to photolithography, wet etching, dry etching including reactive ion or plasma etching, chemical mechanical polishing, ion implantation, and/or combinations thereof, processing the deposited layer by transient heating using pulsed laser or particle beams, crystallizing the deposited amorphous film, grain refining the deposited film, introducing and activating a dopant thereon; the molecular, oligomeric or polymeric material for each layer is deposited using one of the following processes, namely, solvent techniques, evaporation, sputtering, or other vacuum techniques, or thin film transfer techniques, or a combination thereof.
24. The method of claim 23, wherein the thin film silicon-based circuits and transistors are fabricated using low temperature compatible processes using laser induced crystallization and dopant activation of thin film transistors.
25. A method according to claim 23, wherein the memory module is implemented as a matrix-addressable memory with isolated diodes, characterized in that the isolated diodes are formed in a longitudinal or planar structure by direct deposition of amorphous, microcrystalline or polycrystalline n-and p-type silicon or germanium films and direct deposition of oligomeric or polymeric semiconducting organic thin films.
26. A method according to claim 23, wherein the memory module is implemented as a matrix-addressable memory with isolated diodes, characterized in that the isolated diodes are formed by using laser induced melting and solidification of n-and p-type amorphous or microcrystalline inorganic semiconductor materials deposited directly on the underlying low temperature compatible layer.
27. The method of claim 26, wherein the underlayer is prevented from reacting with molten semiconductor material during laser induced crystallization by providing a thin film diffusion barrier layer.
28. The method of claim 26, wherein the reaction between the molten semiconducting material and the underlying layer is designed to form a stable conducting compound.
29. The method of claim 28 wherein said stable conductive compound is a silicide.
30. A method according to claim 23, wherein the memory module is implemented as a matrix-addressable memory with isolated diodes, characterized in that the isolated diodes are formed by laser induced melting and solidification of deposited amorphous or microcrystalline inorganic films and by formation of pn-junctions of the diodes by means of offset doping, said pn-junctions being formed by layers deposited on underlying metallization layers or by so-called autodoping by means of alloying elements in passive matrix metal layers.
31. A method according to claim 23, wherein the memory module is implemented as a matrix-addressable memory with isolated diodes, characterized in that the isolated diodes are formed by forming schottky barrier diodes by laser induced melting and solidification of deposited amorphous or microcrystalline inorganic films and by using underlying metal structures or compounds formed by reaction with underlying metal structures.
32. The method of claim 23, wherein laser induced crystallization within the explosive crystallization zone is limited such that only instantaneous melting of the film surface is required to form a self-grown liquid film to crystallize the remainder of the crystallized film.
33. A method according to claim 23, characterized in that the isolation structures for the longitudinally isolated diodes are formed from a high-resistance or anisotropic contact material, and that the non-conductive interlayer dielectric is formed in a horizontal direction with respect to the layers.
34. A method according to claim 33, characterized by forming the isolated diode and the non-conductive interlayer dielectric by means of a chemically or thermally induced modification of said contact material.
35. The method according to claim 34, characterized in that the chemically or thermally induced modification is achieved by autodoping of the high resistive amorphous silicon and laser induced crystallization of the high resistive amorphous silicon.
36. The method according to claim 23, wherein the memory module is implemented as a matrix-addressable memory with isolated diodes, characterized in that, with the following process, i.e., laser-induced crystallization where the absorbed laser energy is modulated by the underlying layer or structure, laser-induced crystallization where the absorbed laser energy is modulated by the antireflective or reflective film, with a self-aligned process that limits the formation of diode junctions to only locally limited regions, forming diodes in the spatially confined area while providing lateral isolation between the diodes, by using the underlying or underlying structure as a dopant source for forming diode junctions by explosive crystallization, or selective chemical or physical vapor deposition of amorphous or microcrystalline films using surface modification of the interlayer dielectric surface, controls the interlayer dielectric surface to confine nuclei to metal regions during laser induced crystallization.
37. The method of claim 36, wherein the spatially-restricted area is an intersection of matrices.
38. The method of claim 23, wherein the functional sublayers are separated by a planarizing dielectric layer formed by spin coating or other deposition methods, said dielectric layer being comprised of an oligomer, polymer or inorganic material, and by chemical mechanical polishing.
39. The method of claim 23, wherein the inducing crystallization is initiated using a direct energy source other than a laser including pulsed ions and electron beams.
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JP3526552B2 (en) 2004-05-17
KR20010052512A (en) 2001-06-25
CA2334287A1 (en) 1999-12-09
KR100423659B1 (en) 2004-03-18
KR100392446B1 (en) 2003-07-22
CA2333973C (en) 2006-03-28
NO308149B1 (en) 2000-07-31
NO982518D0 (en) 1998-06-02
CN1191626C (en) 2005-03-02
JP2002518848A (en) 2002-06-25
WO1999063527A2 (en) 1999-12-09
HK1040002A1 (en) 2002-05-17
HK1040002B (en) 2005-02-18
CN1146039C (en) 2004-04-14
JP2006253699A (en) 2006-09-21

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