HK1041587A - Soldering of a semiconductor chip to a substrate - Google Patents

Description

Bonding of semiconductor chips to substrates

Field of the invention

The present invention relates generally to a method and a device produced by said method of bonding a semiconductor chip to a substrate, and more particularly to a method of bonding said semiconductor chip to a package in a radio frequency power transistor.

Background of the invention

Currently, chips are mounted in rf power transistors and rf power modules using a eutectic gold-silicon bonding process. The capsules used are often alloyed with nickel and a relatively thick gold layer (2-5 μm). The bottom surfaces of the chips (transistors, resistors and capacitors) to be placed in the package are provided with a very thin layer of gold. The gold layer serves to prevent the bottom surface of the chip from being oxidized. When gold-silicon is used, the capsule is heated to a temperature of 400-450 deg.C, then the chips are placed on the capsule separately and rubbed back and forth until an alloy is formed between the silicon in the chips and the gold on the capsule. It is not possible to determine when to begin forming the alloy. Thus, this step in the process is typically performed manually so that an operator can observe when the alloy has formed and when an effective weld has been achieved.

Although all of the gold on the capsule (under the chip) is consumed in this soldering process, a significant amount of silicon remains in the chip. This remaining silicon can migrate into the molten AuSi alloy and precipitate out as silicon crystals. This process is accelerated at elevated temperatures and with mechanical friction. Therefore, it is not suitable or possible to achieve this rubbing process mechanically or ultrasonically, since excess silicon crystals will concentrate in the molten Au — Si alloy. A disadvantage of an excess of silicon crystals in the molten alloy is that the melt obtains a viscous consistency, so that it does not flow outwards and wets the surface effectively.

These silicon crystals will effectively encapsulate any bubbles that may have formed between the chip and the encapsulant. Such bubbles greatly reduce the thermal conductivity between the chip and the encapsulant. The total thickness of the AuSi alloy junction formed by the gold on the capsule and the silicon in the chip must not be more than about 50% of the gold thickness. Thus, when the gold thickness is about 4 μm, the junction thickness will be only about 6 μm. This places high demands on the surface flatness, i.e. smoothness, of the package, since otherwise insufficient solder may occur between the chip and the package.

It is generally known to apply additional AuSi solder between the chip and the capsule in a pre-fabricated manner. This is often very difficult and expensive to do due to the small size of the preforms. It is practically impossible to process preforms having a material thickness of less than about 25 μm. However, junctions of such thickness may increase the thermal resistance between the chip and the encapsulant to an unacceptable level.

Summary of the invention

One problem with known soldering techniques of semiconductors to substrates, such as packages in rf power transistors, is that the soldering process requires manual processing steps in the soldering of the individual chips themselves.

Another problem with known techniques is that the formation of silicon crystals impedes the flow of solder, resulting in entrapment of gas bubbles. These bubbles tend to block heat transfer away from the chip.

A further problem of the known technique is that the high solidification temperature of the SiAu leads to high mechanical stresses between the chip and the capsule, thereby placing an upper limit on the size of the chip. If this limit is exceeded, the chip will crack.

A further problem of the known art is that in order to prevent the chips from being broken by mechanical stress, several small chips must instead be mounted, increasing the cost in this respect.

Another problem with the known technique is that the high operating temperature (400-. This problem must be counteracted with special nickel plating techniques and thick gold layers on the surface, which is not actually required for AuSi soldering purposes.

Another problem with the known technique is the high operating temperatures incurred by the chip mounting process, meaning that the individual parts of the actual package must be bonded together at 790 ℃ with a higher melting hard solder, i.e. a high copper containing solder such as AgCu. Since those metals and ceramics suitable for this document do not have the same coefficient of thermal expansion as each other, the metals and ceramics combine at such high temperatures, causing high mechanical stresses after the junction cools. This limits the design of the capsule. For example, it is not possible to use the optimal metallic copper and ceramic AlN in the capsule because the expansion coefficients of these materials are too different from each other.

Another problem with the known technique is that the relatively thin solder joint formed places high demands on the surface flatness of the package, since otherwise insufficient solder will occur, resulting in not all chips being soldered effectively. This greatly reduces the thermal conductivity between the chip and the package.

The present invention addresses these problems by providing a method of soldering a semiconductor chip to a substrate, such as a package in a radio frequency power transistor. The semiconductor chip is first provided with an adhesive layer consisting of a first material composition. A solderable layer consisting of a second material composition is then arranged on this adhesion layer. An oxidation resistant layer comprised of a third material composition is then arranged on the solderable layer. A solder layer composed of a gold-tin alloy is then applied over the oxidation resistant layer. The chip is placed on the solderable capsule surface via said gold-tin solder. The capsule and chip are exposed to an inert atmosphere with a reducing gas, and the capsule and chip are subjected to a pressure substantially below atmospheric pressure during heating of the gold-tin alloy in the solder to a temperature above its melting point. The pressure is increased while the gold-tin solder is in a molten state, and the temperature is decreased above a predetermined pressure to solidify the gold-tin alloy.

According to a preferred embodiment of the method according to the invention, the first material composition is a titanium-tungsten composition (TiW), the second material composition is nickel (Ni) and the third material composition is gold (Au).

In another preferred embodiment of the method of the invention, the first material composition is titanium (Ti), the second material composition is platinum (Pt) and the third material composition is gold (Au).

According to another preferred embodiment of the method according to the invention, the gold-tin solder composition is compensated by gold from the capsule so that the final alloy composition is as close as possible to the eutectic melting point.

In another preferred embodiment of the method according to the invention, the gold-tin alloy in the solder is a composition consisting of 75% gold and 25% tin, while the package on which the chip is to be soldered comprises a 3-4 μm thick layer of gold.

According to a further preferred embodiment of the process according to the invention, the reducing gas is gaseous formic acid.

In one embodiment of the rf power transistor according to the present invention, the transistor comprises at least one rf power semiconductor chip and an encapsulant. The semiconductor chip is provided with an adhesive layer composed of a first material composition, a solderable layer composed of a second material composition arranged on the adhesive layer, and an oxidation-resistant layer composed of a third material composition arranged on the solderable layer. The chip is arranged on the surface of the solderable capsule via a solder containing a gold-tin alloy whose alloy composition is close to the eutectic melting point.

The object of the present invention is to enable a pore-free solder joint between a semiconductor chip and a substrate, such as a capsule in a radio-frequency transistor, for example, where a low solder solidification temperature is desired, which enables aluminium nitride to be used as a ceramic insulator in certain types of capsules instead of the highly toxic barium oxide.

One advantage provided by the present invention is that the entire process from the step of positioning the chip to the step of firmly soldering the chip to the package can be automated.

Another advantage provided by the present invention is that the thickness of the solder joint can be accurately determined to accommodate the curvature of the encapsulant and minimize the thermal resistance of the solder joint.

Yet another advantage provided by the present invention is that the thermal conductivity of the gold-tin alloy in the solder joint is about 2 times greater than the thermal conductivity of a solder joint composed of a gold-silicon alloy.

Another advantage provided by the present invention is that the relatively low soldering temperature minimizes the risk of nickel diffusion through the gold. Thus, the thickness of the gold on the capsule can be reduced from 3-5 μm to 0.5-1 μm required for wire bonding. In addition to reducing costs, this thinner gold coating greatly reduces the risk of poor solder bonding between the package and the printed circuit board caused by gold contamination of the tin-lead solder. It is also possible to selectively plate a very thin layer of gold on the tab piece to be soldered to the printed circuit board.

Yet another advantage provided by the present invention is that the gold-tin welding process is a batch process, which enables a large number of capsules to be processed simultaneously. This is particularly advantageous for capsules of the kind that can be handled in an array, since the manufacturing costs are substantially reduced.

Another advantage afforded by the invention is that the soldering process using a solder consisting of a gold-tin alloy is carried out at a temperature of only about 300 c, thereby enabling fundamental changes in the method of manufacturing the actual capsule. The brazing of the capsule parts at 790 c, i.e. soldering containing much copper, can now be replaced by a much lower temperature soldering process, e.g. soldering with a solder containing a gold-silicon alloy at 380 c. The latter process results in much less thermodynamic stress between the ceramic and the metal in the capsule, enabling the use of materials with poorer thermal matching properties, such as copper and aluminum nitride, for example, to obtain benefits such as improved thermal conductivity and non-toxicity.

The invention will be described in more detail below with reference to exemplary preferred embodiments thereof and the accompanying drawings.

Description of The Preferred Embodiment

Gold-tin soldering requires solderable surfaces on both the substrate and the semiconductor chip. For semiconductor chips this requirement is achieved by coating the semiconductor chips which have otherwise been finished with an adhesive layer on the semiconductor, which may be, for example, silicon. A solderable layer is disposed on the adhesion layer and an oxidation resistant layer is arranged on the solderable layer. This adhesion layer may for example comprise TiW (titanium-tungsten), while the solderable layer may comprise Ni (nickel) and the oxidation resistant layer may comprise Au (gold). The adhesion layer may also consist of pure titanium, in which case the solderable layer may consist of platinum and the oxidation resistant layer may consist of gold.

The thickness of the adhesion layer can be in the range of 1000-1500 , the thickness of the solderable layer can be in the range of 1000-1500 , and the thickness of the oxidation resistant layer can be in the range of 5000-10000 . A thick gold-tin solder alloy is applied to or simultaneously with the anti-oxidation layer. This ensures that each chip has metal solder, thereby eliminating the need to handle the solder preform.

Gold-tin solder can be applied in many different ways, for example by means of selective plating, deposition in the form of solder paste by stencil printing or screen printing methods. Solder is preferably sputtered or plated onto the back side of the semiconductor chip, or the foil may be affixed to the back side of the semiconductor chip by melting a very thin gold-tin foil, or by thermocompression bonding.

Since the capsule in which the chip or chips are to be placed is not absolutely flat, the amount of solder used must be appropriate in order to ensure that the space between the chip and the capsule is always filled with gold-tin solder. In the case of, for example, a chip length of 5mm and in the case of a 5% capsule, a gold-tin thickness of 10 μm is required.

The gold coating is always on the package on which the chip is mounted. If the solder is previously of an alloy composition that is exactly at the eutectic melting point, the gold will alloy with the gold-tin solder, thereby raising the melting point. To avoid this, the chip is coated with a gold-tin alloy whose composition is determined taking into account the gold from the capsule. For example, a suitable composition may be 75% gold and 25% tin on a capsule containing 3-4 μm gold. This resulted in a final composition very close to the eutectic melting point of 280 ℃.

When soldering a chip to a package, bubbles often form at the solder joints. Since the occurrence of such a bubble is controlled by how the solder wets both soldering surfaces, it is impossible to prevent the formation of such a bubble. These bubbles are very detrimental to solder joints in high power components such as radio frequency power transistors, because they cause the components to overheat. This problem can be minimized by welding at the lowest possible gas pressure, e.g., 1-10 torr. When soldering is complete, the ambient pressure on the solder joint is increased, for example to normal atmospheric pressure, to solidify the solder before cooling the component. Any bubbles that have formed during the melting of the solder will thus be compressed and become practically harmless. The volume of such a bubble will be reduced with respect to the pressure difference, in which case the volume of the bubble will be reduced by a factor of about 100.

The gold-tin alloy is easily oxidized and the oxide (tin oxide) prevents satisfactory wetting and flow of the solder. The use of conventional fluxes in welding operations is inappropriate because they result in decomposition products that are not readily soluble at the welding temperatures of interest (300- & 350 ℃). Moreover, it is very difficult, impractical and expensive to clean away flux residue. Thus, a gaseous flux may be used in the welding process. In the present case, a small amount of formic acid vapor to which an inert gas is added is used. The inert gas used may be, for example, nitrogen. The nitrogen gas may be passed through a container containing formic acid before being fed to the chamber where the weld is to be made. The nitrogen then carries the formic acid molecules into the working chamber. Formic acid vapor reduces tin oxides to provide metallic tin as well as other gaseous products. This eliminates the need to clean the components after the welding operation.

It is to be understood that the invention is not limited to the exemplary embodiments described above, but that modifications are possible within the scope of the following claims.

Claims (9)

1. A method of soldering a semiconductor chip to a substrate, such as a package in an RF power transistor, characterised by

Coating a semiconductor chip with an adhesive layer composed of a first material composition;

covering the bonding layer with a solderable layer consisting of a second material composition;

covering the solderable layer with an anti-oxidation layer consisting of a third material composition;

covering the anti-oxidation layer with a gold-tin solder layer;

placing the chip on the solderable surface of the package via said gold-tin solder;

exposing the capsule and chip to an inert environment in which a reducing gas is introduced and subjecting said capsule and chip to a pressure substantially below atmospheric pressure while heating the gold-tin alloy to a temperature above its melting point temperature;

increasing the gas pressure in the case that the gold-tin solder is melted; and

when the predetermined gas pressure is exceeded, the temperature is reduced to solidify the gold-tin solder.

2. The method according to claim 1, characterized in that the first material composition is titanium-Tungsten (TiW), the second material composition is nickel (Ni) and the third material composition is gold (Au).

3. The method according to claim 1, characterized in that the first material composition is titanium (Ti), the second material composition is platinum (Pt) and the third material composition is gold (Au).

4. A method according to claim 1, characterized in that the composition of the gold-tin solder is adapted to compensate for gold from the capsule so that a final alloy composition is obtained having a eutectic melting point or close to said eutectic melting point.

5. A method according to claim 4, characterized in that the gold-tin solder comprises 75% gold and 25% tin when the capsule comprises a gold layer with a thickness of 3-4 μm.

6. A process according to claim 1, characterized in that the reducing gas is gaseous formic acid.

7. An rf power transistor comprising at least one rf power semiconductor chip and an encapsulation, characterized in that the semiconductor chip comprises an adhesive layer consisting of a first material composition, a solderable layer consisting of a second material composition provided on said adhesive layer, and an oxidation-resistant layer consisting of a third material composition provided on said solderable layer, wherein the chip is arranged on the surface of the solderable encapsulation via a gold-tin solder whose alloy composition has a eutectic melting point or a close to eutectic melting point.

8. The rf power transistor of claim 7, wherein the first material composition is titanium-Tungsten (TiW), the second material composition is nickel (Ni), and the third material composition is gold (Au).

9. The rf power transistor of claim 7, wherein the first material composition is titanium (Ti), the second material composition is platinum (Pt), and the third material composition is gold (Au).