HK1057290B - Test structure for evaluating antenna effects - Google Patents

Description

High-sensitivity test structure for evaluating plasma antenna effect

Technical Field

The present invention relates to a test wafer for evaluating and monitoring plasma potential (plasma potential) on a wafer surface, and more particularly, to an NROM-like antenna test structure formed on a test wafer for performing highly sensitive monitoring of charge accumulation caused by plasma and providing quantitative data.

Background

With the miniaturization of integrated circuits, multilevel interconnect technology is becoming more complex. In this case, high density anisotropic plasma etching plays an important role in semiconductor processing. Plasma etching techniques define trench structures with very small line widths in the dielectric layer and produce vertical trench profile sidewalls. For example, reactive-ion-etching (RIE) plasmas are commonly used in semiconductor processing to achieve precise dimensional control. Plasma formation is typically induced by radio waves, however, plasma treatment has also recently been found to cause damage to surface elements of the wafer.

The antenna effect (antenna effect) is a problem that often occurs in semiconductor processes. Generally, when a plasma process is performed, the surface of the semiconductor substrate is bombarded by plasma ions, which generate many charged particles, such as electrons, and accumulate on the surface of the semiconductor substrate. Sometimes these charged particles are collected by the interconnect metal structure exposed to the plasma environment and accumulate on the device structure, which may affect the electrical performance of the device and in severe cases even damage the device itself. The strength of the antenna effect can be expressed by the following relation:

R＝A_a/A_g

wherein R is referred to as the wire ratio (antenna ratio); a. the_aA so-called Charge Collection Electrode (CCE) area connected to the gate electrode; a. the_gRepresented is the gate area.

The conventional method for monitoring plasma antenna effect is to use a charge monitor wafer (also sometimes called a CHARM wafer). Conventional charge monitor chip with E²PROM is the main unit test structure, which can be written and reused repeatedly. Reference is made to "CHARMWARA CHARACTERIZATION" REDHOLM Technical Note TN-1, June 1996, which is not repeated herein. E is known to the person skilled in the art²The PROM structure basically includes a floating gate and a control gate stacked over the floating gate. An oxide layer is arranged between the floating gate and the semiconductor substrate for controllingThe grid electrode and the floating grid electrode are separated by another dielectric layer. However, the existing ones employ E²The charge monitor chip of PROM architecture has the following disadvantages. First, the existing ones adopt E²Charge monitoring chip of PROM structure²The PROM cell has an insufficient coupling ratio (coupling ratio), which results in a large loss of detection sensitivity of the charge monitor chip. Generally, a voltage threshold difference (Δ V) can be utilized_t) To scale the plasma-derived charge of the antenna effect, the relationship is as follows:

ΔV_t＝(R ×Q_F)/C_total

wherein R represents E of the charge monitor wafer²The coupling ratio of the PROM unit; q_FRepresenting the amount of charge trapped in the floating gate; c_totalRepresents E²The overall capacitance of the PROM cell. As known to those skilled in the art, E²The coupling ratio of the PROM cells is between about 0.5 and 0.6, which is a major cause of insufficient detection sensitivity of the charge monitor chip. Furthermore, the existing ones employ E²The charge monitor wafer structure of PROM structures is more complex, which means more process steps and higher manufacturing costs are required.

As can be seen from the above, conventional use of E²The charge monitor chip with PROM structure has a great improvement space, and there is a need in the industry for a charge monitor chip that is lower in cost, can provide higher detection sensitivity, and can perform accurate quantitative analysis, so as to improve the yield of the product and reduce the production cost.

Disclosure of Invention

Accordingly, it is a primary objective of the claimed invention to provide an NROM-like (NROM-like) antenna test structure formed on a test wafer for highly sensitive monitoring of charge accumulation caused by plasma and providing quantitative data.

In accordance with one aspect of the present invention, a high sensitivity test structure for quantitatively detecting a plasma antenna effect is disclosed, the test structure comprising: a substrate; an ONO dielectric layer formed on the substrate, wherein the ONO dielectric layer is composed of a lower oxide layer, a silicon nitride layer and an upper oxide layer; an electrode formed on the ONO dielectric layer; and an antenna structure electrically connected to the electrode for collecting charges induced by a plasma.

In accordance with one aspect of the present invention, a test wafer for quantitatively evaluating plasma-induced charge effects comprises: a silicon wafer; and an array of test structures formed on the surface of the silicon wafer for detecting a plasma-induced charge effect, wherein each of the test structures comprises: a substrate; an ONO dielectric layer formed on the substrate, wherein the ONO dielectric layer is composed of a lower oxide layer, a silicon nitride layer and an upper oxide layer; an electrode formed on the ONO layer; and an antenna structure electrically connected to the electrode for collecting charges induced by a plasma.

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a schematic top view of the present invention;

FIG. 2 is a schematic cross-sectional view of the present invention; and

fig. 3 is a schematic cross-sectional view of a second embodiment of the present invention.

The reference numerals in the drawings are explained below:

10 wafer 12 field effect transistor

14 grid 15 antenna structure

16 contact plug 22 source

24 drain 26 diffusion region

30ONO dielectric layer 32 bottom oxide layer

34 silicon nitride layer 36 upper oxide layer

50 capacitance test structure 52 doped well

54 upper electrode

Detailed Description

As previously mentioned, the existing use of E²One of the drawbacks of the charge monitor chip with PROM structure is the requirement of fabricating two polysilicon stacks, i.e., the floating gate and the control gate structure are defined separately. Therefore, at least one additional photolithography etching process and cleaning step are required in the manufacturing process, which results in increased cost. In addition, evaluating the plasma-derived charges accumulated on the wafer surface also requires a more sensitive test structure to accomplish. The test structure has the advantages of high sensitivity, low manufacturing cost and quantitative analysis, and can completely make up the defects of the prior art.

Referring to fig. 1, fig. 1 is a schematic top view of a test structure according to the present invention. As shown in fig. 1, a field effect transistor 12 is provided on a substrate 10. The substrate 10 is formed of a silicon substrate. The transistor 12 includes a gate 14 electrically connected to an antenna structure 15 via a contact plug 16. The gate 14 is made of polysilicon. The antenna structure 15 may be a single-layer interconnect structure or a multi-layer interconnect structure for collecting charges induced by a plasma process. A source 22 and a drain 24 are provided in the substrate 10 on either side of the gate 14. Another diffusion region 26 is formed in substrate 10 adjacent to transistor 12.

Referring to FIG. 2, FIG. 2 is a cross-sectional view of the test structure along line AA' of FIG. 1. As shown in fig. 2, the gate 14 is separated from the substrate 10 by an ONO dielectric layer 30. The ONO dielectric layer 30 includes a bottom oxide layer 32, a top oxide layer 36, and a silicon nitride layer 34 between the bottom oxide layer 32 and the top oxide layer 36. In the figure, the source, drain, gate and metal electrode are represented by S, D, G and P, respectively. The ONO dielectric layer 30 is formed by conventional methods. For example, the process disclosed in U.S. patent No. 5966603 includes forming a bottom oxide layer on the substrate surface at a low temperature, depositing a silicon nitride layer on the bottom oxide layer by chemical vapor deposition, and forming an upper oxide layer on the silicon nitride layer by oxidation or deposition. The thickness of the upper oxide layer 36 is recommended to be between 80 and 100 angstroms, preferably around 90 angstroms. The thickness of silicon nitride layer 34 is between 60 and 80 angstroms, preferably around 70 angstroms. Bottom oxide layer 32 is about 50 to 70 angstroms thick. The gate 14 and source drain regions 22 and 24 are formed by conventional photolithography steps and etching.

When a plasma operation is performed, plasma-derived charges, such as electrons, accumulate in the antenna structure 15, causing a charge to accumulate on one side of the ONO dielectric layer 30 and a potential difference to form between the substrate 10 and the gate 14. The energetic charged particles are injected into the SiN layer 34 and trapped therein, resulting in a threshold voltage shift (Δ V)_t) It can be expressed by the following relation:

ΔV_t＝Q/C

where Q is the amount of charge trapped in the silicon nitride layer 34; c is the capacitance between the gate 14 and the substrate 10. By measuring the threshold voltage shift (Δ V)_t) The total amount of plasma-derived charges Q trapped in the silicon nitride layer 34, i.e., Q ═ Δ V, can be quantitatively calculated_tAnd (4) x C. Compared with the existing adoption of E²Compared with charge monitoring chip of PROM structure, the test structure of the invention can generate larger range of initial voltage shift (delta V)_t). This is due to the fact that the coupling value of the NROM-like test structure of the present invention is close to 1.

Proceeding with the threshold voltage (V)_t) For measurement, the source 22 and the substrate 10 are both grounded. A positive voltage of about 1.6V is applied to the drain 24. A gradually increasing positive voltage is applied to the gate 14. Shift in threshold voltage (Δ V)_t) Can be obtained by comparing a reference threshold voltage with the measured threshold voltage value. Due to the starting voltage (V)_t) Are well known to those skilled in the art and therefore their details are not described in detail.

Referring to fig. 3, fig. 3 is a schematic cross-sectional view of a CV test structure having an ONO dielectric layer in another preferred embodiment of the invention. As shown in fig. 3, a capacitive test structure 50 is formed on the substrate 10. The substrate 10 may be a P-doped silicon substrate. The capacitor 50 has an upper electrode 54 formed of polysilicon. In addition, the upper electrode 54 may be made of metal or metal silicon compound. The upper electrode 54 is electrically connected to a charge-collecting antenna structure (not shown in fig. 3). In the substrate 10, a doped well 52, which serves as a lower electrode, is formed below an upper electrode 54. Between the top electrode 54 and the bottom electrode 52 is an ONO dielectric layer 30. Similarly, the ONO dielectric layer 30 includes a bottom oxide layer 32, a top oxide layer 36, and a silicon nitride layer 34 between the bottom oxide layer 32 and the top oxide layer 36. In general, test structure 50 occupies a wafer area of about 100 microns by 100 microns. Existing C-V metrology methods may be effectively performed on the test structure 50 of the present invention. In the C-V test, the substrate 10 is typically grounded, and a probe is used to measure the threshold voltage of the gate 54. Then, the current flat-band shift calculation method is compared with a reference threshold voltage to calculate the threshold voltage shift (Δ V)_t)。

Briefly, the present invention is directed to an NROM-like test structure with high sensitivity or a capacitive test structure derived therefrom with an ONO dielectric layer. Due to the improved sensitivity, the test structure of the present invention can be used for quantification and analysis by using the C-V method or the conventional threshold voltage measurement procedure even in an environment with only a small amount of plasma derived charges.

The above-mentioned embodiments are only preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the scope of the present invention.

Claims (12)

1. A high sensitivity test structure for quantitatively detecting a plasma antenna effect, the test structure comprising:

a substrate;

an ONO dielectric layer formed on the substrate, wherein the ONO dielectric layer is composed of a lower oxide layer, a silicon nitride layer and an upper oxide layer;

an electrode formed on the ONO dielectric layer; and

an antenna structure electrically connected to the electrode for collecting charges induced by a plasma.

2. The test structure of claim 1, wherein charges induced by the plasma are injected into the silicon nitride layer through the top oxide layer.

3. The test structure of claim 1, wherein the electrode is comprised of polysilicon.

4. The test structure of claim 1, wherein the electrode is comprised of a metal.

5. The test structure of claim 1, wherein the thickness of the top oxide layer of the ONO dielectric layer is between about 80-100 angstroms, the thickness of the silicon nitride layer is between about 60-80 angstroms, and the thickness of the bottom oxide layer is between about 50-70 angstroms.

6. The test structure of claim 1, wherein the antenna structure is a single or multi-layer metal interconnect.

7. The test structure of claim 1, further comprising a drain and a source formed on the surface of the substrate on opposite sides of the electrode.

8. A test wafer for quantitatively evaluating plasma-induced charge effects, the test wafer comprising:

a silicon wafer; and

an array of test structures formed on the surface of the silicon wafer for detecting the effect of a plasma-induced charge, wherein each of the test structures comprises:

a substrate;

an ONO dielectric layer formed on the substrate, wherein the ONO dielectric layer is composed of a lower oxide layer, a silicon nitride layer and an upper oxide layer;

an electrode formed on the ONO dielectric layer; and

an antenna structure electrically connected to the electrode for collecting charges induced by a plasma.

9. The test wafer of claim 8 wherein charges induced by the plasma are implanted through the top oxide layer into the silicon nitride layer.

10. The test wafer of claim 8 wherein the electrode is comprised of polysilicon.

11. The test wafer of claim 8, wherein the thickness of the top oxide layer of the ONO dielectric layer is between about 80-100 angstroms, the thickness of the silicon nitride layer is between about 60-80 angstroms, and the thickness of the bottom oxide layer is between about 50-70 angstroms.

12. The test wafer of claim 8, wherein the test structure further comprises a drain and a source formed on the substrate surface on both sides of the electrode.