HK1062956B - Integrated circuit and laminated leadframe package - Google Patents

Description

Integrated circuit and layered lead frame package

Technical Field

The present invention relates generally to semiconductor devices and, more particularly, to small area packaged integrated circuits.

Background

Electronic system manufacturers continue to demand components with small physical size and low manufacturing cost while having high performance and high reliability. To meet this demand, semiconductor manufacturers are working to develop techniques to reduce device size and cost by placing multiple components within a single leadframe, which packages form a single integrated circuit package block.

The size of the integrated circuit chip is determined in part by the minimum feature size of the package leadframe, which determines the width and spacing of the leads. The minimum feature size is typically about equal to the thickness of the leadframe metal, which is a function of the mechanical requirements of the package block and the electrical and thermal specifications of the packaged circuit. For example, high power circuits typically require a relatively thick leadframe metal to support large current levels and to adequately dissipate the heat generated by the circuit.

Small interconnect feature sizes have been previously achieved by mounting the circuit on an interposer (interposer). An interposer is a type of printed circuit board having a metal foil sheet sandwiched between two layers of dielectric that is etched to prepare interconnect lines that electrically connect components mounted on the interposer. The metal foil is thin so that small feature sizes can be achieved. However, for high current devices, the thin metal lines of the interposer must be made very wide, which offsets the advantages of using metal foils to increase the package area. For high power applications, the high thermal resistance of the thin metal foil of the insert can cause undesirable heat transfer. Moreover, the manufacturing costs of the inserts are high, which further limits their application.

Other devices use a rolled metal lead frame to achieve small feature sizes by thinning the metal using a half-etch technique that selectively etches away part of the thickness of the lead frame. However, the half etching is not easy to control, and the reliability of the integrated package is poor because the adhesion between the encapsulant and the curved surface of the half-etched lead frame is insufficient and the encapsulant is suspended.

Accordingly, there is a need for an integrated circuit and packaging technology that can accommodate multiple components in a small footprint, with large current and heat dissipation capabilities, and high reliability, while maintaining low cost.

Disclosure of Invention

The present invention thus provides an integrated circuit characterized by a first semiconductor die; and a lead frame, which includes: a first laminate having an exposed surface formed as a lead of the integrated circuit and a second surface for mounting the first semiconductor die, and a second laminate having a bottom surface in contact with the second surface of the first laminate to electrically couple the lead to the first semiconductor die.

The above integrated circuit according to the present invention is further characterized by comprising a mold compound for encapsulating the first semiconductor die.

The integrated circuit according to the present invention, wherein the second stack forms a mold block of the mold compound.

The integrated circuit according to the present invention, wherein the second laminate extends outwardly from the leads to form a mask frame, and the mold compound covers the mask frame.

The integrated circuit according to the invention wherein the bottom surface of the first semiconductor die is disposed on the second surface of the first laminate layer, the second laminate layer having a thickness greater than the thickness of the first semiconductor die.

The above integrated circuit according to the present invention is further characterized by a second semiconductor die mounted on the leadframe.

The integrated circuit according to the present invention wherein one of the first interconnects of the first stack is electrically coupled to a bond pad of the first semiconductor die through the second stack.

The above integrated circuit according to the present invention, wherein the lead frame further comprises a third laminate layer, the first surface of which is in contact with the second surface of the second laminate layer, and is patterned with a bonding tape in contact with the bonding pads of the first semiconductor die.

The present invention also provides a semiconductor device characterized in that: a semiconductor die; and a leadframe formed as stacked conductive stacks, wherein a first of the stacked conductive stacks is patterned to form outer leads of the semiconductor device and has a surface for mounting a semiconductor die, wherein a second of the stacked conductive stacks has portions that contact bond pads of the semiconductor die and is coupled to the outer leads through a third of the stacked conductive stacks.

The present invention also provides a semiconductor package block for housing a semiconductor die, characterized by a lead frame comprising: a first conductive stack having an exposed surface patterned for making external electrical connections, and a second surface for mounting a semiconductor die; and a second conductive stack in contact with the second surface of the first conductive stack and providing a signal path from the semiconductor die to the first conductive stack.

Drawings

FIG. 1 is a partial isometric view of a set of integrated circuits at selected steps of manufacture;

FIG. 2 is a cross-sectional view of a packaged integrated circuit;

FIG. 3 is a cross-sectional view of another embodiment of a packaged integrated circuit;

FIG. 4 is yet another partial isometric display diagram of an integrated circuit of an embodiment; and

FIG. 5 is a partial isometric display of an integrated circuit of another implementation.

Detailed Description

In the drawings, elements having the same reference number designation have similar functions.

Fig. 1 is a partially isometric view of an integrated circuit array 10 at selected fabrication steps, including a leadframe matrix comprising a laminated matrix 2, a laminated matrix 4, and an overmolded or covered encapsulant block 8. A large number of element groups 6 are mounted at predetermined positions of the laminated matrix 2. The individual devices in the array 10 are referred to as an integrated circuit 100, and the integrated circuit 100 is shown prior to singulation. As shown, the array 10 is formed from a two-layer laminated matrix, but in some applications it may be advantageous to use three or more laminated matrices to form the lead frame so that the desired functionality can be achieved. Note that the element group 6 is shown in the form of a separate element for simplicity of description, but it typically includes multiple electrical elements that are mounted using a standard pick-and-place tool or similar equipment.

The laminate matrix 2 is formed of a layer of rolled copper or other conductive material patterned to form an array of leadframe laminates 20 having the same configuration to mount the component group 6. The patterning of the layer matrix 2 is achieved by etching, stamping, milling or almost any other standard leadframe patterning method. The laminated matrix 2 includes alignment holes 11 through which alignment posts (not shown) are inserted for alignment during fabrication. The laminated matrix 2 is typically more than about 50 microns thick.

The laminated matrix 4 is formed similar to the laminated matrix 2 from a layer of rolled copper or other conductive material that is patterned to form a leadframe laminate 40 having a similar configuration. The shape of the leadframe stack 40 is generally different from the shape of the leadframe stack 20. A plurality of alignment holes 13 are positioned on the alignment posts of the above-mentioned alignment stack matrices 2 and 4 so that the leadframe stacks 40 overlie their corresponding leadframe stacks 20. Laminated matrix 4 is typically more than about 50 microns thick and may be different in thickness and material than laminated matrix 2. For example, in one embodiment, the thickness of the laminated matrix 2 is approximately 50 microns to facilitate etching features in small dimensions (e.g., high lead density), while the thickness of the laminated matrix 4 is 1000 microns to selectively provide high thermal or electrical conductivity.

Array 10 was prepared as follows. The upper surface 5 of the laminated matrix 2 is covered by a layer of low temperature solder, conductive epoxy or other conductive material having conductive and adhesive properties and may be processed at less than 300 degrees celsius. The lower surface 3 of the laminate matrix 4 is typically covered by the same material.

The component groups 6 are then mounted in their specific positions and the alignment holes 11 and 13 are used to align the stacked matrices 2 and 4 when the lower surface 3 is brought into contact with the upper surface 5. The stacked matrices 2 and 4 are then placed on a thermocompression or other standard solder reflow tool to mechanically bond the lower surface 3 and the upper surface 5, which also forms the electrical connection between the stacked matrices 2 and 4. Depending on the application, other fabrication processes such as wire bonding are typically done after stacking and adhering of stacks 2 and 4, if not done earlier in the fabrication cycle.

After the lamination matrices 2 and 4 are adhered, the assembly is placed in a molding tool and a standard thermoset resin or thermoplastic molding compound is used to form the overlay seal block 8. The cover seal block 8 covers the element group 6 and the exposed surfaces of the laminated matrices 2 and 4 that are within the seal area 9 on the surface 22 of the laminated matrix 4. The encapsulation process leaves the lower surface 7 of the matrix laminate 2 uncovered or exposed, which may provide external electrical connection leads to be fabricated and connected to the integrated circuit 100 after singulation.

After the cap seal block 8 is solidified, the laminated matrices 2 and 4 and the cap seal block 8 are sawed into individual packaged integrated circuits along predetermined dicing lines. For example, dicing lanes 14, 24, 16 and 26 define the path of a saw blade that singulates integrated circuit 100 from array 10 to fabricate individual packaged devices.

The stacked approach allows virtually any number of stacked matrices to form a semiconductor package block, the maximum number of which is a function of the desired functionality, fabrication cost and final package height.

Fig. 2 shows a cross-sectional view of an integrated circuit 100 in which the component group 6 comprises a semiconductor die 102 and a semiconductor die 103 accommodated in a package block 101, the package block 101 comprising a stack of layers 20 and 40 and a separate encapsulation block 108 covering the encapsulation block 8. Note that the left and right surfaces of the integrated circuit 100 are defined by the cut lines 16 and 26, respectively.

The stack 20 is etched to form die flags 104-105 for respectively positioning the semiconductor die 102-103 and the leads 106-107. Using existing processing techniques, the minimum feature size of the stack 20, such as the spacing 109 between the die flag 105 and the lead 107, and its thickness are approximately equal. Thus, in one embodiment, the stack 20 has a thickness of 250 microns and the gap 109 has a width of approximately 250 microns.

As shown, the lower surface 3 of the stack 40 is in contact with the upper surface 5 of the stack 20, and the regions 206 and 207 are electrically and mechanically connected to the leads 106 and 107. The material on the layer stack 40 covering the areas of the die flags 104 and 105 is removed so that the semiconductor dies 102 and 103 can be arranged on the layer stack matrix 2 and can be processed subsequently without damage. The thickness of the stack 40 is chosen to be slightly thicker than the semiconductor die 102-103 such that the upper surface 114-115 of the semiconductor die 102-103 is recessed from the plane of the surface 22. For example, in an embodiment where the thickness of a semiconductor die 102-103 is about 250 microns, the thickness of the stack 40 is selected to be about 300 microns.

Wire bonds 111 are formed between regions of the semiconductor die 102 and 206, and electrical connections are made between the semiconductor die 102 and the outside through the wire bonds 111, the regions 206, and the leads 106. Likewise, wire bonds 112 are formed between semiconductor die 103 and region 207, and electrical connections are made between semiconductor die 103 and the outside through wire bonds 112, region 207, and wires 107. The electrical connection to the external device or printed circuit board is achieved by features defined on the lower surface 7, the lower surface 7 remaining exposed after the encapsulation process. Wire bonds 113 are formed between the semiconductor dies 102 and 103 to provide direct internal connections.

The plane 114 where the surface of the semiconductor die 102 and 103 is located and 115 is lower or slightly lower than the surface 22. As a result, the loop height (loop height) of wire bonds 111 and 112 is much lower than other semiconductor packaging techniques without introducing mechanical stress. The short loop height reduces the overall length of wire bonds 111 and 112, which provides low parasitic inductance and parasitic resistance, improving the frequency response and overall performance of integrated circuit 100. Moreover, because the height of surface 22 is determined by the thickness of stack 40, control of the loop height is improved and performance is more consistent.

Note that regions 206-207 are defined by scribe lines 16 and 26, respectively, and that leads 106-107 are recessed a distance from scribe lines 16 and 16, respectively. Thus, the lower surface of the region 206 and 207 extends outward to form a mask. This arrangement allows the sealant material to flow underneath and cover the exposed portion of the region 206-207 to form the molded lock 120. Many semiconductor packages employ mold locks to improve mechanical adhesion and to prevent the encapsulant from dangling to improve reliability. Because the laminate layers are used to form the mold lock 120, their edges are substantially square, which can provide greater mechanical and adhesive strength than the curved surfaces of mold locks formed using half-etch methods.

Fig. 3 shows a cross-sectional view of another embodiment of an integrated circuit 100, such as a transceiver in a wireless communication device. The components on integrated circuit 100 have a similar structure and function as described in fig. 2, except that package block 101 is formed from 4 stacked layers, including stacks 20 and 40, stack 60 formed on stack 40, and stack 80 formed on stack 60, as shown. Semiconductor die 102 is configured as a high frequency, low noise amplifier and semiconductor die 103 is configured as a high frequency, high power transmitter stage. In one embodiment, the semiconductor die 102-103 is designated to operate at an operating frequency greater than 6 GHz.

Regions 131 and 132 of the stack 20 serve as leads for the integrated circuit 100. Regions 133 and 134 of stack 40 and regions 135 and 136 of stack 60 are stacked as shown and function as a pad to support region 137 of stack 80 at a height that avoids electrical contact with wire bonds 112. The regions 131-137 are electrically coupled together as a faraday cage or electromagnetic barrier around the semiconductor die 103. Such a barrier substantially prevents electromagnetic waves generated by semiconductor die 103 from propagating to semiconductor die 102 and vice versa. One result of using a stacked approach to form the package blocks 101 is that the semiconductor dies 102-103 are shielded from each other. Also, electromagnetic interference to the inside and outside of the package block 101 is reduced while maintaining low manufacturing costs.

Fig. 4 shows a partial isometric view of another embodiment of an integrated circuit 100 including a semiconductor package block 101 formed with a stack 20, a stack 40, a stack 60, and a seal block 108, and an element group 6. Component group 6 includes semiconductor die 102, packaged semiconductor device 320, and passive components including inductor 322 and bypass capacitor 324.

The packaged semiconductor device 320 is implemented as a sealed, fully tested integrated circuit, housed within the package block 101 and resealed with the sealing block 108. Because guide clips and wire bonding tools are not required, the packaged semiconductor device 320 can be placed closer to the semiconductor die 102 than other bare die. Thus, in many cases, such "layer-by-layer packaging" allows for smaller dimensions than would be possible if two separate unpackaged semiconductor dies had to be mounted in the same package block. Also, by testing the packaged semiconductor device 320 before placement into the package block 101, overall yield is increased and manufacturing costs are reduced.

As shown, inductor 322 is electrically coupled between regions 151 and 153 of stack 60 and with leads 161 and 164. Note that inductor 322 is laterally positioned and intersects leads 162 and 163, thus providing a flexible, low-cost interconnection scheme. In a certain embodiment, the inductor 322 produces an inductance value of about 1 microhenry.

The capacitor 324 is vertically positioned between different stacks, i.e. between the die flag 104 of the stack 20 and the region 155 of the stack 60. The use of such a laminate allows the capacitor 324 to be physically located in the package block 101 adjacent to the semiconductor die 102, since the filtering function of such placement is most effective because the internally mounted components, such as the capacitor 324, have lower parasitic inductance and parasitic resistance.

Fig. 5 is a partial isometric view of yet another embodiment of an integrated circuit 100 including a semiconductor package block 101 formed with a stack of layers 20, 40, and 60, a sealing block 108, and a semiconductor die 102 and 103.

The semiconductor die 102 is formed with bonding regions 382 and 384, while the semiconductor die 103 is formed with a bonding region 383 that is used to make electrical contacts. In one embodiment, bonding regions 382-384 are formed as bonding pads made of a standard semiconductor interconnect material such as aluminum or copper. In another embodiment, bonding regions 382-384 may comprise a combination of layers such as solder balls, copper plating or solder.

To provide external electrical connections, stack 60 is formed with an internal connection region, such as stack region 380, which electrically connects bonding region 382 and wire 390, and stack region 381 electrically connects bonding region 383-. The electrical connection may be achieved using standard thermocompression or ultrasonic bonding processes or solder reflow processes. The stack 60 is preferably made thin so that it is flexible enough to facilitate bonding and has a small feature size compared to integrated circuit bonding features. In a certain embodiment, the thickness of the stack 60 is about 50 microns.

Note that the stack 60 provides electrical connections not only between the semiconductor die and package leads, but also between semiconductor dies disposed in the same package. Furthermore, the bond with the laminate region 380-381 avoids the need for standard wire bond wire looping, and thus has low parasitic inductance and high operating frequency. In addition, large currents are easily supplied, and can be reliably handled by merely making a sufficiently wide current lamination area, thus avoiding the need for multiple bonding wires or larger bonding wires. In fact, by forming the stack 60 of suitable feature sizes, small feature sizes can be combined with high current capability and low manufacturing cost in the same structure.

In summary, the present invention provides a low cost integrated circuit and package that economically combines small feature size with high current capability. A leadframe for mounting a semiconductor die is formed with a first laminate layer having a pattern of integrated circuit leads on a lower surface of the laminate layer. The lower surface of the second laminate layer is in contact with the upper surface of the first laminate layer to electrically couple the leads and the semiconductor die. The present invention provides a low cost structure combining high lead density and high current capability, providing higher quality lead locking, cross-interconnect and electromagnetic shielding. By forming the second stack in the desired bonding pattern, the need for separate bond wires is avoided, resulting in higher performance and lower cost compared to other structures.

Claims (10)

1. An integrated circuit, characterized in that

A first semiconductor die; and

a lead frame, comprising:

a first laminate layer having an exposed surface formed as a lead of an integrated circuit and a second surface for mounting a first semiconductor die, an

A second laminate layer having a bottom surface in contact with the second surface of the first laminate layer to electrically couple the leads to the first semiconductor die.

2. The integrated circuit of claim 1, further characterized by comprising a mold compound for encapsulating the first semiconductor die.

3. The integrated circuit of claim 2, wherein the second stack forms a mold lock of the mold compound.

4. The integrated circuit of claim 3, wherein the second laminate extends outwardly from the leads to form a mask, and the mold compound covers the mask.

5. The integrated circuit of claim 1, wherein the bottom surface of the first semiconductor die is disposed on a second surface of the first laminate layer, the second laminate layer having a thickness greater than a thickness of the first semiconductor die.

6. The integrated circuit of claim 1, further characterized by a second semiconductor die mounted on the leadframe.

7. The integrated circuit of claim 6, wherein one of the first interconnects of the first stack is electrically coupled to a bond pad of the first semiconductor die through the second stack.

8. The integrated circuit of claim 5, wherein the leadframe further comprises a third laminate layer, the first surface of which is in contact with the second surface of the second laminate layer and is patterned with bonding tape in contact with the bonding pads of the first semiconductor die.

9. A semiconductor device, characterized in that:

a semiconductor die; and

a leadframe formed as stacked conductive stacks, wherein a first of the stacked conductive stacks is patterned to form an outer lead of the semiconductor device and has a surface for mounting a semiconductor die, wherein a second of the stacked conductive stacks has a portion that contacts a bond pad of the semiconductor die and is coupled to the outer lead by a third of the stacked conductive stacks.

10. A semiconductor package block for receiving a semiconductor die, characterized by a lead frame comprising:

a first conductive stack having an exposed surface patterned for making external electrical connections, and a second surface for mounting a semiconductor die; and

a second conductive stack in contact with the second surface of the first conductive stack and providing a signal path from the semiconductor die to the first conductive stack.