HK1063376A - Eeprom cell with asymmetric thin window - Google Patents

Description

EEPROM cell with asymmetric thin window

Technical Field

The invention relates to a floating gate nonvolatile electrically rewritable memory cell, in particular to a subminiature memory cell and a manufacturing method thereof.

Background

Nonvolatile memory cells typically pass charge to the floating gate through an oxide window, the logic state of the memory cell is determined by the presence or absence of charge on the floating gate, and the rate of charge transfer to the floating gate is dependent on the applied voltage potential, the relative size of the oxide window, the thickness of the oxide window, and the like.

Non-volatile memory cells require more than one reference off-potential Vcc source voltage in operation, and at least one high program and erase voltage Vpp, for example, about 15-16 volts, typically two or three times the magnitude of Vcc. As integrated circuit devices such as cells containing memory transistors and select transistors are scaled down, not only are the dimensions of their successive elements reduced, but their applied voltages must also be reduced in order to keep the devices operating properly without damaging the scaled devices. In a non-volatile memory cell, the program and erase voltages Vpp cannot be lowered excessively because it must remain above Vcc by some predetermined large margin. By designing the cell such that it requires a relatively high Vpp voltage to cause program and erase operations, the chance of the cell being inadvertently programmed or erased by a standard Vcc voltage rail may be reduced, particularly when small devices that employ a relatively low reference voltage Vcc1 interface with large devices that employ a relatively higher reference voltage Vcc 2. If the voltage level of the larger reference Vcc2 is comparable to the program and erase voltages Vpp of the smaller device, the data of the memory cells of the smaller device may be inadvertently changed. Therefore, the program and erase voltages Vpp for smaller devices must remain above the margin of safety of Vcc1 or Vcc 2.

As cell sizes shrink, the effects of the reference voltages Vcc and Vpp expand. Without reducing the magnitude of Vcc and Vpp, the scaled down cells operate as if a higher voltage were applied, resulting in degraded performance and reliability of the cells. In the case of non-volatile memory, since the Vpp value of scaled memory cells remains relatively high, as the memory cell size shrinks, the effect of the charge transfer oxide window is magnified, e.g., the amount of charge transfer per unit area of the oxide window may remain constant, or even increase as the floating gate, control gate and drain regions shrink, which may result in non-uniform scaling of the memory cell, resulting in a limited amount of allowable scaling. To compensate for the relatively stronger effect of Vpp, it is contemplated that the oxide window size be scaled smaller than the other elements of the cell. However, the minimum oxide window is typically limited by the minimum feature size resolution of the fabrication equipment used to build the memory cell, which places a finite limit on the minimum size achievable by the oxide window that can no longer be scaled down.

Further complicating the scaling of constituent memory cells lies in the complex structure of the cells themselves. It is often desirable for the oxide window to be located between the select transistor and the memory transistor, which requires multiple masking steps in forming the cell, which poses a problem of the limited size of the oxide window when attempting to construct scaled-down non-volatile memory cells.

Referring to the nonvolatile memory transistor of fig. 1, which is an integral part of a memory cell, it is similar to a general MOS transistor in that a source region 11 and a drain region 12 are included in a substrate 15. The region between the source region 11 and the drain region 12 defines the channel region length of the memory transistor. The stacked gate non-volatile memory transistor is characterized by a gate oxide 23 floating on the control gate 21 over the gate 19, and the gate oxide 23 covering the channel region 17 and partially covering the source region 11 and the drain region 12. The floating gate 19 is separated from the control gate 21 by a copoly oxide. A more prominent feature of typical electrically rewritable non-volatile memory cells is the oxide window 27 through which charge can be transferred to the floating gate 19. In effect, the size of the oxide window 27 defines the size of the charge transfer region of the cell. This feature is an obstacle to constructing minimum feature size memory cells, as described below.

Referring to fig. 2, a cross-sectional view along line 2-2 of fig. 1 shows the transistor being built between two opposing field oxide regions 29, the spacing of the field oxide regions 29 defining the width direction of the memory transistor. The floating gate 19 is shown spanning the channel region width and partially covering the field oxide region 29. Likewise, the control gates 21 are formed as polysilicon strips extending perpendicular to the length of the memory transistors. The oxide window 27, which now covers the drain region 12, extends from one field oxide region 29 to the other field oxide region 29.

The cell structure, described more fully in U.S. patent No.5,086,325 assigned to the assignee of the present invention, simplifies the memory transistor structure of the cell by defining the width of the oxide window by the minimum spacing between field oxide regions 29. This structure has historically resulted in cells of small size, but as cell sizes are further scaled down, the field oxide regions 29 must be brought closer together to maintain the proportional performance of the cell. It has been found that due to the close proximity of the field oxide regions 29, oxide wrinkles can occur which deform the window oxide, leading to premature cell failure, thereby limiting the amount of scaling allowed by the structure.

Referring to fig. 3, U.S. patent No.5,904,524 addresses this problem by moving its oxide window 31 out from between the field oxide regions 33 and 35 that define the cell channel width. The cell is defined by three active regions 41, 43 and 45. The source, drain and channel regions of the memory cell are all in the active region 43, the control gate 47 is coupled to the floating gate 49 in the active region 41, and the floating gate 49 covers the channel region in the active region 43 and covers the oxide window 31 in the active region 45. Since the channel region is in active region 43 and oxide window 31 is not in active region 43, field oxide regions 33 and 35 can be brought closer together to form a small width channel without wrinkling oxide window 31. The' 524 patent states that it is easier to scale down the memory cell because the oxide window 31 is no longer affected by narrowing the cell trench width. But this cell structure requires that three adjacent active regions 41, 43 and 45 be isolated with intervening field oxide regions 33 and 35, and is thus not an extremely compact structure.

Referring to fig. 4, a different cell structure, discussed in U.S. application specific No.5,066,992, assigned to the assignee of the present invention, shows a memory cell having one side of oxide window 51 aligned with source region gate 53 and control gate 55. The width of the oxide window 51 still extends across the channel width and thus the cell miniaturization is still subject to the proximity of surrounding field oxide regions (not shown). However, by placing the floating gate 53 and the control gate 55, the length of the oxide window 51 can be adjusted because the floating gate 53 is formed using a mask that defines the floating gate 53 and the underlying oxide window 51, automatically aligning the oxide window 51 in place. The process facilitates cell scaling, and in particular oxide window scaling along the length direction.

A similar approach is proposed in us patent No.5,953,254, but the oxide window does not extend across the entire cell width to two field oxide regions that can be opposite, as described in the' 254 patent, which improves the capacitive coupling of the floating gate if the oxide window is not bounded by either field oxide region, but this necessarily increases the allowable distance between the field oxide regions, since it must be kept separate from the oxide window. To reduce the width dimension and maintain normal scaling performance, this approach opposes bringing the opposing field oxide regions closer together.

U.S. patent No.5,972,752 proposes a non-volatile memory cell whose oxide window can be made smaller than the minimum feature size resolution possible with the fabrication equipment used. This is said to scale the oxide window down to obtain smaller cells. Referring to fig. 5, the memory cell of the' 751 patent has a source region 61, a drain region 63, and a channel region 65 therebetween. Floating gate 67 and control gate 69 overlie channel region 65 and partially overlie lift-off block 71. Gate oxide 75 includes an oxide window 77 that extends across the cell width from one field oxide (not shown) to the opposite field oxide region (not shown). However, by using lift-off block 71 to construct a highly controlled mask for the oxide window, the length of oxide window 77 can be made smaller than the minimum dimensional resolution of the fabrication tool.

Referring to fig. 6, the' 752 patent teaches first laying up the lift-off blocks 71 over the source and drain regions 61 and 63 and then growing the oxide 73 on the exposed surfaces, including the exposed sides of the lift-off blocks 71 and the exposed surface of the substrate 79. The structure is then covered with a layer of original insulating material that is etched down to form sidewall spacers 81. the sidewall spacers 81 cover most of the oxide layer 73 in the channel region, but a narrow region of the oxide layer 73 is exposed between the sidewall spacers 81. the narrow strip of oxide is etched back into the oxide window 77. In fig. 7, sidewall spacers 81 are removed, first and second polysilicon layers 67 and 69 are applied, and these polysilicon layers are etched to form floating gate 67 and control gate 69 as shown in fig. 5.

Although the length dimension of the oxide window of the cell of the' 752 patent is less than that achievable with the minimum feature size resolution of the device, it requires a much more complex fabrication process. Furthermore, the lift-off necessary for scaled-down oxide windows results in memory cells with irregular profiles, further degrading cell integrity due to the increased number of fabrication process layers. In addition, the degradation of the oxide window due to the requirement of isolating oxide regions close together to reduce the cell width is not addressed.

It is an object of the present invention to provide a memory cell structure that facilitates scaling down its charge transfer region without requiring complex processing steps.

It is another object of the present invention to provide a method of forming a memory cell that allows isolated field oxide regions defining the cell width to be closely packed together for proper scaling without degrading the oxide window.

It is a further object of this invention to provide a method of fabricating a memory cell having a charge transfer region of a size less than that achievable with the minimum feature size resolution of the fabrication equipment used to fabricate the cell.

Disclosure of Invention

The above objects are achieved in a method of fabricating a non-volatile memory cell structure in which the size of its oxide window remains limited, but the portion of the oxide window that transfers charge can be reduced to a size less than the minimum feature size resolution of the fabrication equipment used. This is accomplished by positioning a fixed size oxide window that does not extend across the cell width from one field oxide region to another field oxide region, the position of which controls the amount of charge that is allowed to pass through it. This is achieved by forming the oxide window such that a first portion thereof covers only one of the two opposing field oxide window regions and the remaining portion thereof overlies the channel region but does not extend across it, thereby effectively forming a slit in the oxide window, the size of which can be adjusted by shifting the position of the oxide window. All portions of the oxide window constructed above the field oxide region cannot be used to transfer charge to the floating gate, and charge can only be transferred using the portion of the oxide window located in the channel region. Thus, the effective charge transfer region is formed to be smaller than the oxide window and also smaller than the size achievable with the minimum feature size resolution of the fabrication tool. In this approach, the relatively fixed oxide window size does not affect the scaling of the nonvolatile cell, since only a small portion of the oxide window is used for charge transfer. In addition, because the oxide window does not extend across the opposing field oxide regions, the field oxide regions can be abutted together without adversely affecting the charge transfer portion of the oxide window.

It should be noted that the oxide window is generally rectangular when disposed. Typically, the long side of the rectangle extends across the nonvolatile cell width, while the short side is aligned along the cell length. However, to properly control the charge transfer portion of the cell, the preferred apparatus rotates the oxide window 90 degrees so that the long side is aligned along the length of the cell and the short side is aligned along the width of the cell. In this approach, the short sides of the oxide window do not extend across the channel width, making the field oxide regions tighter, if desired.

Brief description of the drawings

Fig. 1 is a cross-sectional view of a prior art stack gate non-volatile memory cell.

Fig. 2 is a cross-sectional view along line 2-2 of the prior art non-volatile memory cell of fig. 1.

Fig. 3 is a perspective view of another prior art memory cell.

Fig. 4 is a cross-sectional view of a prior art memory cell equipped with a select transistor.

Fig. 5-7 illustrate various processing steps for constructing a prior art memory cell having a tunnel oxide length that is less than the minimum resolution achievable by the fabrication equipment used to construct the memory cell.

Fig. 8 and 9 show layout diagrams of the memory cell of the present invention.

Fig. 10 is a perspective view of a partially constructed memory cell of the present invention.

Fig. 11 is a perspective view of a memory cell of the present invention equipped with a select transistor.

Fig. 12 is a cross-sectional view of the memory cell of fig. 8 taken along line 10-10.

Fig. 13 is a cross-sectional view of the memory cell of fig. 8 taken along line 13-13.

Fig. 14-19 illustrate various processing steps for fabricating the memory cell of the present invention.

Fig. 20 is a sectional view of a memory cell of the first embodiment of the present invention.

Fig. 21 is a cross-sectional view of a memory cell of a second embodiment of the present invention.

Best mode for carrying out the invention

Referring to fig. 8, a top view of the layout of the non-volatile memory cell 80 of the present invention is shown. In this example, the memory cell is shown to include a memory transistor 81 in series with a select transistor 82, the active region of the memory cell being drawn with a dashed line 83. As is well known in the art, the active area of an IC is defined as the surface area of a substrate on which active devices, i.e., transistors and resistors, are formed. The active regions are surrounded by insulated field oxide regions 85 a-85 d that serve as barrier walls to provide electrical isolation between the active regions 83. Various forms of field oxide 85 are known in the art, but presently preferred structures implement local oxidation of silicon or LOCOS, field oxide regions 85, it being understood that other field oxide structures, such as shallow isolation (STI), etc., are equally suitable depending on device requirements.

Polysilicon strips 87 and 89 partially cover field oxide region 85 through active region 83 as shown. Typically, the polysilicon strips function as control gates for the transistors, while the uncovered active regions on either side of the polysilicon strips function as source and drain regions for the transistors when appropriately doped. In this example, polysilicon strip 89 forms the control gate of memory transistor 81 and polysilicon strip 87 forms the control gate of select transistor 82. Likewise, cross section 91 of active region 83 functions as the source region of memory transistor 81 and cross section 95 of active region 83 functions as the drain region of select transistor 82. The shaded region 97 of drain region 95 indicates the contact location. The cross section 93 of the active region 83 functions as a drain region of the memory transistor 81 and a source region of the selection transistor 82. Under the polysilicon strips 87 and 89, the width of the select transistor 82 and the memory transistor 81 are defined by the opposing boundaries of the field oxide regions 85a and 85b, which are indicated by arrows 85' and 85 ", respectively.

The active region under the control gate 89 constitutes a channel region of the memory transistor 81. Likewise, polysilicon strip 87 is separated from active region 83 by a gate oxide, and the active region under polysilicon strip 87 constitutes the channel region of select transistor 82. The memory transistor 81 also includes an insulated floating gate 99 under the polysilicon strip 89. The floating gate 99 is also made of polysilicon and is considered floating because it is encapsulated in insulating oxide preventing it from having direct physical and electrical contact with its adjacent conductive elements. For example, insulated above by a copoly oxide (not shown) from the polysilicon strips 89, at the sides by overlying field oxide regions, and below by a gate oxide from the active regions 83.

As described above, data is stored in the memory transistor 81 by moving charge into and out of the floating gate 99, and since the floating gate 99 is sealed, a controlled path must be made to enter another isolated floating gate 99. This controllable path, actually called a "window," is typically built into the gate oxide under the floating gate 99. The window is constructed by scribing a frame region within the gate oxide and thinning the in-frame oxide or forming a thin oxide within the frame. The in-frame oxide is made thin enough to maintain its insulating qualities and its electric field barrier can be overcome by applying a large electric field Vpp without seriously damaging the oxide window 101. With the appropriate amount of Vpp applied, charge is controllably moved into and out of the floating gate 99 through the thin oxide window 101. In the present invention, the construction of the oxide window 101 is of particular interest.

Oxide window 101 is a problem when attempting to scale down the size of nonvolatile memory cell 80, and in particular nonvolatile transistor 81, in general. The amount of charge that is moved through the oxide window depends on several factors including the thickness of the oxide window, its area, and the voltage potential across it, e.g., if the drain-source voltage of the holding transistor is held constant while its channel length dimension is scaled down, the average electric field along the scaled-down channel will be greater, resulting in gain loss and enhanced hot carrier effects. Other problems such as electromigration and punch-through failures also occur. Therefore, the principle of device scaling is that the applied voltage is reduced along with the reduction in device size. In other words, the device is scaled down and the Vcc and Vdd values should be reduced, otherwise the device performance will degrade and the device itself will be damaged.

Unfortunately, to maintain compatibility with other parameter scaling, the voltage across the oxide window generally cannot be scaled down as much as desired. Since Vpp remains relatively high in relation to the physical dimensions of a scaled non-volatile transistor, such as its width, length, oxide window thickness, floating gate size, etc., if Vpp is allowed to decrease at the normal rate of scaling down the physical dimensions and charge concentration of the transistor, the area of the oxide window must be reduced more than necessary to compensate for the relatively larger electric field. Reducing the size of the oxide window limits the amount of charge that can be transferred through it, thus compensating for the higher electric field of the relatively large Vpp value. Reducing the tunnel oxide area under the floating gate also increases the capacitive coupling ratio. For a memory cell with a high coupling ratio, electrons can be transferred from the floating gate to the source/drain regions at a high speed, and thus, the memory cell has better programming characteristics. However, the minimum feature size resolution of the fabrication equipment used to build memory cell 80 limits the minimum size of oxide window 101.

In addition, as the size of the nonvolatile transistor is reduced, the trench width size thereof must be reduced. As described above, the width of the nonvolatile memory transistor 81 is defined by the opposing field oxide regions 85a and 85 b. Thus, as transistor 81 is scaled down, field oxide regions 85a and 85b are required to be close together in order to reduce its width. However, as described above, if the field oxide window crosses from one opposing field oxide region 85a to the other 85b, and the field oxide walls 85a and 85b are too close together, the quality thereof deteriorates.

The present invention solves the above two problems by changing the layout of the oxide window 101. The requirement for the scaled-down oxide window size to be less than the minimum feature size resolution of the fabrication equipment used to produce the non-volatile transistor is due to the fact that the physical dimensions of the non-volatile memory transistor 81 are typically scaled down to the limits of the fabrication equipment, e.g., it is desirable to define the trench length of the transistor as the minimum feature size resolution of the fabrication equipment and correspondingly define all other parameters with the minimum trench length as a calibration reference. As described above, to maintain proper operation, the oxide window 101 must be smaller than the memory transistor by a scaling factor. Since the transistor scaling factor is based on the nominal trench length, which is scaled to the minimum feature size resolution of the fabrication tool, the oxide window requires a smaller size than the minimum feature size resolution of the fabrication tool. However, the oxide window 101 is defined as a thin region of oxide, and the minimum size of the thin region of oxide 101 is limited to a fixed value determined by the minimum feature size resolution of the fabrication tool.

To compensate for oxide window 101 having a minimum dimension that is limited to a fixed value greater than that required for normal scaling, the present invention arranges for the oxide window 101 to be positioned such that a first region 101A of oxide window 101 partially extends into the channel region of memory transistor 81 and a second region 101B overlies field oxide region 85B. The first region 101A constitutes a charge transfer region, and the second region 101B constitutes a non-charge transfer region 101B of the oxide window 101. The oxide window 101 contacts only one field oxide region 85b so that it is not adversely affected by the close proximity of the opposing field oxide regions 85a and 85b when scaling the width of the memory transistor 81. Furthermore, the charge transfer region 101A is located entirely within the channel region of the memory transistor 81, without contacting either the source region 91, the drain region 93, or the opposing field oxide region 85A. Although the oxide window 101 still has a large size limited by the minimum feature size resolution of the fabrication equipment, by limiting the area of its charge transfer region 101A, the effective size of the oxide window is reduced. The non-charge transfer region 101B of the oxide window 101 is unable to transfer charge because it resides entirely within the insulated field oxide region 85B. If it is desired to further shrink the charge transfer region 101A of the field oxide window 101, the field oxide window 101 may be moved further towards the field oxide region 85 b. Similarly, to increase the charge transfer region 101A, the oxide window 101 is moved further toward the opposite field oxide region 85A, but preferably the oxide window 101 is not in contact with the opposite field oxide region 85A. It should be understood that the exact area of the charge transfer region 101A may not be completely determined due to slight variations in the oxide window 101A caused by alignment errors, but that such misalignment is typically taken into account when designing the cell layout, and the resulting structure remains within the spirit of the present invention. Note also that the charge transfer window 101 is rectangular with the long side parallel to the length dimension of the transistor and the short side of the oxide window parallel to the width dimension of the channel, which facilitates placement of the oxide window without extending the channel width.

Referring to fig. 9, all elements similar to those of fig. 8 are numbered identically and are described above. In this example, the oxide window 101 is moved closer to the field oxide 85b, resulting in a smaller charge transfer region 101A, thereby further scaling the physical parameters of the nonvolatile memory cell 80 without facing any limitations on the minimum achievable size from the oxide window 101.

Referring to fig. 10, there is shown a perspective view of a partially fabricated memory transistor 81 of the present invention. All elements similar to those of fig. 8 are labeled with the same reference numerals and are described above. The illustrated active region 83 comprises doped regions diffused into the substrate 111 that are optionally included to adjust the threshold voltage of the transistor and to assist in shaping the electric field in the active region. The field oxide regions 85a and 85b, which define the width of the active region 83, are not drawn to scale for illustrating their LOCOS structure, which is characterized in that the field oxide regions narrow to a point at the boundary of the active region 83. This narrowing of the field oxide region 85 is commonly referred to as a "bird's beak". Gate oxide 103 is shown over active region 83. As shown in fig. 8, the gate oxide 103 separates the floating gate 99 from the channel region defined by the surface of the active region 83. Dashed lines 107 and 109 indicate that the source region 91 and drain region 93 encroach into the channel region under the gate oxide 103, respectively, as a result of the expansion of the various heating stages in the fabrication process.

As shown, oxide window 101 is located partially in the channel region of active region 83 and partially over field oxide region 85 b. The oxide window 101 is characterized by an etching process (e.g., wet etch, dry etch, or combination etch) that thins the oxide of the gate oxide 103 and field oxide region 85b within the target frame area and then builds up a thin layer of oxide within the target frame area. The portion of the oxide window 101 located in the channel region is its charge transfer region 101A, characterized by a thin oxide 105, preferably less than 80 , suitable for Fowler, Nordheim tunneling of charges. The portion of the oxide window 101 located in the field oxide region 85B is its non-charge transfer region 101B.

Referring to fig. 11, a cross-sectional perspective view of the memory cell 80 of fig. 8 is illustrated, taken along arrow 10. Tunnel region 115 is under gate oxide 103 and gate oxide 103 is under floating gate 99; tunnel region 117 is under gate oxide 119 and gate oxide 119 is under control gate 87. Within gate oxide 103, charge transfer region 101A is shown featuring a thin region of oxide, which forms a recess in gate oxide 103 that extends along the layer covering charge transfer region 101A. For example, the floating gate 99, its poly oxide 113 and the control gate 89 have a similar recess in their structure. The memory cell 80 of fig. 11 shows the floating gate 99 partially overlying the field oxide region 85a and the control gate 89 extending beyond the field oxide region 85a, laid out as in the example of fig. 8. Likewise, the control gate 87 of select transistor 82 also extends beyond field oxide region 85 a. In addition, conductive regions 91, 93, and 95 are all shown as comprising doped regions within substrate 111. If desired, the charge transfer region 101A may be doped by a suitable amount to increase the concentration under the tunnel oxide.

Referring to fig. 12, which is a cross-sectional view of the memory cell of fig. 11, all elements that are similar to those of fig. 11 are labeled with the same reference numerals and are described above. Memory cell 80 is shown to include nonvolatile transistor 81 in series with select transistor 82, with region 91 preferably functioning as the source region of nonvolatile transistor 81, region 95 functioning as the drain region of select transistor 87, and region 93 functioning as the drain region of nonvolatile transistor 81 and the source region of select transistor 82. Fig. 12 highlights the push-on structure of the non-volatile transistor 81. The charge transfer region 101A of the illustrated oxide window resides entirely within the channel region defined by the floating gate 99 and the control gate 89. In addition, the oxide window 101 is shown forming a recess 121 in the stack of gate oxide 103, floating gate 99, copoly oxide 113 and control gate 89, the recess being caused by the charge transfer cross section 101A of the oxide window. The copolyoxide 113 includes a dielectric film or a combined dielectric film.

Fig. 13 shows a cross-sectional view of the memory cell of fig. 8 and 11 along arrows 13-13, preferably highlighting the structure of oxide window 101. As shown, control gate 89 spans across opposite field oxide regions 85A and 85B. Similarly, floating gate 99 extends partially across field oxide region 85A to field oxide region 85B, separated from control gate 89 by a copoly oxide 113. The gate oxide 103 separates the floating gate 99 from the active region channel region within the substrate 111. As shown, the oxide window 101 includes a first charge transfer region 101A separating the floating gate 99 from the channel region and a second non-charge transfer region 101B partially spanning the field oxide region 85B. The oxide window 101 creates a recess 121 that extends the stack including the gate oxide 103, floating gate 99, copoly oxide 113 and control gate 89.

Fig. 14-19 illustrate various processing steps for constructing a non-volatile transistor in accordance with the present invention. In fig. 14-19, reference a, as in fig. 14A, indicates a view along arrows 13-13 in fig. 8, while reference B, as in fig. 14B, indicates a view along arrows 10-10 in fig. 7.

Referring to fig. 14, after the surface of substrate 111 is cleaned and polished and any desired well structures are formed, field oxide regions 85 are formed. If desired, a buried N may be built into the substrate 111⁺Regions (not shown) are then buried to define active regions, preferably cells buried at 90keV and 7 degrees including 75As +8.5E11 without rotation.

In fig. 15, a cell oxide or gate oxide 103 is formed, preferably with a thickness of 390 , and then the surface is wet etched to form an opening 131 in the gate oxide 103 through to the substrate 111, as shown in fig. 16. The shape and location of the opening 131 may be defined using the photoresist 104 of the masking step. The opening 131 extends from the active region 83 to the field oxide region 85D.

Referring to fig. 17, a thin layer of oxide is then grown in the opening 131 to form the oxide window 101, the thin layer preferably having a thickness of about 76  a. As previously described, the oxide window 101 includes a first charge transfer region 101A and a second non-charge transfer region 101B. The portion of the thin layer grown in the active region 83 constitutes a first portion 101A and the portion of the thin layer grown in the field oxide region 85B constitutes a second portion.

Referring to fig. 18, a first polysilicon layer 99 is next deposited over gate oxide 103, oxide window 101 and field oxide regions 85A and 85B. The first polysilicon layer 99 may be ion implanted and etched back to extend only partially from the field oxide regions 85A to 85B. To adjust the threshold voltage of the cell, a threshold adjustment implant is made into the channel region through the first polysilicon layer 99, preferably 11B +4E11 at 45keV and 7 degrees.

Referring to fig. 19, a copoly oxide 113 is formed overlying the cell, followed by the application of a second polysilicon layer 89, preferably extending beyond the field oxides 85A and 85B. This second polysilicon layer 89 will act as the control gate for the floating gate cell and also perform an ion implantation to adjust its conductivity. The floating gate polysilicon layer 99 is separated from the control gate polysilicon 89 by a copoly oxide 113. As seen in fig. 19B, the second polysilicon layer is selectively made to extend beyond the length of the first polysilicon layer 99 to rest on the substrate 111. At this point, the oxide 103 separates the second polysilicon layer 89 from the substrate 111. In addition, an optional angled implant 133 may be performed in preparation for building a lightly doped drain structure.

In fig. 20, source region 91 and drain region 93 are formed by vertical implants 135 using control gate 89 and floating gate 99 as masks, preferably 31P +4.0E13 at 25 keV. Fig. 21 shows that the control gate and floating gate may be configured to align with each other if desired, and the source region 91 and drain region 93 may be selectively configured with or without a Lightly Doped Drain (LDD) structure (drain region 93A), in which case both the source region 91 and drain region 93 are self-aligned to the gate stack comprising the floating gate 99 and control gate 89.

Claims (30)

1. A memory cell, comprising:

a field oxide separating two opposite barrier walls to define a width limit of an active region of the memory cell, the field oxide being on a first conductivity type substrate;

diffused into the substrate and extending across the cell in the width direction from one field oxide barrier wall to a source region opposite the field oxide barrier wall;

a drain region diffused into said substrate and spaced apart from said source region between which is defined a channel region, said drain region having opposite ends abutting said opposite field oxide barrier walls, said source and drain regions being of a second conductivity type opposite said first conductivity type;

a first gate oxide overlying the channel;

an oxide window region extending from within said channel to a selected one of said field oxide barriers, said oxide window region not extending to the opposite field oxide barrier nor to said source and drain regions, said oxide window region characterized by a notch in said first gate oxide defining a first region on said channel region and a notch in said selected field oxide barrier defining a second region on said selected field oxide barrier;

a conductive floating gate layer overlying said first gate oxide, said first gate oxide including all of said first regions of said oxide window region.

2. The memory cell of claim 1 wherein said first region lies entirely within said channel region, without contacting said source region, drain region and said opposing field oxide barrier walls, said first gate oxide region within said first region further having a thickness that is conductive to Fowler-Nordheim tunneling.

3. The memory cell of claim 2 wherein said first gate oxide region within said first region has a thickness of less than 80 a 80  a.

4. The memory cell of claim 1 wherein at least one dimension of the oxide window region is defined by a minimum feature size resolution of a fabrication apparatus used to fabricate the memory cell, the first region encompassing an area less than an area of the oxide window.

5. The memory cell of claim 1 further comprising at least one dielectric film over said conductive floating gate layer and a conductive control gate layer over said at least one dielectric film.

6. The memory cell of claim 5 wherein said window region forms a rectangular recess in said floating gate layer, said at least one dielectric film and said control gate layer, said rectangular recess characterized by an upper ridge and a lower plane, said lower plane being entirely enclosed by said upper ridge on three sides within said channel region.

7. The memory cell of claim 5 wherein said conductive control gate layer extends beyond said opposing field oxide barrier walls.

8. The memory cell of claim 7 wherein said conductive floating gate layer partially overlaps said opposing field oxide barrier walls.

9. The memory cell of claim 8 wherein the floating gate layer and the control gate layer are both polysilicon layers.

10. The memory cell of claim 1 wherein said field oxide barrier wall is at least partially embedded in said substrate.

11. A method of fabricating a memory cell having a charge transfer region dimension less than a minimum process feature size defined by fabrication equipment used to fabricate the memory cell, the method comprising:

forming a field oxide region spaced apart with opposing barrier walls defining a width limit of an active region of the memory cell, the field oxide region formed on a first conductivity type substrate;

building a first gate oxide within said active region defined by said opposing field oxide barrier walls;

defining a window region having a dimension equal to said minimum process feature dimension, said window region being defined to partially surround said active region and only partially surround a selected one of said field oxide regions, a portion of said window region within said active region being a charge transfer region and a portion of said window region within said selected field oxide region being a non-charge transfer region;

etching away oxide within said defined window area by an amount substantially equal to the thickness of said first gate oxide, thereby exposing said substrate within said window area;

growing a tunnel oxide within both said charge transporting and non-charge transporting regions of said window region, said tunnel oxide being at most half the thickness of said first gate oxide;

laying a first polysilicon strip layer on said first gate oxide and extending from one of said field oxide barrier walls to an opposite field oxide barrier wall, said first polysilicon strip partially overlapping said two opposite field oxide barrier walls, said first polysilicon strip completely covering said charge transfer region of said window region such that said charge transfer region does not extend to the boundary of said first polysilicon strip;

covering the first polysilicon strip layer with at least one dielectric film;

laying a second polysilicon strip layer on the at least one dielectric film and the first polysilicon strip layer, wherein the second polysilicon strip layer extends beyond the two field oxide regions;

ion implantation is performed on either side of the first and second polysilicon stripe layers to form a source region and a drain region, and the drain region and the source region are far away from the charge transfer region of the window region.

12. The method of claim 11, wherein the oxide in the window region is removed with a wet etch step.

13. The method of claim 11, wherein the oxide in the window region is removed with a dry etch step.

14. The method of claim 11, wherein the oxide in the window region is removed using a combination of wet and dry etch steps.

15. The method of claim 11, defining the window region with a mask.

16. The method of claim 11 wherein said tunnel oxide is grown to a thickness of less than 80 a 80  a within said active region.

17. The method of claim 11 wherein said first gate oxide is less than 400 .

18. The method of claim 11, wherein said first and second polysilicon strips are electrically conductive by respective ion implantation.

19. The method of claim 11 further comprising a threshold adjustment ion implant after said first polysilicon strip layer is deposited and before said second gate oxide is formed, said threshold adjustment ion implant being applied to an active region underlying said first polysilicon strip layer.

20. The method of claim 11, wherein said second polysilicon strip layer has a greater length in said active region than said first polysilicon strip layer, said second polysilicon strip extending to cover a side of said first polysilicon strip and to cover a portion of said active region.

21. The method of claim 18 further comprising implanting ions into the substrate along a side of said first polysilicon strip layer not covered by said second polysilicon strip layer, said ion implantation being applied prior to said ion implantation step used to construct the source and drain regions, said ion implantation being of a lower concentration than the ion implantation step used to construct the source and drain regions.

22. A method of making a scalable non-volatile memory cell, the method comprising:

selecting a scaling factor subject to a minimum process feature size defined by the fabrication equipment used to fabricate the memory cell;

applying the scaling factor to a first positive power supply rail and a larger scaling factor to a second positive power supply rail, the second power supply rail being approximately three times larger than the first power supply rail;

determining a charge transfer region dimension from the second positive power supply rail value, the charge transfer region dimension being less than a minimum process feature size defined by fabrication equipment used to fabricate the memory cell;

after forming a field oxide, which is formed on a first conductivity type substrate, with spaced apart opposing barrier walls defining a width limit of an active region of the memory cell;

forming a first gate oxide within said active region defined by said opposing field oxide barrier walls;

defining a window region having a dimension equal to said minimum process feature dimension, said window region being defined to partially surround said active region and only partially surround a selected one of said field oxide regions, a portion of said window region within said active region being said charge transfer region and a portion of said window region within said selected field oxide region being a non-charge transfer region;

etching away oxide within said defined window region, the amount of oxide etched away being substantially equal to the thickness of said first gate oxide, thereby exposing said substrate within said window region;

growing a tunnel oxide within both said charge transfer and non-charge transfer regions of said window region, said tunnel oxide being at most half the thickness of said first gate oxide;

laying a first poly strip layer over said first gate oxide and extending from one said field oxide barrier wall to an opposite field oxide barrier wall, said first poly strip partially overlapping said two opposite field oxide barrier walls, said first poly strip completely covering said charge transfer region of said window region such that said charge transfer region does not extend to a boundary of said first poly strip, a length scale of said first poly strip layer being orthogonal to said width limit of said memory cell active region, a length of said poly strip being a basis for said selected scaling factor;

covering the first polysilicon strip layer with a second gate oxide;

laying a second polysilicon strip layer over said second gate oxide and said first polysilicon strip layer, said second polysilicon strip layer extending beyond said two field oxide regions;

and performing an ion implantation step to form a source region and a drain region on either side of the first and second polysilicon strip layers, the drain region and the source region being remote from the charge transfer region of the window region.

23. The method of claim 22, wherein the window region is defined by a mask.

24. The method of claim 22 wherein said tunnel oxide is grown to a thickness of less than 80 a 80  a within said active region.

25. The method of claim 22 wherein said first gate oxide is less than 400 .

26. The method of claim 22, wherein said first and second polysilicon strips are each ion implanted to be conductive.

27. The method of claim 22 further comprising, after said first polysilicon strip layer is applied and before said second gate oxide is formed, a threshold adjustment ion implant applied to an active region underlying said first polysilicon strip layer.

28. The method of claim 22 wherein said second polysilicon strip layer is of greater length in said active region than said first polysilicon strip layer, said second polysilicon strip layer extending to cover a side of said first polysilicon strip and to cover a portion of said active region.

29. The method of claim 28 further comprising implanting ions into the substrate along a side of said first polysilicon strip layer covered by said second polysilicon strip layer, said ion implantation prior to applying said ion implantation step to form the source and drain regions, said ion implantation having a lower concentration of ions than said ion implantation step used to form the source and drain regions.

30. The method of claim 22 wherein said ion implantation step to form source and drain regions is a vertical implant, said source and drain regions being self-aligned to said first and second polysilicon strip layers.