HK1064212B - A method and system for forming a semiconductor device - Google Patents

Description

Method and system for manufacturing semiconductor device

Technical Field

The present invention relates generally to the field of semiconductor devices, and more particularly to methods and systems for manufacturing semiconductor devices.

Background

There is a strong trend to reduce the size of existing structures and to make smaller structures. This process is commonly referred to as microfabrication. One area in which micro-fabrication has had a great impact is in the field of microelectronics. In particular, the reduction in size of microelectronic structures generally allows for cheaper structures, higher performance, reduced power consumption and more components included in a given size. While microfabrication has been very active in the electronics industry, it has also been applied to other fields such as biotechnology, optical systems, mechanical systems, sensor devices, and reactors.

One method used in microfabrication processes is imprint lithography (lithodraph). Imprint lithography is commonly used to pattern thin films on substrate materials with high resolution. The patterned film may be dielectric, semiconductor, metal, or organic and can be patterned into a film or a single layer. Imprint lithography is particularly useful for patterning devices in a roll-to-roll environment because it is not as sensitive to flatness as conventional lithography. In addition, imprint lithography has higher yield and is able to handle wider substrates.

In general, the manufacture of electronic devices requires several patterning steps that often must be aligned with each other with an accuracy that approaches or even exceeds the minimum feature size. In conventional lithography, an optical alignment mask is used to ensure alignment between successive patterning steps. While it is possible to employ optical alignment in a roll-to-roll process, it is not practical for several reasons. First, additional complexity is added because the underlying imprint lithography process is not optical. Second, in a roll-to-roll environment, the flatness of the substrate is poor, causing difficulties in the accuracy with which optical alignment can be performed due to depth of field limitations and other optical aberrations. Finally, flexible substrates used in roll-to-roll processes may undergo dimensional changes due to changes in temperature, humidity, or mechanical stress. These contractions or expansions of one patterned layer with respect to the next may make large area alignment impossible.

What is needed, therefore, is a method and system for manufacturing devices that overcomes the above-described problems. The method and system should be simple, cost effective, and capable of being easily adapted to existing technologies. The present invention seeks to meet these needs.

Disclosure of Invention

The present invention includes a method and system for manufacturing a semiconductor device. The present invention relates to the use of a stamp tool to create a three-dimensional resist structure, thereby enabling the transfer of a thin film patterning step to the resist in a single molding step and subsequent exposure thereof in a later processing step. Thus, the alignment between the various successive patterning steps can be determined with the precision with which the stamp tool is manufactured, regardless of expansion or contraction that may occur during the manufacturing process.

A first aspect of the invention includes a method for manufacturing a semiconductor device. The method includes providing a substrate, depositing a first material layer on the substrate, and forming a three-dimensional (3D) resist structure on the substrate, wherein the 3D resist structure includes at least three different vertical heights throughout the structure.

A second aspect of the invention comprises a system for manufacturing a semiconductor device, the system comprising means for depositing a layer of a first material on a flexible substrate, means for depositing a layer of resist on the flexible substrate, means for transferring a 3D pattern to the layer of resist to form a 3D layer of resist on the flexible substrate, and means for using the 3D layer of resist to form an array of crossing points on the flexible substrate.

Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.

Drawings

FIG. 1 is a high level flow chart of a method according to the present invention.

FIGS. 2(a) -2(c) illustrate the formation of a 3D resist structure using a stamp tool.

Fig. 3 is an illustration of a cross-point array configuration.

Fig. 4(a) -4(g) illustrate a first embodiment of using a masking effect to form a cross-point array.

Fig. 5 is a flow chart of a first embodiment of the method according to the invention.

Fig. 6(a) -6(i) illustrate a second embodiment of using two polymers to form a cross-point array.

Fig. 7 is a flow chart of a second embodiment of the method according to the present invention.

Fig. 8 shows experimental results for the case where the substrate was coated with a thin layer of photopolymer, followed by uv transparent molding of PDMS.

Fig. 9 is an illustration of a topography in which a first feature is narrower than a second feature.

Fig. 10(a) -10(1) show a third embodiment for forming a cross-point array using capillary forces.

Fig. 11 is a flow chart according to a third embodiment of the present invention.

Detailed Description

The present invention relates to a method and system for manufacturing a semiconductor device. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications and features of the preferred embodiment and the generic principles described herein will be apparent to those skilled in the art. Thus, the present invention is not to be considered limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.

As shown in the drawings for purposes of illustration, the present invention is a method and system for fabricating a semiconductor device. The present invention relates to the use of a stamp tool to create a three-dimensional resist structure so that multiple patterns can be transferred to the resist in a single molding step and subsequently revealed in a later processing step.

Although the present invention has been described as being used to fabricate semiconductor devices, one of ordinary skill in the art will readily appreciate that the present invention can be used to fabricate other types of devices (e.g., mechanical devices, optical devices, biological devices, etc.) while still not exceeding the spirit and scope of the present invention.

For a better understanding of the invention, reference is made to fig. 1. FIG. 1 is a high level flow chart of a method according to the present invention. First, a substrate is provided, via step 110. The substrate preferably comprises a flexible substrate suitable for use in roll-to-roll manufacturing processes. Next, a layer of material is deposited on the substrate, via step 120. The material preferably comprises an organic material or an inorganic material. Finally, a three-dimensional (3D) resist structure is formed on the first material layer, wherein the 3D resist structure includes a plurality of different vertical heights throughout the structure, via step 130. Preferably, the 3D resist structure is produced using an imprint tool. Since the 3D resist structure comprises a plurality of different vertical heights throughout the structure, this structure can be used to transfer the alignment pattern to the underlying layer based on the subsequent etch step.

As previously mentioned, the present invention relates to the use of a stamp tool to create a 3D resist structure on a flexible substrate. For a clearer understanding of this concept, please refer to fig. 2(a) -2 (c). Fig. 2(a) -2(c) show cross-sections of a 3D resist structure formed using a stamp tool. Fig. 2(a) shows a cross-section of the stamp tool 210 and the layer 214 of unformed resist material. The stamp tool 210 comprises a 3D pattern 212 to be transferred to a resist layer 214. The resist layer 214 may comprise any of a variety of commercially available polymers. For example, polymers from the Norland Optical Adhesive (NOA) polymer family may be employed.

The stamp tool 210 is then brought into contact with the resist layer 214, thereby displacing the resist layer 214 into the 3D pattern 212 of the stamp tool 210. Fig. 2(b) shows a cross-section of the stamp tool 210 that has been brought into contact with the resist layer 214. The displaced resist layer 214 is then cured by ultraviolet lithography or any other suitable curing method. Fig. 2(c) shows a cross section of the formed resist layer 214'.

Furthermore, as can be seen in fig. 2(c), the resist layer 214', i.e. the resist structure, is formed to comprise different vertical heights 216, 218, 220, 222. The respective vertical heights are preferably different, i.e. at least one height differs significantly from another height. These different vertical heights thus enable structure 214' to be used to transfer the alignment pattern to an underlying layer based on a subsequent etch step. These structures are particularly useful in the fabrication of cross-point memory arrays.

Cross point array

The cross-point memory array preferably includes two spaced-apart orthogonal sets of parallel conductors with a semiconductor layer disposed therebetween. Two sets of conductors form row and column electrodes, overlapping in such a way that each row electrode crosses each column electrode at a precise location.

For a more detailed understanding of the cross-point array, please refer to FIG. 3. Fig. 3 is an illustration of a cross-point array configuration 300. At each intersection, a connection is made between the row 310 and column 320 electrodes through a semiconductor layer 330 that functions as a diode in series with a fuse. The diodes in the array are all oriented such that if a common potential is applied between all row electrodes and all column electrodes then all diodes will be biased in the same direction. The fuse element may be implemented as a discrete element that will open when a critical current is passed, or may be combined in the operation of a diode.

One of ordinary skill in the art will readily appreciate that the cross-point array described above can be used to form a wide variety of semiconductor devices, including but not limited to transistors, resistors, capacitors, and the like, without departing from the spirit and scope of the present invention.

Different methods of forming the cross-point array using the above-described 3D resist structure are presented below. A first method utilizes a "masking" effect in conjunction with a 3D structure to form a cross-point array; the second method utilizes two polymers with etch selectivity to each other to form a cross-point array; the third method utilizes the effect of capillary forces to create 3D structures and form cross-point arrays. Although three methods are described, one of ordinary skill in the art will readily appreciate that a 3D resist structure can be utilized in conjunction with a variety of different methods without departing from the spirit and scope of the present invention.

Masking effect

A first method of forming a cross-point array using a 3D resist structure takes into account masking effects. The masking effect is a phenomenon in which, under appropriate conditions, when a thin film is deposited on a surface including a trench having steep sidewalls, the deposited material preferentially gathers on a surface perpendicular to the deposition direction to avoid covering the sidewalls. Deposition at an angle to "mask" one sidewall can sometimes enhance this effect.

To better understand how masking effects are considered in this approach, reference may be made to fig. 4(a) -4(g) in conjunction with the following description. Fig. 4(a) -4(g) illustrate a process of forming a cross-point array using a masking effect. Fig. 4(a) is a side view of a structure 400, the structure 400 including a flexible substrate 410, a first layer of material ("first thin film stack") 415, and a formed 3D resist structure 420.

Once the resist structure is formed, the process is initiated by removing the thinnest layer of the resist structure by an anisotropic etch process, thereby exposing portions of the first thin film stack. Fig. 4(b) shows an exposed portion 415' of the first film stack. Next, the exposed portions of the first film stack are etched using the same or a different etch chemistry, thereby forming a plurality of recesses in the substrate. Fig. 4(c) shows the structure where the recesses 425 have been etched into the substrate 410. It is important that the sidewalls of the recess remain steep and that the depth of the recess be much greater than the thickness of the first thin film stack in this process. Ideally, to enhance the "masking" effect, it is best if the recess in the substrate slightly undercuts (undercut) the first thin-film stack.

Next, the next thinnest layer of the resist structure is etched, exposing a second portion of the first thin film stack. The exposed second portion of the first thin film stack is then etched away. But in this step the etching is stopped when the thin film stack is removed from the substrate below it. Fig. 4(d) shows the exposed substrate 410' after this step.

In a next step, the next thinnest portion of the resist structure is etched, thereby exposing a third portion of the first thin film stack. But in this step the exposed portion of the first thin film stack is not etched. Upon completion of this step, the original resist only leaves a series of isolated islands. Fig. 4(e) shows individual isolated islands of resist 430 and exposed portions 415 "of the first thin film stack.

Next, a second material layer (second thin film stack) is deposited over the entire structure. The second thin film stack preferably includes a semiconductor material and a conductive material. These deposition conditions will be such that small steps caused by the thickness of the first thin film stack will be conformally covered. But the larger step corresponding to the side wall of the recess will not be covered. Fig. 4(f) shows the second thin film stack 435 after deposition.

Finally, the remaining portions of the resist structure are removed, thereby forming an array of cross-points. Fig. 4(g) shows a structure including an array of cross-points 440. Although the cross-point array has been formed at the end of this step, an additional step may include a light clean to remove any residual film on the sidewalls that may create shorts in the final device.

For a better understanding of the above method please see fig. 5. Fig. 5 is a flow chart of the above method according to the invention. First, once the resist structure is formed, a first thinnest layer of the resist structure is anisotropically etched, exposing a first portion of the first thin film stack, via step 510. Next, the exposed first portion of the first thin film stack is etched, thereby forming a plurality of recesses in the substrate, via step 520. The depth of this recess is preferably much greater than the first thin film stack and slightly undercuts the first thin film stack, thereby enhancing the masking effect. Next, the second thinnest layer of resist is etched, exposing a second portion of the first thin film stack, via step 530.

The exposed second portion of the first thin film stack is then etched, via step 540. A second thin film stack is then deposited, via step 550. The second thin film stack preferably includes a semiconductor material and a conductive material. Also, these deposition conditions will be such that small steps caused by the thickness of the first film stack will be covered, while larger steps corresponding to the sidewalls of the recess will be uncovered. Finally, the remaining portions of the resist are removed, via step 560.

Two mask polymers with etch selectivity

A second approach to forming cross-point arrays using 3D resist structures employs two polymers whose properties enable one compound to be etched at a much higher rate than the other under conditions such that for polymers a and B, the etching of polymer "a" does not affect polymer "B" and the etching of polymer "B" does not affect polymer "a". These conditions may include different etch chemistries, different flow rates, different partial pressures, different plasma powers, etc. In addition, both etching methods are preferably anisotropic dry etching.

Although the above-described method is disclosed as being utilized in conjunction with a polymeric material, it will be understood by those of ordinary skill in the art that any material capable of being molded, cast, and then cured can be used in place of a polymeric material as a resist without departing from the spirit and scope of the present invention. For example, spin-on glass (SOG) can be used as the second polymer in the above-described embodiments of the present invention.

For a better understanding of this method, reference may be made to FIGS. 6(a) -6(i) in conjunction with the following description. Fig. 6(a) -6(i) illustrate a process for forming a cross-point array using two polymers. Fig. 6(a) shows a structure 600 that includes a flexible substrate 610, a first layer of material ("first thin film stack"), and a formed 3D resist structure 620, where there are a number of different vertical heights throughout the structure 620. Once the resist structure is formed, the thinnest layer of the resist structure is removed by an anisotropic etch process, thereby exposing portions of the first thin film stack. Fig. 6(b) shows an exposed portion 615' of the first thin film stack.

Next, the exposed portion of the first film stack is etched using the same or a different etch chemistry. Ideally, these etch processes should remove the first thin film stack at a rate similar to or greater than its etch rate for the resist structure. Next, the next thinnest layer of the resist structure is etched, exposing a second portion of the first thin film stack, wherein the second exposed portion of the first thin film stack is adjacent to the area etched in the previous process. Fig. 6(c) shows a second exposed portion 615 "of the first film stack.

Next, a second material layer (second thin film stack) is deposited. The second thin film stack preferably includes a semiconductor material and a conductive material. All exposed surfaces of the substrate, the first thin film stack, and the resist may be coated in this step. Fig. 6(d) shows the deposited second thin film stack 625.

A second polymer is then applied over the second film stack. The coating may be applied by a roll coating process such as gravure coating or by vacuum deposition or vapor deposition. This coating is intended to smooth out the structure and should result in a substantially flat surface covering all of the topography created by the previous steps. Fig. 6(e) shows a second polymer layer 630 overlying the second film layer 625.

The second polymer layer is then etched back until all of the second thin film stack deposited on the initially horizontal resist surface has been revealed. Fig. 6(f) shows the exposed second thin film stack 625' after etching the second polymer layer 630. It should be noted that for this process, the second thin film stack does not have to be used as an etch stop layer since it will be removed.

Next, the second thin film stack is etched from the top surface of the resist structure. It is important that the etching process used herein does not attack the second polymer at a rate higher than the rate at which the second thin film stack is etched. Fig. 6(g) shows the resist exposed portion 620' after the second thin film stack has been etched. Next, the next thinnest area of the resist structure is etched away, exposing another portion of the first thin film stack. This portion of the first film stack is then removed using the same or a different etch process. The set of etching processes used to remove the resist and the first thin film stack preferably does not remove the second thin film stack covered by the second polymer. This can be achieved by making the second polymer layer or the top layer of the second film stack resistant to the etching process used to remove the first film stack and the resist. Fig. 6(h) shows the remaining portion 630 of the second polymer layer.

Finally, the resist structure and the remaining portions of the second polymer layer are removed, thereby forming an array of cross-points. An additional step again includes a light clean to remove any residual film on the sidewalls that may create shorts in the final device. Fig. 6(i) shows a structure including a cross-point array 640.

For a better understanding of the above method please see fig. 7. Fig. 7 is a flow chart of the above method according to the invention. First, once the resist structure is formed, the first thinnest layer of the resist structure is anisotropically etched, exposing a first portion of the first thin film stack, via step 705. Next, the exposed first portion of the first thin film stack is etched, thereby exposing a portion of the substrate, via step 710. Then, the second thinnest layer of resist is etched, exposing a second portion of the first thin film stack, via step 715.

Next, a second thin film stack is deposited, via step 720. The second thin film stack preferably includes a semiconductor material and a conductive material. A second resist layer is then applied over the second thin film stack, via step 725. The second resist layer can preferably be applied by a roll-coating process. Next, the second resist layer is etched, exposing a first portion of the second thin film stack, via step 730. This portion of the second thin film stack is then etched, via step 735. Next, the third thinnest layer of resist is etched, exposing a third portion of the first thin film stack, via step 740. This exposed portion is then etched, via step 745. Finally, the remaining portions of the resist and the second resist layer are removed, via step 750.

Capillary force

A third method of forming a cross-point array using a 3D resist structure takes into account capillary force phenomena. Capillary forces are forces that cause resist material to be more easily drawn into a narrow channel than into a wider channel. For a better understanding of this concept, please see fig. 8.

Fig. 8 shows experimental results in the case where a substrate is coated with a thin photopolymer layer and then molded with an Ultraviolet (UV) transparent mold of PDMS (polydimethylsiloxane). In this example, the stamp included narrow (10 micron) features and wider (100 micron) features with a depth of 5.6 microns. A thin layer of uv-curable polymer (0.9 microns) was applied to the substrate. When the stamp is contacted with a liquid polymer, capillary forces drag most of the polymer into the narrow channels 810, while less polymer is dragged into the wider regions 820. It is also observed that more polymer is dragged into the corner regions 830 of the wider region 820.

For a clearer understanding, please refer to fig. 9. Fig. 9 is an illustration of the first feature 910 being narrower than the second feature 920. Since the first feature 910 is narrower than the second feature 920, capillary forces cause the subsequently deposited polymer material to be more easily drawn to the first feature 910 than to the second feature 920. As a result, since the first feature 910 will include a thicker layer of polymer material than the second feature 920, the underlying material can be easily patterned according to subsequent process steps.

For a better understanding of this method, please refer to FIGS. 10(a) -10(j) in conjunction with the following description. Fig. 10(a) -10(j) illustrate a process of forming a cross-point array using capillary forces. Fig. 10(a) shows an X-X' cross-section (from fig. 9) of a structure comprising a flexible substrate 1010, a first layer of material ("first thin film stack") 1015, and a formed 3D resist structure 1020, wherein a plurality of different vertical heights exist throughout the structure 1020. FIG. 10(b) shows a Y-Y' cross-sectional view of the structure. Also shown in both figures are features 910 corresponding to the topographical features 910 of FIG. 9.

Once the resist structure is formed, the thinnest layer of the resist structure is removed by an anisotropic etch process, thereby exposing a portion of the first thin film stack. Fig. 10(c) shows an X-X 'cross-sectional view of a structure in which a portion 1015' of the first thin film stack has been exposed. FIG. 10(d) shows a Y-Y' cross-sectional view of the structure after the etching process described above.

Next, a second material layer (second thin film stack) is deposited. The second thin film stack preferably includes a semiconductor material and a conductive material. FIGS. 10(e) and 10(f) show cross-sectional views X-X 'and Y-Y' of the structure, respectively, after deposition of the second thin film stack 1030.

A second polymer is then applied over the entire structure. During the application of the second polymer, two techniques are envisaged. With the first technique, the second polymer has a relatively low viscosity and readily wets the resist. The amount of second polymer applied is not sufficient to completely fill the voids present on the structural features, but due to capillary forces, the second polymer will be more easily drawn into the narrow channels. As a result, these regions will be filled to a greater depth than regions where there is greater spacing between the sidewalls.

A second contemplated technique involves uniformly coating the second polymer on the structure by a vapor deposition or vacuum deposition process. Again based on capillary forces, narrow gaps may be obscured before larger gaps. Also, since the process relies on geometric effects rather than etch selectivity, the second polymer may have the same or different chemical composition as the resist structure. FIG. 10(g)10(h) shows X-X 'and Y-Y' cross-sectional views, respectively, of the structure after deposition of the second polymer 1040.

Although the above-described methods are disclosed as being utilized in conjunction with polymeric materials, one of ordinary skill in the art will readily appreciate that a variety of resist compounds can be utilized without departing from the spirit and scope of the present invention.

Once the second polymer is applied, an anisotropic etch is performed to remove the exposed second thin film stack, thereby exposing portions of the first resist. FIGS. 10(i) and 10(j) show X-X 'and Y-Y' cross-sectional views, respectively, of the structure after performing an anisotropic etch. Fig. 10(j) shows the exposed resist 1020'. Next, the resist and the second polymer are removed. The second film stack covers the respective areas at the first film stack and is an array of cross-points. FIGS. 10(k) and 10(l) show X-X 'and Y-Y' cross-sectional views, respectively, of the resulting cross-point array 1050.

For a better understanding of the above method please see fig. 11. Fig. 11 is a flow chart of the above method according to the invention. First, once the resist structure is formed, the first thinnest layer of the resist structure is anisotropically etched, exposing a first portion of the first thin-film stack, via step 1100. The resist structure formed preferably includes at least one feature that is wider than another feature. A second thin film stack is then deposited, via step 1110. The second thin film stack preferably includes a semiconductor material and a conductive material.

Next, a second polymer layer is deposited, via step 1120. An anisotropic etch is then performed to remove the second thin film stack, exposing portions of the resist, via step 1130. Finally, the remaining portions of the resist and second polymer are removed, via step 1140.

Methods and systems for fabricating semiconductor devices have been disclosed. The method and system involve the use of a stamp tool to create a 3D resist structure so that the thin film pattern can be transferred to the resist in a single molding step and subsequently revealed in a later process step.

While the invention has been described in accordance with the various embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.

Claims (9)

1. A method for manufacturing a semiconductor device, comprising:

providing a substrate [410 ];

depositing a first layer of material [415] on the substrate [410 ]; and

a three-dimensional resist structure [420] is formed on a substrate [410], wherein the three-dimensional resist structure [420] includes four different vertical heights throughout the structure [420 ].

2. The method of claim 1, wherein the four different vertical heights comprise at least one height that is substantially different from another height.

3. The method of claim 2, wherein the substrate [410] is a flexible substrate material and the operation of forming the three-dimensional resist structure [420] further comprises:

depositing a resist layer on the first material layer [415 ]; and

the three-dimensional pattern is transferred to a resist layer to form a three-dimensional resist structure [420 ].

4. The method of claim 3, wherein transferring the three-dimensional pattern to the resist layer further comprises:

forming a three-dimensional pattern in the resist layer using a stamp tool; and

the resist layer is cured, thereby forming a three-dimensional resist structure [440 ].

5. The method of claim 4, further comprising:

an array of cross-points is created on the substrate.

6. The method of claim 5, wherein the operation of generating the cross-point array [440] further comprises:

anisotropically etching through a first thinnest layer of the three-dimensional resist structure, thereby exposing a first portion [ 415' ]ofthe first material layer;

etching the exposed first portion [ 415' ] of the first material layer to form a plurality of recesses [425] in the substrate [410], wherein each of the plurality of recesses [425] comprises a depth greater than a thickness of the first material layer [415 ];

etching through a second thinnest layer of the three-dimensional resist structure, thereby exposing a second portion of the first material layer;

etching the exposed second portion of the first material layer;

etching through a third thinnest layer of the three-dimensional resist structure, thereby exposing a third portion [415 "]ofthe first material layer;

depositing a second material layer [435] on the exposed portion of the first material layer and the remaining portion of the three-dimensional resist structure, wherein the second material layer [435] comprises a semiconductor material and a conductive material; and

the remaining portions of the three-dimensional resist structure are removed.

7. The method of claim 5, wherein generating the cross-point array further comprises:

anisotropically etching through a first thinnest layer of the three-dimensional resist structure, thereby exposing a first portion [ 615' ]ofthe first material layer;

etching the exposed first portion [ 615' ] of the first material layer, thereby exposing a portion of the substrate;

etching through a second thinnest layer of the three-dimensional resist structure [620] to expose a second portion [615 "]ofthe first material layer;

depositing a second material layer [625] on the exposed portions of the first material layer and the remaining portions of the three-dimensional resist structure, wherein the second material layer [625] comprises a semiconductor material and a conductive material;

rolling a second resist layer [630] on the second material layer [625], wherein an etch rate of the second resist layer [630] is different from an etch rate of the three-dimensional resist structure;

etching the second resist layer [630] thereby exposing a first portion [ 625' ] of the second material layer;

etching a first portion [ 625' ] of the second material layer;

etching a third thinnest layer of the three-dimensional resist structure, thereby exposing a third portion of the first material layer;

etching a third portion of the first material layer; and

the remaining portions of the three-dimensional resist structure and the remaining portions of the second resist layer [625] are removed.

8. The method of claim 5, wherein the three-dimensional resist structure includes at least one trench [910] that is narrower than another trench, and the operation of creating the cross-point array further comprises:

depositing a second material layer [1030] on the exposed portions [ 1015' ] of the first material layer and the remaining portions of the three-dimensional resist structure, wherein the second material layer [1030] comprises a semiconductor material and a conductive material;

depositing a second resist layer [1040] on the second material layer [1030], wherein the second resist layer [1040] is more easily drawn into the at least one channel [910 ];

anisotropically etching the second material layer [1030], thereby exposing portions of the three-dimensional resist structure; and

the remaining portions of the three-dimensional resist structure and the remaining portions of the second resist layer [1040] are removed.

9. A method for fabricating a semiconductor device, comprising:

providing a flexible substrate material [410 ];

depositing a first layer of material [415] on a flexible substrate [410 ]; and

depositing a resist layer on the first material layer;

forming a three-dimensional pattern in the resist layer using a stamp tool;

curing the resist layer to form a three-dimensional resist structure [420] on the first material layer [415], wherein the three-dimensional resist structure [420] comprises four different vertical heights, at least one of which is significantly different from the other; and

an array of cross-points [440] is created on a flexible substrate [410] using a three-dimensional resist structure [420 ].