HK1066998B - Driving circuit for vacuum fluorescent display - Google Patents

Abstract

The Chinese patent application number is 200410008568.4

Description

Driving circuit of vacuum fluorescent display

Cross Reference to Related Applications

This application claims priority to Japanese patent application Nos. 2003-86464 and 2003-86463, filed 3/26/2003, the contents of which are hereby incorporated by reference.

Technical Field

The invention relates to a driving circuit of a vacuum fluorescent display.

Background

A vacuum fluorescent display (hereinafter, referred to as "VFD") is a self-luminous type display device for displaying a desired pattern by causing a filament to emit thermal electrons by generating heat from a directly heated cathode called a filament by applying a voltage thereto in a vacuum chamber, and causing the thermal electrons to collide with a fluorescent material on an anode (segment) electrode and to emit light by accelerating the thermal electrons using a grid electrode (grid). VFDs have excellent characteristics in terms of visibility, multiple coloring, low operating voltage, reliability (environmental resistance), and the like, and are used in various applications and fields such as automobiles, home appliances, and consumer goods.

For the VFD, as one scheme (1) of applying a voltage to its filament, a pulse driving scheme has been proposed. The pulse drive scheme is a scheme in which a pulse voltage (hereinafter, referred to as "filament pulse voltage") generated by chopping a DC voltage considerably higher than the ordinary rated voltage of the filament is applied to the filament, and has the following features: the light emission state has a small intensity gradient, and the like.

Fig. 13 shows a conventional pulse driving scheme. As shown in the drawing, in the conventional pulse driving scheme, a filament pulse voltage having a constant duty ratio is set in the external oscillator 30 and the external controller 40 according to a reference clock signal (an oscillation clock of the external oscillator 30 or a system clock of the external controller 40), and the filament pulse voltage is continuously applied to the filament 11.

As an example of a VFD drive circuit (hereinafter, referred to as "conventional VFD drive circuit") using a conventional drive scheme such as the external oscillator 30 or the external controller 40, there is a technique disclosed in japanese patent application laid-open No. 2002-108263.

Further, in conventional VFD drive circuits, a mechanism is provided for adjusting the intensity of the VFD 10 so that the VFD 10 is displayed at an appropriate intensity in response to ambient environmental conditions (such as ambient lighting intensity) when the VFD 10 is operated. As a mechanism for adjusting the intensity of the VFD 10, a scheme called "grid dimming" in which the duty ratio of the voltage applied to the grid electrode 12 (hereinafter, referred to as "grid voltage") is adjusted, and a scheme called "anode dimming" in which the duty ratio of the voltage applied to the segment (anode) electrode 13 (hereinafter, referred to as "segment voltage") is adjusted are generally used. Hereinafter, the grid dimming and the anode dimming are collectively referred to as "dimming".

Here, for example, the conventional VFD driving circuit performs dimming according to the reference table of dimmer adjustment data and dimmer values as shown in fig. 12 (a). The dimmer regulation data is data associated with a value that can set the duty cycle of the grid voltage and the segment voltage and is assigned to the VFD driving circuit when dimming is performed by the external device. The dimmer adjustment data may be binary data of a bit number in response to the dimming resolution such as 10-bit binary data (DM0 to DM9) in which DM0 shown in fig. 12(a) is LSB (least significant bit). On the other hand, the dimming value is a value that can be set as a duty ratio as described above, and can be defined as "pulse width TW/pulse period T" using pulse width TW and pulse period T as shown in the waveform diagram in fig. 12 (b).

First task

Fig. 14 shows waveform diagrams of main signals in the case where dimming is performed such that the duty ratios of the grid voltage and the segment voltage are reduced to "1/2", "1/4", and "1/8" in a state where the conventional VFD driving circuit continuously applies the filament pulse voltage having a constant duty ratio to the filament 11. The period in which both the grid voltage and the segment voltage are at the high level H shown in the figure represents a period (hereinafter, referred to as "start period") in which a voltage at which the grid electrode 12 and the segment electrode 13 are simultaneously driven is present, and during this period, it is assumed that the fluorescent material on the driven segment electrode 13 emits light and a desired pattern is displayed on the VFD 10.

Here, during the start-up, during the period in which the filament pulse voltage is at the high level H, the intensity of the VFD 10 is reduced as the voltage difference between the filament and the grid and segment electrodes becomes small. Further, as shown in fig. 14, the start-up period becomes short, and as the duty ratio of the grid voltage and the segment voltage decreases, the ratio of the period in which the filament pulse voltage is at the high level H increases in the start-up period. Thus, the intensity reduction of the VFD 10 as described above becomes quite significant (it is said that the duty cycle "1/8" of the grid voltage and the segment voltage is the minimum threshold).

That is, in the conventional VFD driving circuit, dimming is performed such that the duty ratio of the grid voltage and the segment voltage is reduced in order to reduce the intensity of the VFD 10. In this case, since the occupancy ratio of the period in which the filament pulse voltage is at the high level H is affected to become larger than the reduction rate of the intensity of the VFD 10 based on dimming in the start-up period, the reduction rate of the intensity of the VFD 10 becomes larger. Therefore, with the conventional VFD driving circuit, there is a problem in that when the start-up period is short, the required intensity adjustment is performed by dimming.

The second task is defined as

In the conventional VFD driving circuit, the filament pulse voltage is designed so as to be applied to the filament at a constant duty ratio, because the duty ratio of the filament pulse voltage fluctuates due to the vibration and thermal characteristics of the components for driving the filament, the fluctuation of the filament power supply voltage, and the like. Furthermore, due to fluctuations in the duty cycle, the effective value of the filament pulse voltage exceeds the tolerance defined for its nominal value (e.g., nominal value ± about 10%), and issues arise in that the intensity level of the VFD display deteriorates and the life of the VFD display is shortened due to aging of the filament.

Thus, in recent years, demands for further improvement in reliability have been increased for VFD drive circuits. Therefore, in order to solve these problems, it is necessary to configure a mechanism to finely adjust the duty ratio of the filament pulse voltage with an appropriate timing (to improve resolution). In the conventional VFD display circuit, the resolution associated with adjusting the duty ratio of the filament pulse voltage can be improved by setting the frequency of the reference clock frequency at which the filament pulse voltage is to be set higher.

However, in the conventional VFD driving circuit, power consumption increases, and at the same time, when the frequency of the reference clock signal is set at a too high frequency in order to improve resolution in relation to the duty ratio of the filament voltage, noise of an interfering device such as a radio is generated. On the other hand, when the frequency of the reference clock signal is set at a lower frequency (making the period longer), the frequency of the filament pulse voltage is reduced. Therefore, the frequency of the filament pulse voltage reaches an audible frequency band (typically 20kHZ or less), and acoustic noise is generated from the filament.

As described above, the above-described problem may occur with the method of adjusting the frequency of the reference clock signal. Therefore, a new technique is sought for a mechanism for adjusting the duty cycle of the filament pulse voltage.

Disclosure of Invention

In order to solve the above problems, a main aspect of the present invention proposes a driving circuit for a vacuum fluorescent display having a filament, a grid electrode, and a segment electrode, the driving circuit comprising: a filament driving unit for driving the filament; a grid driving unit for pulse-driving the grid electrode; the segmented driving unit is used for carrying out pulse driving on the segmented electrodes; and a control unit for enabling or disabling an output of the filament driving unit at a predetermined timing, wherein in the case of disabling the output of the filament driving unit, the control unit disables the output of the filament driving circuit for a time period TW shorter than a predetermined time period to at least one of voltages at which the grid electrode and the segment electrode are driven by the grid driving unit and the segment driving unit, respectively.

The control unit can set the pulse width and/or pulse period of the pulse drive signal for pulse-driving the filament according to data received from the outside.

According to the present invention, the convenience and reliability of the driving circuit of the vacuum fluorescent display using the pulse driving scheme of the filament thereof can be improved, thereby enabling to provide a usable driving circuit of the vacuum fluorescent display.

Other features of the present invention will become apparent from an understanding of the following description and the accompanying drawings.

Drawings

The above and other features, aspects, and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where:

FIG. 1 schematically shows a system configuration including a driving circuit for a vacuum fluorescent display according to an embodiment of the present invention;

FIG. 2 is a timing diagram of a data transfer format between an external controller and a vacuum fluorescent display, according to an embodiment of the present invention;

FIG. 3 is a block diagram of a driving circuit of a vacuum fluorescent display according to an embodiment of the present invention;

fig. 4 is a block diagram of a filament pulse control unit according to an embodiment of the present invention;

fig. 5 is a timing diagram illustrating the operation of the filament pulse control unit according to an embodiment of the present invention;

fig. 6 shows a structure of an FPD control unit according to an embodiment of the present invention;

fig. 7 is a timing diagram showing an operation of the FPD control unit according to an embodiment of the present invention;

fig. 8 is a diagram showing a waveform of a pulse drive signal;

FIG. 9 is a reference table relating to the setting of pulse width data according to an embodiment of the present invention;

FIG. 10 is a reference table relating to the setting of pulse period data according to an embodiment of the present invention;

fig. 11 shows the structure of a filament pulse control unit according to an embodiment of the present invention;

fig. 12 is a reference table of dimmer adjustment data and dimmer values;

FIG. 13 shows a conventional driving circuit of a vacuum fluorescent display; and

fig. 14 shows the relationship of the potential of each electrode of the vacuum fluorescent display.

Detailed Description

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

< System Structure >

Fig. 1 schematically shows the structure of a system including a VFD drive circuit 20 as an embodiment of the present invention. As shown, the following will be described: assuming that the grid electrodes 12 and the segment electrodes 13 are driven in a dynamic driving scheme and the duty ratio (pulse width/repetition period) of the grid driving signal driving the grid electrodes 12 is "1/2" (i.e., the grid (column) is two columns), the present invention is implemented as the VFD driving circuit 20 supporting "90" segment outputs.

The VFD driving circuit 20 according to the present invention is not limited to the VFD driving circuit having the above-mentioned number of grids (two columns) and the number of segments (90 segments), and the driving of the grid electrodes 12 and the segment electrodes 13 may be combined with a driving scheme of a dynamic driving scheme or a static driving scheme. For example, in the case of employing the static driving scheme, all column display is performed by the segment electrodes 13 having the same number as the number of segments and one (1) grid electrode 12. In this case, a constant voltage (grid voltage) is applied to the one (1) grid electrode 12.

In a Display Technologies Series such as those written by Sangyo Tosho: an overview of The above dynamic and static Driving schemes is described in Vacuum Fluorescent Display 8.2The Basic Driving Circuits (pages 154-158).

As for the peripheral circuits of the VFD drive circuit, these components will be described in the order of the VFD 10, the external oscillator 30, the external controller 40, and the switching element 50.

The VFD 10 includes: a filament 11, a grid electrode 12 and a segmented (anode) electrode 13. The filament 11 is heated by applying a filament pulse voltage according to a pulse driving scheme via the switching element 50, and emits thermal electrons. The grid electrodes 12 serve as electrodes for selecting columns and accelerating and blocking thermionic electrons emitted by the filament 11. The segment electrodes 13 serve as electrodes for selecting segments. However, a fluorescent material is coated on the surface of the segment electrode 13 in accordance with a pattern to be displayed, and the desired pattern is displayed by accelerating thermal electrons by the grid electrode 12 and causing them to collide with the fluorescent material to cause the fluorescent material to emit light.

Further, in the VFD 10, for each column, a lead wire is individually drawn out from the grid electrode 12, while a lead wire that internally connects the segments corresponding to each column to each other is drawn out from the segment electrode 13. These leads, drawn from the grid electrodes 12 and segment electrodes 13, are connected to respective output terminals of the VFD driving circuit 20 (grid output terminals G1-G2, and segment output terminals S1-S45).

The external oscillator 30 is an RC oscillator including a resistor R, a capacitance element C, and the like, and constitutes an RC oscillation circuit by being connected to the oscillator terminals (OSCI terminal, OSCO terminal) of the VFD driving circuit 20. The external oscillator 30 may be a quartz crystal oscillator or a ceramic vibrator each having a prescribed oscillation frequency, and may be configured as a self-driven oscillation unit crystal or a ceramic oscillation circuit. Further, the external oscillator 30 may be an external driving oscillation unit that supplies a clock signal for external driving oscillation to the VFD driving circuit 20.

The external controller 40 is a device such as a microcomputer that does not include any VFD driving components, is connected to the VFD driving circuit 20 through a data bus for transferring serial data, and transfers signals required for driving the VFD 10 to the VFD driving circuit 20 in a predetermined data transfer format. The data transfer between the external controller 40 and the VFD driving circuit 20 is not limited to the serial data transfer described above, but may be a parallel data transfer.

The switching element 50 is a P-channel MOS type FET (field effect transistor) whose gate terminal is connected to the FPCON terminal of the VFD driving circuit 20, and outputs a pulse driving signal described later. The switching element 50 is not limited to the P-channel MOS type FET, and for example, an N-channel MOS type FET may be used, and further, an N-channel MOS type FET and a P-channel MOS type FET combined together may be used. In addition, the switching element 50 generates a filament pulse voltage to be applied to the filament 11 of the VFD 10 from the filament power voltage VFL by performing an on/off operation in response to a pulse driving signal supplied from the FPCON terminal of the VFD driving circuit 20.

The FRR terminal of the VFD driving circuit 20 shown in fig. 1 is an input terminal for setting the polarity of the pulse driving signal output from the FPCON terminal in response to the input/output characteristics of the switching element 50, and for example, as shown in fig. 1, in the case of using a P-channel MOS type FET as the switching element 50, the FRR terminal is connected to the power supply voltage VDD (high level "H" -fixed). Further, in the case of using an N-channel MOS type FET as the switching element 50, the FRR terminal is connected to "ground" (low level "L" -fixed).

Fig. 2 shows a timing diagram of a data transfer format between the external controller and the VFD driving circuit 20. As shown, the data transfer format has a sequence related to the grid electrode G1 (hereinafter, referred to as "G1 sequence") and a sequence related to the grid electrode G2 (hereinafter, referred to as "G2 sequence"). The data transfer format is not limited to the above format, and the G1 sequence and the G2 sequence may be simultaneously performed.

The G1 and G2 sequences will be schematically described.

First, in the G1 sequence, the external controller 40 transmits a bus address (8 bits) given to the VFD driving circuit 20 together with the synchronous clock signal CL. The VFD driving circuit 20 recognizes whether the received address is a bus address given to the circuit 20 itself. Then, when the circuit 20 recognizes a bus address as a bus address given to the circuit 20 itself, the circuit 20 receives a control command (control data or the like, described later) transmitted in addition to the reception bus address from the external controller 40 as a control command of the circuit 20 itself. As described above, the bus address is a specific address given to each corresponding IC, and in an embodiment where the external controller 40 is connected to a plurality of ICs on the same bus, the bus address is used for the external controller 40 to control the plurality of ICs on the same bus.

Next, the external controller 40 puts the VFD driving circuit 20 in an enabled (selected) state by asserting (putting it in an H level) the chip enable signal CE, and then transmits 45-bit display data (D1 to D45) for the grid electrode G1, 16-bit control data for each control of the VFD driving circuit 20, and the like. As the 16-bit control data, 10-bit dimmer adjustment data (DM0 to DM9) are stored as data for adjusting the intensity of the VFD 10, a gate identifier DD (for example, "1" indicates the grid electrode G1, and "0" indicates the grid electrode G2), and the like. Accordingly, the external controller 40 puts the VFD driving circuit 20 in a disabled (unselected) state by negating (putting it at the L level) the chip enable signal CE, and thus, terminates the transmission of the synchronous clock signal CL, thereby terminating the G1 sequence.

On the other hand, in the G2 series, 45-bit display data (D46 to D90) relating to the grid electrode G2 is transmitted in the same process as the above-described G1 series. In the G2 sequence, the control data transmitted from the VFD driving circuit 20 includes FPD (filament pulse disable) setting data, 7-bit pulse period data Cn (C0 to C6), 4-bit pulse width data Wn (W0 to W3), and the like, which are described later.

< VFD drive Circuit >

Fig. 3 shows a block diagram of a VFD driving circuit 20 according to the present invention for a pulse driving scheme.

The VFD driving circuit 20 includes an interface unit 201, an oscillation circuit 202, a driving circuit 203, a timing generator 204, a shift register 205, a control register 206, a latch circuit 207, a multiplexer 208, a segment driver 209, a gate driver 210, a dimmer control unit 211, and a filament pulse control unit 212.

The interface unit 201 is an interface unit for transmitting/receiving data as shown in fig. 2 with the external control 40.

The oscillator circuit 202 generates the reference clock signal for the VFD driving circuit 20 by connecting the external oscillator 30 to terminals (OSCI, OSCO) for the oscillator. This reference clock signal is divided by a division circuit 203 into a predetermined division number and supplied to a timing generator 204. The frequency of the reference clock signal (oscillating clock) is set at or above the audio band so that no acoustic noise is generated at the filament 11, while the frequency is set below a predetermined upper limit frequency in consideration of the power consumption of the VFD driving circuit and the influence of radio noise.

The timing generator 204 outputs a signal (hereinafter, referred to as "internal clock signal a") for determining the timing or the like of a signal (hereinafter, referred to as "grid drive signal") that drives the grid electrodes G1 to G2, a signal (hereinafter, referred to as "internal clock signal B") for determining the timing of a later-described pulse drive signal in the filament pulse control unit 212, and the like, according to the signal supplied from the division circuit 203.

The shift register 205 converts 45-bit display data (D1 to D45 or D46 to D90) and 16-bit control data (dimmer adjustment data (DM0 to DM9) or the like) received by the interface unit 201 for each of the above-described G1 and G2 sequences, respectively, into pulse data, and supplies the pulse data to the control register 206, the latch circuit 207, the filament pulse control unit 212, or the like. The 16-bit control data includes dimmer adjustment data, FPD setting data, pulse width data, pulse period data, grid identifier DD, and the like.

The control register 206 stores 32-bit (16 bits × 2) control data supplied from the shift register 205. The dimmer adjustment data (DM0 to DM9) included in the control data are supplied to the dimmer control unit 211.

The latch circuit 207 holds 45-bit display data related to the grid electrode G1 and 45-bit display data related to the grid electrode G2, which are supplied from the shift register 205. That is, the latch circuit 207 holds 90-bit display data for each of the repetitive cycles related to the driving of the grid electrodes G1 and G2.

The multiplexer 208 selects 45-bit display data related to the grid electrode G1 or G2 to be driven among the 90-bit display data held by the latch circuit 207 and supplies it to the segment driver 209 at a timing for driving each of the grid electrodes G1 and G2.

The segment driver 209 forms signals for driving the segment electrodes S1 to S45 according to the 45-bit display data selected and supplied by the multiplexer 208, and outputs them to the segment electrodes S1 to S45. The signal for driving the segment electrodes S1 to S45 may be a voltage to be applied to the segment electrodes S1 to S45 (hereinafter, referred to as "segment voltage") or a control signal to be supplied to a driving element interposed between the segment driver 209 and the segment electrodes S1 to S45 (hereinafter, the segment voltage and the control signal are collectively referred to as "segment driving signal").

The grid driver 210 forms a grid driving signal from the internal clock signal a supplied from the timing generator 204, and outputs it to the grid electrodes G1 to G2. A signal for driving the grid electrodes G1 to G2 may be applied as a voltage (hereinafter, referred to as a "grid voltage") to the grid electrodes G1 to G2, or a control signal to be supplied to a driving element interposed between the grid driver 210 and the grid electrodes G1 to G2 (hereinafter, the grid voltage and the control signal are collectively referred to as a "grid driving signal").

The dimmer control unit 211 adjusts the duty ratios of the grid driving signal and the segment driving signal according to the dimmer adjustment data (DM0 to DM9) provided by the control detector 206.

The filament pulse control unit 212 forms a pulse drive signal for pulse-driving the filament 11 based on the internal clock signal B supplied from the timing generator 204, and outputs it to the switching element 50. The filament pulse control unit 212 sets the polarity of the pulse drive signal according to the signal supplied from the FPR terminal. For example, when the FPR terminal is at a low level "L", the pulse driving signal has a waveform shown in fig. 8.

The VFD driving circuit 20 according to the present invention has a function of enabling or disabling the pulse driving signal output to the switching element 50 at an appropriate timing. This function is mainly implemented at the filament pulse control unit 212. The functions provided by the pulse control unit 212 will be described in detail below.

< first embodiment >

Filament pulse control unit

As a first embodiment according to the present invention, in the case of invalidating the pulse driving signal, the filament pulse control unit 212 has a function of invalidating the grid electrode 12 and the segment electrode 13 only for a period of time in which they are at a voltage for driving them (hereinafter, referred to as a "start-up period").

Fig. 4 shows a schematic block diagram of the filament control unit 212 as a first embodiment according to the present invention.

As shown, the filament pulse control unit 212 includes a pulse drive signal generation unit 70, an FPD (filament pulse disable) control unit 60, and a pulse drive signal polarity setting unit 110.

The pulse driving signal generating unit 70 generates a pulse driving signal having a predetermined duty ratio according to the internal clock signal B supplied from the timing generator 204.

The FDD control unit 60 includes: an FPDIS signal generating unit 80 for generating a signal (hereinafter, referred to as "FPDIS signal") for setting a period of time during which the pulse driving signal is deactivated; a nand element 90 as a unit capable of setting the validity and invalidity of the FPDIS signal in response to the FPD setting signal received from the external controller 40; and an and element 100 as a unit capable of setting the assertion and non-assertion of the pulse drive signal generated by the pulse drive signal generation unit 70 in response to the output of the nand element 90.

The FPD setting data represents data capable of setting its own function as active or inactive to make the pulse driving signal according to the present invention inactive only for the start-up period, and for example, may be data capable of setting the active or inactive of the FPDIS signal at the nand element 90 as described above. The FPD setting data is set so that when it is at the high level H, the data makes the pulse driving signal invalid only for the start-up period, and when it is at the low level L, the data makes the pulse driving signal valid regardless of the start-up period.

The FPD control unit 60 according to the above-described structure invalidates the pulse drive signal generated by the pulse drive signal generator 70 by fixing it at a predetermined level (e.g., high level) for a start-up period when the FPD setting data received from the external controller 40 is set at the high level H. The FPD control unit 60 is not limited to the above configuration and may be a configuration capable of implementing the above logic.

The pulse driving signal polarity setting unit 110 includes an exclusive or element, and sets the polarity of the pulse driving signal in response to the signal level input to the FPR terminal. As shown in the figure, in the case of employing the P-channel type FET as the switching element 50, the pulse driving signal polarity setting unit 110 sets the polarity of the pulse driving signal output from the FPCON terminal to a low level L when the P-channel MOS type FET is turned on, and to a high level H when the P-channel MOS type FET is turned off. The pulse driving signal polarity setting unit 110 is not limited to the exclusive or element, and may be other elements capable of implementing the above-described logic.

Fig. 5 shows a timing chart illustrating the operation of the filament pulse control unit 212 having the above-described structure.

First, as the waveform diagrams shown in fig. 5(a) and (B), the following case is assumed: dimming is performed at the VFD driving circuit 20 to reduce the duty ratios of the grid driving signal and the segment driving signal to "1/4", "1/8", "1/16".

Here, since the FPD setting data (fig. 5(D)) is at the "low" level in the period 1T shown in fig. 5, the FPDIS signal (fig. 5(C)) is invalidated, and the output of the nand element 90 (fig. 5(E)) is at the high level H. Therefore, even for the start-up period (Ta), the pulse drive signal (fig. 5(F)) generated at the pulse drive signal generator 70 is validated and supplied to the switching element 50 through the and element 100 (fig. 5(G)) and the xor element 110 (fig. 5 (H)).

On the other hand, since the FPD setting data (fig. 5(D)) is at the high level H in the periods 2T, 3T, the FPDIS signal (fig. 5(C)) is made active, and the output of the nand element (fig. 5(E)) is made at the low level L in the period of the pulse width of the FPDIS signal (fig. 5 (C)). Therefore, the pulse drive signal (fig. 5(F)) generated at the pulse drive signal generation unit 70 is invalidated in the start-up period (Tb, Tc), and supplied to the switching element 50 at a logic value (high level: fig. 5(H)) that turns off the switching element 50.

In this manner, when the period of time during which both the grid electrode 12 and the segment electrode 13 are at the voltage for driving them is short (e.g., when the voltage period is approximately equal to 1/8 or less of one (1) period), the VFD driving circuit 20 can perform the required intensity adjustment by dimming by making the potential difference between the filament 11 and the grid electrode 12 and the segment electrode 13 constant during that period of time. Therefore, the convenience of the circuit can be improved.

Further, the VFD driving circuit 20 may set the above-described function of itself to be valid or invalid according to the FPD setting data, such as checking the display intensity of the VFD 10 from the external controller 40. Therefore, the convenience of the circuit can be further improved.

FPDIS signal generating unit

The FPDIS signal generation unit 80 can generate a signal having a pulse width in response to a dimmer value corresponding to dimmer adjustment data (a value that can be set to a duty ratio of the grid driving signal and the segment driving signal) as the FPDIS signal according to the dimmer adjustment data received from the external controller 40.

The FPDIS signal generating unit 80 may be implemented as a circuit structure shown in fig. 6. The embodiment of the FPDIS signal generating unit 80 shown in fig. 6 will be described as necessary using a timing diagram of main signals of the FPDIS signal generating unit 80 shown in fig. 7.

The FPDIS signal generation unit 80 includes a latch unit 801, a comparison unit 802, a count unit 803, and a signal generation unit 804.

The latch unit 801 includes a D flip-flop, and latches dimmer adjustment data (DM0 to DM9) received from the external controller 40 as information for generating the FPDIS signal (fig. 7 (E)). For example, as shown in fig. 6, the timing for latching the dimmer regulation data is at the rising timing (t0, t3, t6) of the reset input (fig. 7(D)) of the RS flip-flop 808.

The comparison unit 802 includes an exclusive or element, a nand element, and a nor element, compares each bit inverted from the dimmer adjustment data (DM0-DM9) latched at the latch circuit 801 with a count value (1T to 9T) according to the reference clock signal output from the count unit 803, outputs "1" when they coincide with each other, and outputs "0" when they do not coincide with each other.

The count unit 803 includes a T flip-flop having a reset terminal, and generates count values (1T to 9T) by frequency division to a predetermined (nine (9) in fig. 6) reference clock signal generated at the oscillation circuit 202, and resets the count values (1T to 9T) at falling timings (T0, T3, T6) of an inverted output of the RS flip-flop 808, which is described later, the inverted data being a signal having an opposite polarity with respect to the FPDIS signal (fig. 7 (E)).

The signal generation unit 804 includes D flip-flops 805 and 806, a nor element 807, and an RS flip-flop 808.

The D flip-flop 805 sets the output from the comparison unit 802 at the rising timing (t2) of the reference clock signal, and inputs it to the set terminal of the RS flip-flop 808 (fig. 7 (C)). Time T2 of fig. 7 represents a time when the count value (1T to 9T) counted from time T0 at the counting unit 803 and each bit obtained by inverting the dimmer adjustment data (DM0 to DM9) latched by the latch unit 801 coincide with each other.

In accordance with the internal clock signal a (fig. 7(B)) having a period as its period for driving each of the grid electrodes G1 to G2, the D flip-flop 806 inputs a signal obtained by inverting the internal clock signal a (fig. 7(B)) to the reset terminal of the RS flip-flop 808 via the and element 807 (fig. 7 (D)).

Based on the set input (fig. 7(C)) and the reset input (fig. 7(D)), the RS flip-flop 808 outputs the FPDIS signal shown in fig. 7 (E). The pulse width TW of the FPDIS signal is equal to or includes the pulse widths TWG and TWs of the grid driving signal (fig. 7(F)) and the segment driving signal (fig. 7(G)) adjusted according to the same dimmer adjustment data at the dimmer adjusting unit 211.

In this way, the FPDIS signal generating unit 80 generates the FPDIS signal for invalidating the impulsive driving signals shown by the dotted-line regions S and T in fig. 7, based on the dimmer adjustment data received from the external controller 40. The FPDIS signal generation unit 80 is not limited to the unit having the above-described structure, but may have any structure capable of implementing the above-described logic.

Even in the case where the period of driving the grid electrodes 12 and the segment electrodes 13 is short, the VFD driving circuit 20, by having the FPDIS signal generating unit 80, can perform the required intensity adjustment by dimming by making the potential difference between the filament 11 and the grid electrodes 12 and the segment electrodes 13 constant within the period. Therefore, the convenience of the circuit can be improved.

In the above-described embodiment, the VFD driving circuit 20 may invalidate the pulse driving signal in the case where the period of time responsive to the pulse width of the dimmer value (a value that can be set to the duty ratio of the grid driving signal and the segment driving signal) corresponding to the dimmer adjustment data is shorter than the predetermined period of time (e.g., about 1/8 of one (1) cycle of the grid driving signal and the segment driving signal) according to the dimmer adjustment data received from the external controller 40. For example, it is preferable that in the case where the count values (1T to 9T) of the output of the counting unit 803 are equal to or larger (one (1) pulse period-predetermined period) when the comparing unit 802 outputs "1", a unit for resetting the output of the comparing unit 802 is newly provided in the FPDIS signal generating unit 80.

In this manner, each time the VFD driver circuit 20 receives dimmer adjustment data from the external controller 40, it may automatically determine the following: it should deactivate the pulsed drive signal in accordance with the received dimmer adjustment data. Therefore, the convenience of the circuit can be further improved.

Further, in the above-described embodiment, the VFD driving circuit 20 may be a semiconductor integrated unit, and may be provided therein with an interface (FPCON terminal) enabling the switching element 50 generating a voltage to pulse-drive the filament 11 to be connected to the outside.

Further, in the above-described embodiment, the switching element 50 may be provided in various application circuits (for example, vacuum fluorescent display modules) using the VFD driving circuit 20. Preferably, the VFD driving circuit 20 may be a semiconductor integrated circuit, and the switching element 50 may be connected to the outside, or may be a semiconductor integrated circuit in which the integrated switching element 50 is embedded.

< second embodiment >

As a second example according to the present invention, in the case of making the pulse drive signal effective, the filament pulse control unit 212 has a function of setting either one of the pulse width or the pulse period of the pulse drive signal in accordance with the pulse width data and the pulse period data received from the external controller 40.

To describe the above functions, first, embodiments of the pulse width data and the pulse period data will be described with reference to fig. 9 and 10.

Pulse width data

Fig. 9 is a reference table relating to the setting of pulse width data.

As shown, the pulse width data transmitted from the external controller 40 is serial data Wn (W0 to W3) such as 4 bits, where W0 is LSB (least significant bit). The external controller 40 transmits 4-bit serial data Wn (W0 to W3) to the VFD driving circuit 20, and includes the serial data Wn as pulse width data in the 16-bit control data transmitted in the G2 sequence.

On the other hand, the pulse width data (W0 to W3) is associated with the set value of the pulse width of the pulse drive signal, and is decoded into set data having the pulse width in the VFD drive circuit 20. The setting data having this pulse width may be a value such as 1/fosc (frequency of the reference clock signal) with reference to the period of the reference clock signal generated at the oscillation circuit 202. In this case, the pulse width of the pulse drive signal is a value calculated from "set value of pulse width/fosc".

According to this figure, as a method of design, in the case where the pulse width data (W0 to W3) is "0000", the setting of the pulse width is prohibited. However, the set value of the pulse width may be allocated from the pulse width data (W0 to W3) equal to "0000", for example. Further, the number of bits of the serial data as the pulse width data is not limited to the above-described four (4) bits, and should be set at an appropriate value so that the pulse width setting of the pulse drive signal has a desired resolution.

The VFD driving circuit 20 is enabled to finely set the pulse width of the pulse driving signal (i.e., the filament pulse voltage) at an appropriate timing based on these pulse width data.

Pulse period data

Fig. 10 shows a reference table relating to pulse period data.

As shown, the data transmitted from the external controller 40 as the pulse period data is, for example, 7-bit serial data (C0 to C6) having C0 as LSB. The external controller 40 transmits 7-bit serial data (C0 to C6) as pulse period data to the VFD driving circuit 20, and includes the serial data (C0 to C6) in the 16-bit control data transmitted in the G2 sequence.

On the other hand, the pulse period data (C0 to C6) is associated with the set value of the pulse period of the pulse drive signal and decoded into the set value of the pulse period in the VFD drive circuit 20. The set value of the pulse period may be a value that refers to the period (1/fosc (frequency of reference clock signal)) of the reference clock signal generated at the oscillation circuit 202. In this case, the pulse period of the pulse drive signal is a value calculated from "set value of pulse period/fosc".

According to this figure, as a design method, in the case where binary data (C0 to C6) are "0000" and "1111", the setting of the pulse period is prohibited. However, the set value of the pulse period may be specified from binary data (C0 to C6) as "0000", for example.

Further, the number of bits of the serial data Cn as the pulse period data is not limited to the above-described seven (7) bits, and should be set at an appropriate value so that the pulse period setting of the pulse drive signal can obtain a desired resolution.

The VFD driving circuit 20 is enabled to finely set the pulse period of the pulse driving signal (i.e., the filament pulse voltage) at an appropriate timing based on these pulse period data.

Filament pulse control unit

Fig. 11 shows the structure of a filament pulse control unit 212 according to a second embodiment of the present invention. The filament pulse control unit 212 shown in fig. 11 is an embodiment for achieving the pulse width setting shown in fig. 9 and the setting of the pulse period shown in fig. 10.

The filament pulse control unit 212 includes a first comparison unit 71, a second comparison unit 72, a counting unit 73, and a pulse drive signal generation unit 77.

The first comparison unit 71 compares the pulse width data (W0 to W3) received from the external controller 40 with the count value (1T to 4T) based on the reference clock signal as the output of the count unit 73, and includes, for example, four (4) elements of an exclusive nor and an and, that is, in a case where the comparison result of the respective bits between the pulse width data (W0 to W3) and the count value (1T to 4T) appears to coincide in each of the elements of the exclusive nor, the first comparison unit 71 outputs "1" from the element of the and thereof. Further, the result of the bit comparison shows that there is an inconsistency at any of the "exclusive or" elements, and the output of the "and" element is "0".

According to fig. 11, the first comparison unit 71 has a structure in which one (1) 3-input (negative logic) "and" element exists in addition to the above-described structure. The and element is used to invalidate the comparison operation related to the count values (5T to 7T) as a result of replacement of the count unit 73 by the comparison unit 72, so as to reduce the circuit scale. Further, the structure of the first comparison unit 71 is not limited to the above-described structure, and it may be a gate circuit that compares the pulse width data (W0 to W3) with the count values (1T to 4T), and outputs the comparison result (for example, "1" is output in the case of coincidence), and changes the number of constituent elements of the gate circuit according to the bit value of the pulse width data.

The second comparison unit 72 compares the pulse period data (C0 to C6) received from the external controller 40 with count values (1T to 7T) based on a reference clock signal, which are output of the counting unit 73, described later, and includes, for example, seven (7) "exclusive or" elements and "elements. That is, in the case where the comparison result of the respective bits between the pulse period data (C0 to C6) and the count value (1T to 7T) shows agreement in each of the "exclusive or" elements, the second comparing unit 72 outputs "1" from the "and" element thereof. Further, the output of the and element is "0" in the case where the result of the bit comparison shows inconsistency at any of its xor or nor elements.

Further, the second comparing unit 72 is not limited to the above-described structure, and it may be a gate circuit that compares the pulse period data (C0 to C6) with the count values (1T to 7T), and outputs the comparison result (for example, "1" is output in the case of coincidence). In this case, the number of constituent elements of the gate circuit is changed in accordance with the bit value of the pulse period data.

The counting unit 73 divides the reference clock signal generated by the oscillation circuit 202 into seven (7) and generates count values (1T to 7T), and resets the count values (1T to 7T) in the unit in the case where the bit comparison result of the first comparing unit 71 or the second comparing unit 72 shows coincidence (for example, the output of the and element of the first comparing unit 71 or the second comparing unit 72 is "1").

The above-described counting unit 73 may be realized by, for example, a frequency dividing circuit in which seven (7) T flip-flops each having a reset terminal are connected in series as shown in fig. 11. The counting unit 73 may be constituted by a gate circuit using various flip-flop elements other than the T flip-flop (e.g., a D flip-flop and a JK flip-flop), and the number of constituent elements of the gate circuit is changed when the number of divided reference clock signals is changed in response to a required resolution for setting at least any one of a pulse width and a pulse period.

The pulse drive signal generation unit 77 makes the pulse drive signal at one (1) level (for example, "0") in a case where the comparison result of each bit in the first comparison unit 71 shows coincidence, and the pulse drive signal generation unit 77 makes the pulse drive signal at the other level (for example, "1") in a case where the comparison result of each bit in the second comparison unit 72 shows coincidence, and the pulse drive signal generation circuit 77 includes D flip-flops 74 and 75, and an RS flip-flop 76, as shown in fig. 11.

Next, the operation of the filament pulse control unit 212 will be schematically described using fig. 8.

First, at time T0 shown in fig. 8, the count unit 73 has each bit count value (1T to 7T) as its output in a "0" state (hereinafter, referred to as a "reset state"). From this state, the counting unit 73 increments the count value (1T to 7T) one by one according to a decimal counter as 128 (power of 7 of 2).

Next, at time T1 shown in fig. 8, the count values (1T to 7T) as the output of the count unit 73 coincide with the pulse period data (C0 to C6) received from the external controller 40 in the second comparing unit 72. Then, according to the rise of the reference clock signal, "1" is set at the D flip-flop 74 and the RS flip-flop 76 one by one, and the pulse drive signal is switched from level "0" to level "1".

When "1" is set at the D flip-flop 74, the count state of the count value (1T to 7T) of the count unit 73 is moved to the reset state, and the count value (1T to 7T) is incremented.

Next, at time T2 shown in fig. 8, the count values (1T to 4T) as the output of the count unit 73 coincide with the pulse width data (W0 to W3) received from the external controller 40 in the first comparison unit 71, and the unit 71 outputs "1" to the D flip-flop 75. Then, according to the rise of the reference clock signal, "1" is set at the D flip-flop 75. Accordingly, the pulse drive signal is switched from level "1" to level "0".

In this way, the filament pulse control unit 212 may set at least either one of the pulse width or the pulse period of the pulse drive signal by making the pulse drive signal at one level for a period of the pulse width corresponding to the pulse width data and making the pulse drive signal at another level for a period other than the pulse width corresponding to the pulse period data.

Further, the filament pulse control unit 212 may be set so as to fix the content of the pulse width data or the pulse period data which is not set for the previously set data content, and receive the update data of the pulse width data or the pulse period data to be set from the external controller 40, and when either of the pulse width or the pulse period of the pulse driving signal is set, update only the setting of the pulse width data or the pulse period data to be set. In this case, the VFD driving circuit 20 may receive the pulse width data or the pulse period data not to be set together with the update data from the external controller 40, or may hold the data content for the previous setting and use the held data.

As described above, the VFD driving circuit according to the present invention can finely adjust the duty ratio of the pulse driving signal (i.e., the filament voltage) at an appropriate timing according to data (pulse width data and pulse period data) received from an external controller. Also, therefore, deterioration of the intensity level on the display of the VFD 10 and deterioration of the filament 11 can be suppressed. Therefore, the reliability of the VFD driving circuit can be improved.

Further, even when the frequency of the reference clock signal for setting the pulse drive signal is within a predetermined frequency band (at or above the audible frequency band and at or below a predetermined upper limit frequency), the VFD drive circuit according to the present invention easily sets at least either of the pulse width or the pulse period finely with an appropriate timing.

In the above-described embodiment, the VFD driving circuit 20 may be a semiconductor integrated circuit, and an interface (for example, the above-described FPCON terminal) for enabling the switching element 50 generating the filament pulse voltage to be connected to the outside may be provided in the circuit.

Further, in the above-described embodiment, the switching element 50 may be provided in various application circuits (e.g., vacuum fluorescent display modules) using the VFD driving circuit 20. In this case, the VFD driving circuit 20 may be a semiconductor integrated circuit, and the switching element 50 may be connected to the outside, or may be a semiconductor integrated circuit integrated with the switching element 50 in the circuit.

Claims (19)

1. A drive circuit for a vacuum fluorescent display having a filament, a grid electrode, and a segment electrode, the drive circuit comprising:

a filament driving unit for driving the filament;

a grid driving unit for pulse-driving the grid electrode;

the segmented driving unit is used for carrying out pulse driving on the segmented electrodes; and

a control unit for enabling or disabling an output of the filament driving unit at a predetermined timing,

wherein in the case of invalidating the output of the filament driving unit, the control unit invalidates the output of the filament driving circuit for a time period TW shorter than a predetermined time period to at least one of the voltages at which the grid electrodes and the segment electrodes are driven by the grid driving unit and the segment driving unit, respectively.

2. The driving circuit of the vacuum fluorescent display device according to claim 1, wherein: the control unit outputs a pulse driving signal for pulse-driving the filament.

3. The driving circuit of the vacuum fluorescent display device according to claim 1, wherein: the control unit fixes the output of the filament driving unit at a predetermined level for a time period TW shorter than a predetermined time period.

4. The driving circuit of the vacuum fluorescent display device according to claim 1, wherein:

the driving circuit of the vacuum fluorescent display can set the output of the filament driving unit to be inactive when the data X received from the outside is at a first logic value, the driving circuit of the vacuum fluorescent display can set the output of the filament driving unit to be active when the data X received from the outside is at a second logic value, and

the control unit

Setting an output of the filament driving unit to be inactive for a time period TW shorter than a predetermined time period when data X received from the outside is at a first logic value; and

when the data X received from the outside is at the second logic value, the output of the filament driving unit is set to be active.

5. The driving circuit of vacuum fluorescent display according to claim 4, characterized in that:

the driving circuit of the vacuum fluorescent display receives data Y associated with the duty ratio of the output of the grid driving unit or the output of the segment driving circuit from the outside, an

The time period TW is a time period based on the pulse width of the duty ratio corresponding to the received data Y.

6. The driving circuit of the vacuum fluorescent display device according to claim 1, wherein:

the driving circuit of the vacuum fluorescent display receives data Y associated with the duty ratio of the output of the grid driving unit or the output of the segment driving unit from the outside, an

When a time period TW based on a duty ratio corresponding to the received data Y is equal to or shorter than a predetermined time period, the control unit deactivates the output of the filament driving unit for the time period TW.

7. The driving circuit of the vacuum fluorescent display device according to claim 1, wherein: the driving circuit of the vacuum fluorescent display is a semiconductor integrated circuit, and the driving circuit enables a switching element for generating a voltage for pulse-driving the filament to be connected to the outside according to a pulse driving signal.

8. The driving circuit of the vacuum fluorescent display device according to claim 1, wherein: a switching element is included for generating a voltage for pulse-driving the filament according to an output of the filament driving unit.

9. The driving circuit of the vacuum fluorescent display device according to claim 8, wherein: the driving circuit of the vacuum fluorescent display, which enables the switching elements to be connected to the outside, is a semiconductor integrated circuit.

10. The driving circuit of the vacuum fluorescent display device according to claim 8, wherein: the driving circuit of the vacuum fluorescent display is a semiconductor integrated circuit integrated with the switching element.

11. The driving circuit of the vacuum fluorescent display device according to claim 1, wherein: when the output of the filament driving unit is enabled, the control unit can set the pulse width and/or pulse period of the pulse driving signal for pulse-driving the filament according to the data Z received from the outside.

12. The driving circuit of the vacuum fluorescent display device according to claim 11, wherein: the data Z received from the outside includes pulse width data for setting a pulse width of the pulse driving signal; and

the control unit generates a pulse driving signal having a pulse width corresponding to the received pulse width data.

13. The driving circuit of the vacuum fluorescent display device according to claim 11, wherein: the data Z received from the outside includes pulse period data for setting a pulse period of the pulse driving signal; and

the control unit generates a pulse driving signal having a pulse period corresponding to the received pulse period data.

14. The driving circuit of the vacuum fluorescent display device according to claim 11, wherein: data Z received from the outside includes pulse width data for setting a pulse width of the pulse driving signal and pulse period data for setting a period of the pulse driving signal; and

the control unit sets the pulse width and/or pulse period of the pulse drive signal by bringing the pulse drive signal to one level for a period of the pulse width corresponding to the received pulse width data and to another level for a period other than the pulse width in the pulse period corresponding to the received pulse period data.

15. The driving circuit of the vacuum fluorescent display device according to claim 14, wherein: the control unit includes:

a first comparing unit for comparing the pulse width data with a count value based on a reference clock signal;

a second comparing unit for comparing the pulse period data with a count value based on the reference clock signal;

a counting unit for generating a count value by frequency-dividing into a predetermined reference clock signal and resetting the count value when a comparison result at the first comparing unit or the second comparing unit shows coincidence; and

and an impulse driving signal control unit which makes the impulse driving signal at one level when the comparison result at the first comparison unit shows agreement, wherein the control unit makes the impulse driving signal at the other level when the comparison result at the second comparison unit shows agreement.

16. The driving circuit of the vacuum fluorescent display device according to claim 11, wherein: the driving circuit of the vacuum fluorescent display is a semiconductor integrated circuit, and the driving circuit enables a switching element that generates a voltage for pulse-driving a filament according to a pulse driving signal to be connected to the outside.

17. The driving circuit of the vacuum fluorescent display device according to claim 11, wherein: the driving circuit of the vacuum fluorescent display includes a switching element generating a voltage for pulse-driving the filament according to a pulse driving signal.

18. The driving circuit of a vacuum fluorescent display device according to claim 17, wherein: the driving circuit of the vacuum fluorescent display, which enables the switching elements to be connected to the outside, is a semiconductor integrated circuit.

19. The driving circuit of a vacuum fluorescent display device according to claim 17, wherein: the driving circuit of the vacuum fluorescent display is a semiconductor integrated circuit integrated with the switching element.