HK1077440B - Framing structure for digital broadcasting and interactive services - Google Patents

Description

Framing structure for digital broadcasting and interactive services

Technical Field

The present invention relates to communication systems, and more particularly to digital communication systems.

Background

Broadcast systems have accepted the requirement to use digital techniques to make the transmission high quality. The digital revolution has changed the way broadband services including audio and video programming and data transmission are transmitted. Satellite communication systems represent a viable solution to support such broadband services. Thus, it is highly desirable that the modulation and coding be both power and bandwidth efficient so that the satellite communication system can provide reliable communication in the presence of relatively noisy communication channels. In broadcast applications supported by such systems, it is desirable to employ fast frame synchronization in low signal-to-noise ratio (SNR) environments in order to avoid negative impact on user perception and to efficiently utilize system resources.

For normal broadcast and/or continuous transmission systems using convolutional codes, frame synchronization has not historically been an area of concern, primarily because decoding can be performed prior to frame synchronization. In this way, the decoded frame sync can enjoy the benefits of the coding gain provided by the error correction code. For example, the satellite digital video broadcasting (DVB-S) standard has become widely adopted worldwide to provide, for example, digital satellite television programming. Conventional DVB compliant systems employ a fixed modulation and coding scheme. Currently, such DVB compliant systems employ Quadrature Phase Shift Keying (QPSK) modulation and concatenated convolutional codes and Reed-Solomon channel coding. In case the modulation and coding scheme is fixed, a simple framing structure may be employed for these applications due to the continuous transmission nature of broadcast or unidirectional transmission. In practice, the only framing overhead is to append a Synchronization (SYNC) byte to an MPEG 2 (moving picture experts group 2) frame. The SYNC byte is processed by the convolutional code and Reed-Solomon encoder as well as other data. At the receiving end, the data contaminated by the communication medium is first recovered using convolutional codes. Convolutional codes can work without knowledge of the frame structure. The output of the convolutional code has high fidelity, and the error rate is usually lower than 1 × 10^-5. In the case of such high fidelity of the output, simply matching the data with the SYNC byte can determine the start of the MPEG frame. Therefore, the transmitted data can be correctly reassembled and then transmitted to the next layer.

However, for block coding systems, frame synchronization is typically performed prior to decoding. This is particularly required when the receiver has to determine which modulation and coding is used among a large number of possible combinations of modulation and coding schemes. Modem error correction coding, such as Low Density Parity Check (LDPC) codes, operate with very low signal-to-noise ratios. This means that such frame synchronization must be achieved with the same low signal-to-noise ratio (S/N or SNR). In addition, frame synchronization in such systems determines not only the start and end points of a frame, but also the modulation and coding scheme used within the frame.

In view of the above, the conventional approach to frame synchronization is not suitable in situations where, for example, high fidelity output requirements can no longer be guaranteed.

Therefore, some other approaches have been developed, but these approaches result in significant overhead (i.e., reduced throughput) and receiver complexity. For example, one approach suggests employing forward error correction coding, such as a Bose Chaudhuri Hocquenghem (BCH) code, to protect framing information within the frame structure. At the receiving end, the receiver first searches for a unique word with correlation. Upon detection of the unique word, the BCH encoded framing information is coherently decoded using maximum likelihood correlation decoding. The disadvantage of this technique is that the unique word must be very long (i.e., large in overhead). Another disadvantage is that the true maximum likelihood decoding of BCH codes is rather complex.

Therefore, there is a need for a frame synchronization mechanism that provides fast acquisition without incurring large overhead. There is also a need for a frame synchronization approach that is simple to implement. There is also a need for a flexible synchronization technique to provide coding and modulation independence.

Disclosure of Invention

The present invention addresses these and other needs by providing a way to support frame synchronization in digital broadcast systems that employ Low Density Parity Check (LDPC) codes. The framing module includes a constellation mapper for mapping codewords (e.g., produced by a Reed-Muller encoder) that define the framing information for the frame according to a signal constellation to output a data stream. This data stream is split into two data streams. One of the data streams is modified to transmit an additional bit (each bit of the data stream is multiplied by a bit depending on the information to be transmitted, which means that the data stream comprises a copy of the original data stream or a binary complement of the original data stream in the binary domain). The two data streams are then combined into a physical layer signaling code that is added to an LDPC coded frame. This approach embeds a framing structure that can facilitate synchronization. On the receiving side, a relatively simple frame detector may be used to determine the location of the unique word and the physical layer signaling code based on the framing structure of the embedded physical layer signaling code. This information is then provided to a peak search detection process, which searches for a peak within a search window and identifies this peak as a candidate. The length of the search window can be set in accordance with the modulation scheme knowing the modulation scheme used; otherwise, a default length is set. The peak search may be performed over multiple search windows to obtain other candidates. After each search, the candidate is validated by deriving the position of the next peak from the particular candidate. The above configuration advantageously provides fast and reliable frame acquisition without additional overhead.

According to an aspect of an embodiment of the present invention, a method of supporting frame synchronization in a digital communication system is disclosed. The method includes mapping a codeword that defines framing information for a frame according to a signal constellation and outputting a data stream. The method also includes replicating and splitting the data stream into a first data stream and a second data stream. The method further includes modifying the first data stream according to a predetermined operation; and multiplexing the modified first data stream with the second data stream. Further, the method includes outputting a physical layer header corresponding to the frame based on the multiplexed data stream.

According to another aspect of another embodiment of the present invention, an apparatus for supporting frame synchronization in a digital communication system is disclosed. The apparatus includes a constellation mapper configured to map a codeword that defines framing information for a frame according to a signal constellation and output a data stream, wherein the data stream is decomposed into a first data stream and a second data stream. The apparatus also includes a multiplier coupled to the constellation mapper and configured to modify the first data stream. The apparatus further comprises a multiplexer configured to combine the modified first data stream with the second data stream and to output a physical layer header corresponding to the frame based on the multiplexed data stream.

According to another aspect of an embodiment of the present invention, a method of supporting frame synchronization in a digital broadcasting system is disclosed. The method includes encoding framing information of a frame with a forward error correction code and outputting a number of encoded bits. The method also includes repeating each coded bit. The method further includes modifying the repeated bits according to a predetermined operation to transmit additional framing information.

According to another aspect of an embodiment of the present invention, a method of detecting the start of a frame is disclosed. The method includes receiving a data stream corresponding to a broadcast signal. The data stream includes a unique word and a physical layer header that defines modulation and coding information for the broadcast signal. The method further comprises; differencing the data stream; multiplying the differentiated data stream by a predetermined multiplier; summing the outputs of the multiplications; adding the summed outputs to obtain a plurality of added values; and subtracting the summed outputs to obtain a plurality of subtracted values. The method further includes determining a maximum value of the absolute values of the added value and the subtracted value.

According to another aspect of an embodiment of the present invention, an apparatus for detecting a start of a frame is disclosed. The apparatus comprises means for receiving a data stream corresponding to a broadcast signal. The data stream includes a unique word and a physical layer header that defines modulation and coding information for the broadcast signal. Such an apparatus further comprises: means for differencing the received data stream; means for multiplying the differentiated data stream by a predetermined multiplier; means for summing the outputs of the multiplications; means for summing the summed outputs to obtain a plurality of summed values; means for subtracting the summed outputs to obtain a plurality of subtracted values; and means for determining a maximum value of the absolute values of the added value and the subtracted value.

According to another aspect of an embodiment of the present invention, a method of recovering framing information of a frame transmitted within a digital communication system is disclosed. The method includes descrambling a physical layer signaling code of the frame. This physical layer signaling code is interleaved after being coded according to a first order Reed-Muller code. The method also includes decoding the physical layer signaling code to derive a coding rate, a modulation format, and a pilot structure for the frame.

According to yet another aspect of an embodiment of the present invention, a method of supporting frame synchronization in a digital communication system is disclosed. Such a method comprises: setting a search window length; and determining the location of a peak within a frame over the entire search window length. The frame includes a unique word, a code word and a code segment, wherein the code word determines framing information for the code segment. The method further comprises: marking the peak position as a candidate object; and verifying the candidate object. The method further includes declaring that the frame was captured if the candidate object is verified.

According to yet another aspect of an embodiment of the present invention, a transmitter is disclosed that includes an encoder configured to output a Low Density Parity Check (LDPC) codeword. The transmitter also includes a framing module configured to generate an LDPC coded frame based on the LDPC codeword and to add to the LDPC codeword a physical layer signaling segment that determines modulation and coding information associated with the LDPC coded frame. This physical layer signaling segment is encoded with a Forward Error Correction (FEC) code and has an embedded framing structure that facilitates frame synchronization.

Other aspects, features and advantages of the present invention will become apparent from the following detailed description, which illustrates some specific embodiments and implementations of the invention, including the best mode contemplated for carrying out the invention. The invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the spirit and scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

Drawings

The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

fig. 1 is a configuration diagram of a digital broadcasting system employing a Low Density Parity Check (LDPC) code according to an embodiment of the present invention;

FIG. 2 is a diagram of an exemplary transmitter used in the digital transmitting device of the system of FIG. 1;

FIG. 3 is a diagram of an exemplary digital modem in the system of FIG. 1;

FIG. 4 is a diagram of an exemplary frame structure in accordance with one embodiment of the present invention;

fig. 5 is a diagram of a configuration of a physical layer signaling information segment generator using Binary Phase Shift Keying (BPSK), according to an embodiment of the present invention;

fig. 6 is a flow diagram of the operation of a physical layer signaling information segment generator in accordance with one embodiment of the present invention;

FIG. 7 is a flow diagram of a frame detection process according to one embodiment of the invention;

fig. 8 is a diagram of a detector configuration utilizing physical layer signaling information, in accordance with one embodiment of the present invention;

FIG. 9 is a diagram of a differential detector configuration in accordance with one embodiment of the present invention;

fig. 10 is a schematic diagram of a peak search detection scheme in accordance with an embodiment of the present invention.

FIG. 11 is a flow diagram of a peak search process in accordance with one embodiment of the present invention;

FIG. 12 is a diagram of a configuration in which the detector of FIG. 8 is modified to add buffering and accumulation, according to one embodiment of the invention; and

fig. 13 is a configuration diagram of a computer system that may perform the various processes associated with frame synchronization according to an embodiment of the present invention.

Detailed Description

An apparatus, method, and software for efficiently providing frame synchronization in a digital broadcasting system will be described. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the present invention.

Fig. 1 is a configuration diagram of a digital broadcasting system using a Low Density Parity Check (LDPC) code according to an embodiment of the present invention. The digital communication system 100 includes a digital transmitting device 101 for generating a signal waveform for broadcast over a communication channel 103 to one or more digital modems 105. According to one embodiment of the present invention, communication system 100 is a satellite communication system supporting, for example, audio and video broadcast services and interactive services. Interactive services include, for example, Electronic Program Guides (EPGs), high speed internet access, interactive advertising, telephony, and email services. These interactive services may also include television services like pay-per-view, TV commerce, video-on-demand, near video-on-demand, and audio-on-demand services. In this environment, modem 105 is a satellite modem.

These modems 105 achieve carrier synchronization by checking the preamble and/or Unique Word (UW) embedded in the broadcast data frame structure (see fig. 4), thereby avoiding the overhead dedicated to training. The digital modem 105 will be described in detail below in conjunction with fig. 3.

In this discrete communication system 100, a transmitting device 101 generates a discrete set of possible messages representing media content (e.g., audio, video, text information, data, etc.), each possible message having a corresponding signal waveform. This signal waveform is subject to attenuation or intrusion by the communication channel 103. To combat the noisy interference channel 103, the transmitting device 101 employs an LDPC code.

The LDPC code generated by the transmitting apparatus 101 can be implemented at high speed without causing any performance loss. These LDPC codes output from the transmitting apparatus 101 avoid assigning a small number of check nodes to bit nodes susceptible to channel errors due to a modulation scheme (e.g., 8 PSK). Such LDPC codes have a parallelizable decoding process (unlike turbo codes) that advantageously involves only some simple operations such as addition, comparison and table lookup. Furthermore, carefully designed LDPC codes do not exhibit any signs of error propagation.

In accordance with one embodiment of the present invention, the transmitting device 101 generates LDPC codes that communicate with the satellite modem 105 based on a parity check matrix (which facilitates efficient memory access during decoding) using a relatively simple encoding technique as described below in conjunction with fig. 2.

Fig. 2 is a diagram of a typical transmitter used in the digital transmitting device of the system of fig. 1. Transmitter 200 is used within device 101 to support, for example, digital broadcast and interactive services. Information source 201 provides information bits to LDPC encoder 203, and encoder 203 outputs an encoded data stream having high redundancy suitable for error correction processing at receiver 105. The encoded data stream is provided to framing module 204 to generate a transport frame, which may include a Unique Word (UW) and a physical layer signaling header that determines the framing information of the LDPC encoded frame.

LDPC codes typically require a determination of a generator matrix. The LDPC encoder 203 employs a simple encoding technique using only a parity check matrix by applying a structure to the parity check matrix. Specifically, a constraint is imposed on the parity check matrix such that a certain portion of the matrix is triangular. This limitation results in negligible performance loss and therefore constitutes an attractive compromise.

The transmission frames from the framing module 204 are mapped into signal waveforms by the modulator 205, transmitted to the transmit antennas 207, and transmitted by the transmit antennas 207 onto the communication channel 103. These coded messages are therefore modulated and distributed to the transmit antennas 207. The waveform transmitted by the transmit antenna 207 is passed to a digital modem as explained below. In the case of a satellite communication system, the signal transmitted by the antenna 207 is relayed through a satellite.

Fig. 3 is a diagram of an exemplary digital modem configuration in the system of fig. 1. Digital modem 300, acting as a modulator/demodulator, supports the transmission and reception of signals from transmitter 200. According to one embodiment of the present invention, modem 300 has a frame synchronization module 301 for performing frame acquisition on the LDPC coded signal received from antenna 303. The demodulator 305 demodulates the received signal output from the carrier synchronization module 301. After demodulation, the signal is provided to LDPC decoder 307, which LDPC decoder 307 attempts to reconstruct the original source message (i.e., information bits).

On the transmitting side, the modem 305 encodes an input signal with the LDPC encoder 309. The encoded signal is then modulated by a modulator 311 with, for example, BPSK (binary phase shift keying), QPSK, 8PSK, 16APSK (amplitude phase shift keying) or other higher order modulation schemes.

Alternatively, in a strictly broadcast application, modulator 311 may not be needed because the end user does not need to send information back to the broadcast network. As part of transmitter 200, modulator 205 may reside in a broadcast center, while demodulator 305 may be deployed in the home of the end user. In the case of this configuration, the end-user's terminal will be a receive-only terminal.

Figure 4 illustrates a schematic diagram of an exemplary frame structure according to one embodiment of the present invention. For example, the frame structure 400 is designed to support the digital broadcasting system shown in fig. 1. The system 100, as mentioned, may be deployed as a satellite communication system. Thus, the frame structure 400 conforms to the Digital Video Broadcasting (DVB) -S2 standard that supports, for example, satellite broadcasting and interactive services.

With improved performance, some satellite systems may support high-efficiency dynamic coding and modulation schemes, such as LDPC coding schemes and higher order modulation. By dynamically determining the coding and modulation schemes, the transmission can be adapted to the environment (e.g., rainy, sunny, etc.) for optimal throughput. However, dynamic coding and modulation schemes place significant limitations and requirements on the frame structure. Because the modulation scheme is dynamic, the receiver does not know the specific modulation scheme used in the transmission. In addition, the LDPC code, which is a block code, can be decoded only if the encoded frame is clearly identified, i.e., it is necessary to determine the start point and the end point of the frame before decoding. Therefore, any framing information inserted into the transport stream will not be protected by a powerful LDPC coding scheme. Furthermore, due to the power efficiency of LDPC, system 100 can operate at very low SNR; for example, for BPSK at a rate of 1/2, LDPC only-2 dB of Es/No is required. In the case of many possible LDPC codes and modulation schemes, the framing information requires the particular coding and modulation scheme to be used for LDPC coded frames following the framing information.

It can therefore be appreciated that the framing information must be correctly embedded so that the signal-to-noise ratio is so low that it is recoverable without protection by the LDPC decoder 307. Framing information, as can be seen from the above discussion, information such as modulation, coding, and steering structures must be efficiently conveyed rather than just the beginning and end of a frame.

As shown in fig. 4, the framing structure 400 includes a Unique Word (UW)401 and a physical layer signaling information segment 403 labeled as a MODCODE segment. The UW 401 contains a bit pattern that assists in frame synchronization. The UW 401 is fixed and known to the receiver. The MODCODE segment 403, which in an exemplary embodiment is a Forward Error Correction (FEC) encoded block (e.g., Reed-Muller encoding), conveys information necessary to enable the demodulator 305 and LDPC decoder 307 to function correctly, decoding the received signal. For example, the MODCODF section 403 determines framing information including the rate of the LDPC code, the modulation scheme, and other information such as the length and the pilot shape of the LDPC code. The modulation schemes supported by frame 400 may include BPSK, QPSK, 8PSK, 16-ary, 32-ary modulation. Based on the information it provides, the MODECODE field is also referred to as the "physical layer signaling" field.

It is clear that any information that needs to be transmitted over a noisy channel (rather than a pure protocol) needs to be properly protected. Therefore, following the MODCODE field 403 is an LDPC coded frame 405. To support broadcasting and interactive services, the length of the LDPC coded frame 405 may be 64800 bits, and the combined length of the UW 401 and the MODCODE segment 403 is 90 bits.

It has been considered that such a physical layer signaling information segment 403 cannot be used for frame detection since the MODCODE segment 401b varies with the information carried. According to an embodiment of the present invention, a mechanism is provided to embed a structure into the MODCODE segment 403 that can easily leverage detection without sacrificing the error correction capability of the MODCODE segment 403.

The frame structure 400 advantageously requires only low overhead and provides reliable acquisition. The capture mode for the fast capture will be described in detail below in conjunction with fig. 7 and 11. It is noted that fast capture is a key to digital video broadcasting applications, affecting the viewing experience when the viewer switches channels.

Therefore, in order to protect the framing information so that the embedded structure within the framing code can also be used for detection and acquisition in such a way to generate MODCODE403, the following is the case.

Fig. 5 is a configuration diagram of a physical layer signaling information segment generator using a Binary Phase Shift Keying (BPSK) constellation according to an embodiment of the present invention. In terms of frame synchronization, the UW 401 at the beginning of frame 400 is known and can be any well correlated sequence. The present invention therefore focuses on the generation of the physical layer signalling information segment 403. In this example, the MODCODE generator 500 may be configured within the framing module 204 of the transmitter 204. Generator 500 includes a Reed-muller (rm) encoder 501 that outputs a bit stream to BPSK constellation mapper 503. The operation of the generator 500 is described below in conjunction with fig. 6.

Figure 6 illustrates a flow diagram of the operation of a physical layer signaling information segment generator in accordance with one embodiment of the present invention. As mentioned earlier, the MODCODE403 conveys information about, for example, modulation, FEC code rate, frame length, and pilot configuration (e.g., whether pilot is present). Conceptually, the generator 500 outputs a MODCODE403, which is an interleaving of a block code with its scrambled version.

Specifically, in step 601, a block code is generated, for example using a Reed-Muller encoder 501, to produce a code [32, 6, 16] carrying 6 bits of information. An exemplary generator matrix is given below:

01010101010101010101010101010101

00110011001100110011001100110011

00001111000011110000111100001111

00000000111111110000000011111111

00000000000000001111111111111111

the encoded data is then mapped to BPSK modulation by BPSK constellation mapper 503, as shown in step 603. It is envisaged that other signal constellations corresponding to different modulation schemes (e.g. QPSK) may be employed. This mapping to a BPSK signal constellation is independent of the modulation scheme of the user data. The resulting 32 BPSK symbols are copied and divided into two coded data blocks in step 605. It is noted that one additional bit of information may be carried by multiplying the unscrambled coded data block by { a, -a } (a may be any constant whose sign (i.e., positive, negative) represents a logical 0 and a logical 1, respectively) with multiplier 505 in step 607. Note that the symbols do not change over the entire replicated 32-bit block.

In step 609, the two data streams are multiplexed into one data stream by the multiplexer 507, resulting in the MODCODE403 having 64 symbols (step 611). This is actually interleaving the two data streams. It is noted that this is fundamentally different from simply repeating the encoded symbols, which would result in a lower order error correction code, i.e. a linear code of parameters [64, 6, 32], which is easily verified as not being optimal. In contrast, the MODCODE403 output by the generator 500 corresponds to a reordered [64, 7, 32] first order Reed-Muller code, which is an optimal code for a given size and information rate. Therefore, neither error correction capability nor data rate is sacrificed. One advantage of using a permutated first order Reed-Muller code is that such a code can be decoded in a maximum likelihood manner using the well-known fast Hadamard transform. Also, MODCODE403 may be used to speed up frame acquisition.

In step 613, the MODCODE403 is scrambled by the scrambler 509 with, for example, the following binary sequence:

0111000110011101100000111100100101010011010000100010110111111010

this scrambling sequence improves the spectral/correlation properties of the interleaved first order Reed-Muller code. This improvement in the relevant properties is critical for detection and capture.

As can be seen from the above discussion, if the MODCODE403 is decomposed into 32 pairs of adjacent symbols,each pair may differ by as much as the proportionality constant 1 or-1. This property allows the MODCODE403 to be used to obtain without knowing the framing information conveyed by the MODCODE 403. That is, the MODCODE403 may be completely described in the binary domain rather than the modulation domain. In this case, RM [32, 6, 16]The output of encoder 501 may be labeled (y)₁y₂...y₃₂). If the additional bits to be transmitted are equal to logic 0, then the output before the scrambler is (y)₁y₁y₂y₂...y₃₂y₃₂). I.e. each bit is repeated. However, if the additional bits to be transmitted are equal to a logical 1, then the output before the scrambler 509 is equal toI.e., the repeated symbols are binary complemented. The binary scrambled sequence may be mapped to any predetermined modulation scheme, such as BPSK, QPSK, or the like.

For other system considerations, the original symbols and the repeated symbols (or repeated and then binary complemented symbols) may be modulated in different formats. For example, according to another embodiment of the present invention, both the original symbol and the repeated symbol are modulated to BPSK, however, the repeated symbol (or repeated re-binary complemented symbol) may be rotated by 90 degrees. In this way, the peak-to-average ratio may be reduced, thereby improving the efficiency of a power amplifier (not shown) of transmitter 200.

Fig. 7 is a flow diagram of a frame detection process according to one embodiment of the invention. This detection process will be described in conjunction with the detector 800 shown in fig. 8. Detection involves determining a unique word 401 and a MODCODE field 403. This process employs differential detection, which can accommodate relatively large frequency offsets (e.g., 10-20 percent of the symbol rate). Assume that in the system shown in fig. 8, there is one sample per symbol. As will be appreciated by those skilled in the art, this process can be readily applied to situations where there are multiple samples per symbol. Consider in the detection process that the framing information conveyed by the MODCODE is unknown and that the framing information is known.

The operation of detector 800 and detector 900 (fig. 9) consider the two cases, where framing information is unknown and known, respectively. As shown in fig. 8, first a difference in signal is derived in step 701 by feeding the incoming signal into the shift register 801. That is, the incoming symbol is multiplied by the conjugate of the signal delayed by one symbol period by the multiplier 803. The output is then buffered by shift register 801. Assuming that the generator 500 of fig. 5 is used, the content of e.g. the rightmost 25 stages (or 25 cells) of the shift register 801 is multiplied by the conjugate of the differentiated unique word by a multiplier 807 at step 703.

The values of the multipliers 805,807 can be easily derived and checked as follows. The shift registers 801 are initialized to all zeros. The unique word 401 and the MODCODE word 403 (including the effect of the scrambling sequence and/or the effect of different modulation schemes on the possible relative rotation of the repeated (re-complemented) symbols) are fed into the detection circuit 800 such that when the content of the rightmost element of the shift register 801 becomes non-zero for the first time, the conjugate of the content of these elements is the corresponding value of the multipliers 805,807 connected to the particular element. Obviously, the multipliers 805, 807 are completely determined by the modulation scheme of the unique word, MODCODE, scrambling sequence and physical layer signaling segment, and can be derived off-line. In step 705, the outputs of multipliers 805, 807 are added together by adders 809, 811. In this example, only 32 of the leftmost 64 cells of the shift register 801 are used at any given time. The 32 units are evenly spaced, i.e., the 32 units numbered 1, 3.. 63 from left to right.

The outputs of adders 809, 811 are added by adder 813 and subtracted by subtractor 815, respectively, as shown in step 707, resulting in two inputs to circuit 817, the maximum of the absolute values of which is determined by circuit 817 (step 709). This maximum value is then output to the peak search detector 819 (step 711). The operation of the peak search detector 819 is described in detail below in conjunction with fig. 10 and 11.

The process of fig. 7 and the associated detector 800 above are directed to the case where MODCODE information is unknown. If the MODCODE information is known, the detector 800 may be pipelined, as shown in fig. 9.

Fig. 9 is a configuration diagram of a differential detector according to an embodiment of the present invention. The detection modes supported by the detector 900 are known for the MODCODE-carried information prior to acquisition. This information may be made known, for example, by establishing a dedicated channel that conveys configuration information to receivers, which is particularly suitable for broadcast system 100. After a cold start, the receiver (i.e., digital modem 105) may tune to the predetermined channel and receive configuration information. In this case, the information carried by MODCODE can be inferred from the configuration information, and thus the acquisition policy of the detector 900 can be easily deployed.

Just as in the detector 800 of fig. 8, the input signal is multiplied by its conjugate by a multiplier 901. The difference between detector 800 and detector 900 is the summation of shift registers 901 after multiplication by the respective differentiated UW 401 and MODCODE 403. Just as with detector 800, the values of multiplier 905 are determined by: the shift register 903 is all initialized to zero and the unique word 401 and MODCODF 403 are fed into the circuit 900, the conjugate of the contents of the rightmost element of the shift register giving the corresponding value of the multiplier 905 connected to the particular element, when the contents of these elements first become non-zero. The outputs of all of these multipliers 905 are fed to a common adder 907.

Fig. 10 is a schematic diagram of a peak search detection scheme according to an embodiment of the present invention. The peak search detector 819 of fig. 8 is essentially configured to search for a peak within a search window 1001, which is identified as a candidate, e.g., candidate 1, stored in the buffer 1003. This search may be performed for a plurality of search windows 1001, resulting in other candidates (e.g., candidate 2 and candidate 3). After each search, the candidate is validated by deriving the position of the next peak from the particular candidate. If this prediction is correct, acquisition is declared.

This above procedure advantageously provides fast acquisition compared to conventional peak search procedures. The conventional peak search process establishes a threshold above which a candidate is obtained once there is a correlation. Thereafter, the process verifies that it is a valid unique word. This conventional approach is slow because such thresholding may produce many candidates, and thus a verification process is performed for each candidate.

Fig. 11 shows details of a peak search process according to an embodiment of the invention. The design of this peak search process is based on the recognition that system 100 may employ different code rates and different modulation schemes (e.g., BPSK, QPSK, 8PSK, 16APSK, etc.). The maximum distance between unique words 401 is known even though the modulation scheme may not be known a priori. The peak search process takes advantage of this knowledge, as follows.

In step 1101, the process determines whether the modulation scheme is known. Such information may be used to specify the search window length (L). For example, if the code length of LDPC is fixed to 64800 bits, for BPSK, the distance between two unique words is 64800 bits. For QPSK, the length is 32400 bits, while for 8PSK the length is 21600 bits. Thus, for the modulation scheme under consideration, the maximum length will depend on the length of the LDPC frame. Therefore, without knowing the modulation scheme in advance, the search window length L may be set to the length of the LDPC frame plus the lengths of UW 401 and MODCODE403 (e.g., 64800+90) in step 1103. If, however, the modulation scheme is known, the search window length is set to match the length of the frame for the particular modulation scheme, as shown in step 1105. In step 1107, the peak search detector finds a peak using the specified search window. The peaks within this window are searched for with a search window even though there may be multiple unique words 401 and MODCODEs 403. The search window is set in such a way that at least one unique word 401 (as shown in fig. 10) is present within the search window.

Next, in step 1109, the peak position within the search window is designated as a candidate. If modulation and coding information is not yet available, the MQDCODE403 is decoded for each candidate (step 1111). The position of the next unique word is derived based on the modulation and coding scheme, as shown in step 1113. Thereafter, in step 1115, the process verifies whether the predicted locations are indeed UW 401 and MODCODE 403. If there are then consecutive predicted positions (e.g., two) that verify as UW 401 and MODCODE403, the process declares that frame synchronization is obtained.

The above process may be performed on these candidates serially or in parallel until one of them is successfully verified.

Fig. 12 is a diagram of a configuration in which the detector of fig. 8 has been modified to add buffers and accumulators, according to one embodiment of the invention. The detector 800 may be modified to include a memory 1201 and an accumulator 1203. After the first differential multiplier 803, the data of length L is buffered in the memory 1201, and the accumulator 1203 adds the next data block of length L together with the buffered data. This modification increases the capture speed of the detector 800. In LDPC systems, LDPC decoder 307 typically has memory available for the decoding process, and thus, such memory may be used for buffering detector 800. That is, the memory 1201 can be shared with the decoder 307, thereby avoiding additional costs.

FIG. 13 illustrates a computer system upon which an embodiment of the invention may be implemented. Computer system 1300 includes a bus 1301 or other communication mechanism for communicating information, and a processor 1303 coupled to bus 1301 for processing information. Computer system 1300 also includes a main memory 1305, such as a Random Access Memory (RAM) or other dynamic storage device, coupled to bus 1301 for storing information and instructions to be executed by processor 1303. Main memory 1305 may also be used for storing temporary variables or other intermediate information during execution of instructions to be executed by processor 1303. Computer system 1300 also includes a Read Only Memory (ROM)1307 or other static storage device coupled to bus 1301 for storing static information and instructions for processor 1303. A storage device 1309, such as a magnetic disk or optical disk, is also coupled to bus 1301 for storing information and instructions.

Computer system 1300 may be coupled via bus 1301 to a display 1311, such as a Cathode Ray Tube (CRT), liquid crystal display, active matrix display, or plasma display, that displays information to a computer user. An input device 1313, such as a keyboard including alphanumeric and other keys, is coupled to bus 1301 for communicating information and command selections to processor 1303. Another type of user input device is cursor control 1315, such as a mouse, a trackball, or cursor direction keys for communicating direction information and command selections to processor 1303 and for controlling cursor movement on display 1311.

According to one embodiment of the invention, computer system 1300 may provide various frame synchronization processes through the execution of instructions contained in main memory 1305 by processor 1303. Such instructions may be read into main memory 1305 from another computer-readable medium, such as storage device 1309. Execution of the series of instructions contained in main memory 1305 causes processor 1303 to perform the process steps described herein. One or more processors in a multi-processing arrangement may also be employed to execute the instructions contained in main memory 1305. In another embodiment, hardwired modules may be used in place of or in combination with software instructions to implement embodiments of the present invention. Thus, embodiments of the invention are not limited to any specific combination of hardware modules and software.

Computer system 1300 also includes a communication interface 1317 coupled to bus 1301. Communication interface 1317 provides a two-way data communication coupling to a network link 1319 that is connected to a local network 1321. For example, communication interface 1317 may be a Digital Subscriber Line (DSL) card or modem, an Integrated Services Digital Network (ISDN) card, a cable modem, or a telephone modem to provide a data communication connection to a corresponding type of telephone line. As another example, a communications interface1317 may be a Local Area Network (LAN) card providing a data communication connection to a compatible LAN (e.g., for Ethernet)^TMOr Asynchronous Transfer Mode (ATM) network). Wireless links may also be implemented. In any such implementation, communication interface 1317 sends and receives electrical, electromagnetic or optical signals that carry digital data streams representing various types of information. In addition, the communication interface 1317 may include a number of peripheral interface devices such as a Universal Serial Bus (USB) interface, a PCMCIA (personal computer memory card international association) interface, or the like.

Network link 1319 typically provides data communication through one or more networks to other data devices. For example, network link 1319 may provide a connection through local network 1321 to a host computer that may be connected to a network 1325 (e.g., a Wide Area Network (WAN) or a global packet data communication network, now commonly referred to as the "internet") or data device operated by a service provider. Local network 1321 and network 1325 both use electrical, electromagnetic or optical signals to communicate information and instructions. The signals through the various networks and the signals applied to network link 1319 through communication interface 1317, which typically are carrier waves carrying the information and instructions, are used to exchange digital data with computer system 1300.

Computer system 1300 can send messages and receive data, including program code, through the network(s), network link 1319 and communication interface 1317. In the Internet example, a server (not shown) might transmit requested code for an application program implementing an embodiment of the invention through the network 1325, the local network 1321 and the communication interface 1317. The processor 1303 may execute the transmitted code while receiving it and/or after storing the code in the storage device 139 or other non-volatile storage. In this manner, computer system 1300 may obtain application code embodied as a carrier wave.

By "computer-readable medium" is meant any medium that participates in providing instructions to processor 1303 for execution. Such a medium may take many forms, including but not limited to, non-volatile media, and transmission media. Non-volatile media includes, for example, optical or magnetic disks, such as storage device 1309. Volatile media includes dynamic memory, such as main memory 1305. Transmission media includes coaxial cables, copper wire and fiber optics, including the wires that comprise bus 1301. Transmission media can also take the form of acoustic, light, or electromagnetic waves, such as those generated during Radio Frequency (RF) and Infrared (IR) data communications. Common forms of computer-readable media include, for example: floppy disks, hard disks, magnetic tape, and any other magnetic medium, CD-ROMs, CDRW, DVDs, and any other optical medium, punch cards, paper tape, optical mark sheets, and any other physical medium with patterns of holes or other optically recognizable indicia, RAMs, PROMs, and EPROMs, FLASH-EPROMs, and any other memory chip or cartridge, carrier wave, or any other medium from which a computer can read.

Various forms of computer readable media may be involved in carrying out the instructions to the processor. For example, the instructions for carrying out at least part of the invention may initially be borne on a magnetic disk of a remote computer. In such a case, the remote computer loads the instructions into main memory and sends the instructions over a telephone line using a modem. A modem of a local computer system receives the data on the telephone line and uses an infrared transmitter to convert the data to an infrared signal for transmission to portable computing devices, such as Personal Digital Assistants (PDAs) and laptop computers. The infrared detector on the portable computing device receives the information and instructions carried by the infrared signal and sends this data to the bus. The bus transfers data to main memory, from which the processor fetches instructions for execution. The instructions received by main memory may be stored on storage device either before or after execution by processor, as desired.

Accordingly, various embodiments of the present invention provide a way to achieve frame synchronization within a digital broadcast system that employs Low Density Parity Check (LDPC) codes. The framing module includes a constellation mapper for mapping codewords (e.g., produced by a Reed-Muller encoder) that define the framing information for the frame according to a signal constellation to output a data stream. This data stream is split into two data streams. Where a data stream is modified to interleave with additional bits (either a duplicate bit or a binary complement bit per bit). The two data streams are then combined into a physical layer header that is added to an LDPC encoded frame. This approach embeds a framing structure that can facilitate synchronization. On the receiving side, a relatively simple frame detector can be used to determine the positions of the unique word and the physical layer header based on the frame structure of the embedded physical layer header. This information is then provided to a peak search detection process, which searches for a peak within a search window and identifies this peak as a candidate. The length of the search window may be set according to the modulation scheme knowing the modulation scheme used, or set to a default length otherwise. The peak search may be performed over multiple search windows to obtain other candidates. After each search, the candidate is validated by deriving the position of the next peak from the particular candidate. The above configuration advantageously provides fast and reliable frame acquisition without additional overhead.

Although the invention has been described in connection with a number of embodiments and implementations, the invention is not limited to these embodiments and implementations, but covers all obvious modifications and equivalent arrangements, which fall within the purview of the appended claims.

Claims (20)

1. A method of supporting frame synchronization in a digital communication system, said method comprising the steps of:

mapping a codeword determining framing information of a frame according to a signal constellation to output a data stream of symbols;

copying each symbol in the data stream and decomposing the data stream into a first data stream of copied symbols and a second data stream of original symbols;

modifying the replica symbols in the first data stream according to a predetermined operation;

multiplexing the modified first data stream with a second data stream to interleave the original symbols with modified replica symbols; and

outputting a physical layer signaling header corresponding to the frame based on the multiplexed data stream.

2. A method according to claim 1, wherein the signal constellation is independent of the modulation scheme of the frame.

3. A method according to claim 1, wherein said frame is a low density parity check, LDPC, encoded frame.

4. A method according to claim 1, wherein said predetermined operation comprises multiplying the first data stream by { -a } or { a }, a being a predetermined constant, by a multiplier (505).

5. A method according to claim 4, wherein the symbol of said multiplier (505) represents a part of the framing information.

6. A method according to claim 4, wherein said multiplying produces bits of the first data stream interleaved with respective additional bits which are phase rotated relative to said bits of the first data stream during modulation.

7. A method according to claim 1, the method further comprising the steps of:

the code words are generated according to a first order Reed-Muller code.

8. A method according to claim 1, wherein the framing information determines a modulation scheme and a coding scheme.

9. A method according to claim 1, the method further comprising the steps of:

the multiplexed data stream is scrambled.

10. A method according to claim 1, wherein said signal constellation corresponds to a binary phase shift keying, BPSK, scheme.

11. An apparatus for supporting frame synchronization in a digital communication system, said apparatus comprising:

a constellation mapper (503) configured to map a codeword defining framing information of a frame according to a signal constellation to output a data stream of symbols, wherein symbols in the data stream are copied and decomposed into a first data stream of copied symbols and a second data stream of original symbols;

a multiplier (505) coupled to the constellation mapper (503) and configured to modify each replica symbol in the first data stream; and

a multiplexer (507) configured to interleave the modified replica symbols of the first data stream with the original symbols of the second data stream, wherein a physical layer signaling header corresponding to the frame is output based on the multiplexed data stream.

12. An apparatus according to claim 11, wherein the signal constellation is independent of a modulation scheme of the frame.

13. An apparatus according to claim 11, wherein said frame is a low density parity check, LDPC, encoded frame.

14. An apparatus according to claim 11, wherein said multiplier (505) multiplies the first data stream by { -a } or { a }, a being a predetermined constant.

15. An apparatus according to claim 14, wherein the symbol of the multiplier (505) represents a part of the framing information.

16. An apparatus according to claim 14, wherein said multiplying produces bits of the first data stream interleaved with respective additional bits which are phase rotated relative to said bits of the first data stream during modulation.

17. An apparatus according to claim 11, the apparatus further comprising:

a code generator (500) coupled to the constellation mapper (503) and configured to generate the code words according to a first order Reed-Muller code.

18. An apparatus according to claim 11, wherein the framing information determines a modulation scheme and a coding scheme.

19. An apparatus according to claim 11, the apparatus further comprising:

a scrambler (509) configured to scramble the multiplexed data stream.

20. An apparatus according to claim 11, wherein said signal constellation corresponds to a binary phase shift keying, BPSK, scheme.