HK1095672B - Delay circuit and method therefor - Google Patents

Description

Delay circuit and method thereof

Technical Field

The present invention relates generally to electronic circuits, and more particularly to methods of forming semiconductor devices and structures.

Background

In the past, the semiconductor industry utilized various structures and methods to produce circuits for providing increased propagation delay in circuit function. The circuit is used in various applications including deskewing signals in clock distribution networks, in-phase-locked loop functions, and in various other applications. Fig. 1 schematically illustrates an example of a prior art amplifier circuit 100 that is used to reduce the effects of internal capacitance and to reduce the delay of the circuit 100. Circuit 100 includes differentially coupled transistors 101 and 102 that are used as a differential amplifier. Transistors 107 and 108 are coupled to the emitters of respective transistors 103 and 104 to pass small bias currents through respective transistors 103 and 104, which limits voltage drift at the collectors of transistors 101 and 102 and reduces delay. One problem with the prior art circuit is the power consumption of the circuit 100. The extra current introduced by transistors 107 and 108 increases the power consumption of the circuit. In addition, outputs 105 and 106 typically provide a large output current in order to drive the next stage connected to outputs 105 and 106.

Therefore, it is desirable to have a delay circuit that has lower power consumption and utilizes less current.

Drawings

FIG. 1 schematically illustrates an example of a prior art circuit;

FIG. 2 schematically illustrates a portion of one embodiment of a delay circuit in accordance with the present invention;

FIG. 3 schematically illustrates a portion of another embodiment of the delay circuit of FIG. 2 in accordance with the present invention;

fig. 4 schematically illustrates an enlarged plan view of a semiconductor device including the delay circuit of fig. 1 or 2 according to the present invention.

For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, and the same reference numbers in different figures denote the same elements. In addition, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein, current carrying electrode refers to a unit of a device that carries current through the device, such as a source and drain of an MOS transistor, or an emitter or collector of a bipolar transistor, or a cathode or anode of a diode, and a control electrode refers to a unit of a device that controls current through the device, such as a gate of an MOS transistor, or a base of a bipolar transistor. Although the device is explained herein as a certain NPN or PNP device, it will be understood by those skilled in the art that additional devices are possible according to the present invention.

Detailed Description

Fig. 2 schematically illustrates a portion of one embodiment of a delay circuit 10 that provides increased delay between input and output signals of circuit 10 and that has low power consumption. Circuit 10 receives a differential input signal between inputs 37 and 38 and provides a differential output signal between outputs 19 and 20. Power is received between a voltage input 43 and a voltage loop (return)44 of the circuit 10. The circuit 10 includes a differential amplifier having a first differential transistor 11 and a second differential transistor 12 coupled as a differential pair 21 of the differential amplifier. The bias circuit 25 of the circuit 10 provides a bias current to the differential amplifier. The circuit 25 includes a bias transistor 23 and a bias resistor 24. Circuit 10 also includes first and second cascode transistors 13 and 14 coupled to receive signals from respective transistors 11 and 12, load resistors 17 and 18, emitter-follower coupled transistors 27 and 28, bias transistors 31 and 33, and bias resistors 32 and 34. Transistor 31 and resistor 32 act as a bias circuit that sets the bias current through transistor 27. Transistor 33 and resistor 34 likewise act as a bias circuit to set the bias current through transistor 28.

In operation, if the signal received by transistors 11 and 12 is greater in voltage applied to the base of transistor 11 than applied to the base of transistor 12, transistor 11 is turned on. Because the bases of transistors 13 and 14 are fixed, the voltage at the collector of transistor 11 must be reduced to a value sufficient to turn on transistor 13. The conducting transistor 13 generates a current through the resistor 17 and a corresponding voltage drop across the resistor 17. The emitter follower configuration of transistor 27 couples the voltage on the collector of transistor 13 minus the base-emitter voltage (Vbe) of transistor 27 to output 19. The additional amount of time required to activate transistor 13 increases the delay through circuit 10 without requiring additional current and associated power consumption. This can be considered as adding another gate delay without using extra current. The emitter follower configuration of transistors 27 and 28 isolates outputs 19 and 20 from the load of the subsequent circuit connected to outputs 19 and 20.

Similarly, if the voltage applied to the base of transistor 12 by the signals received by transistors 11 and 12 is greater than the voltage applied to the base of transistor 11, transistor 12 is turned on. Because the bases of transistors 13 and 14 are fixed, the voltage at the collector of transistor 12 must be reduced to a value sufficient to turn on transistor 14. The conducting transistor 14 generates a current through resistor 18. The emitter follower configuration of transistor 28 couples the voltage on the collector of transistor 14 minus the base-emitter voltage (Vbe) of transistor 28 to output 20. The additional time required to activate transistor 14 increases the delay through circuit 10 without requiring additional current and associated power consumption. The emitter follower configuration of transistors 27 and 28 isolates outputs 19 and 20 from the load of the subsequent circuit connected to outputs 19 and 20.

To perform the function of circuit 10, input 37 is connected to the base of transistor 11 and input 38 is connected to the base of transistor 12. The emitter of transistor 11 is commonly connected to the emitter of transistor 12 and the collector of transistor 23. The collector of transistor 11 is connected to the emitter of transistor 13. The collector of transistor 13 is commonly connected to the base of transistor 27 and to a first terminal of resistor 17. A second terminal of resistor 17 is commonly connected to input 43 and the base of transistor 13. The emitter of transistor 14 is connected to the collector of transistor 12. The collector of transistor 14 is commonly connected to the base of transistor 28 and to a first terminal of resistor 18. A second terminal of resistor 18 is commonly connected to input 43 and the base of transistor 14. The collector of transistor 27 is commonly connected to input 43 and the collector of transistor 28. The emitter of collector transistor 27 is commonly connected to output 19 and the collector of transistor 31. An emitter of transistor 31 is connected to a first terminal of resistor 32, and a second terminal of resistor 32 is commonly connected to return 44, a first terminal of resistor 24, and a first terminal of resistor 34. A second terminal of resistor 34 is coupled to an emitter of transistor 33, and a collector of transistor 33 is commonly coupled to output 20 and to an emitter of transistor 28. Bias control input 39 is commonly connected to the base of transistor 23, the base of transistor 31, and the base of transistor 33. An emitter of the transistor 23 is connected to a second terminal of the resistor 24.

Fig. 3 schematically illustrates a portion of one embodiment of a delay circuit 50, the delay circuit 50 being another embodiment of the delay circuit 10 illustrated in the description of fig. 2. Circuit 50 is similar to circuit 10 except that the base of each cascode transistor is also connected to the collector of the opposite cascode transistor. Similarly, the base of each emitter follower transistor 27 and 28 is also connected to the base of the opposite cascode transistor. Thus, the base of transistor 14 is in turn connected to the collector of transistor 13, and the base of transistor 13 is also connected to the collector of transistor 14. In operation, as the collector voltage of one of the cascode transistors 13 or 14 drops, the base of the opposite cascode transistor also drops, which increases the amount of time it takes to turn on the cascode transistors and thus increases the delay of the circuit 50. For example, if the signal received by transistors 11 and 12 is applied to the base of transistor 11 at a voltage greater than the voltage applied to the base of transistor 12, transistor 11 is turned on. However, because transistor 12 was previously turned on, the collector of transistor 14, as well as the base of transistor 13, are low. Transistor 14 continues to conduct until the voltage at the collector of transistor 11 decreases to a value sufficient to turn on transistor 13. But the base of transistor 13 is low and therefore the voltage on the collector of transistor 11 must become lower to enable transistor 13. The low voltage on the base of transistor 13 requires additional time to activate transistor 13, thereby increasing the delay through circuit 50. In addition, transistor 13 flips quickly once transistor 13 is enabled, thereby reducing the rise and fall times of the edges of the output signals on outputs 19 and 20.

Similarly, if the signals received by transistors 11 and 12 are applied to the base of transistor 12 at a greater voltage than the voltage applied to the base of transistor 11, transistor 12 is turned on. However, because transistor 11 was previously turned on, the collector of transistor 13, as well as the base of transistor 14, are low. Transistor 13 continues to conduct until the voltage at the collector of transistor 12 decreases to a value sufficient to turn on transistor 14. But because the base of transistor 14 is low, the voltage on the collector of transistor 12 must become lower to enable transistor 14. The low voltage on the base of transistor 14 requires additional time to activate transistor 14, thereby increasing the delay through circuit 50. In addition, once transistor 14 is enabled, transistor 14 flips quickly, thereby reducing the rise and fall times of the edges of the output signals on outputs 19 and 20.

Fig. 4 schematically illustrates an enlarged plan view of a portion of one embodiment of a semiconductor device 60 formed on a semiconductor chip (die) 61. In some applications, multiple circuits 10 or circuits 50 or combinations thereof may be used on a semiconductor chip. Chip 61 illustrates several circuits 10 and 50 formed on chip 61. Chip 61 may also include other circuitry not shown in fig. 4 for simplicity of the drawing. Circuit 10 and circuit 50 are formed on chip 61 by semiconductor fabrication techniques known to those skilled in the art.

In view of the foregoing in its entirety, it is apparent that a novel device and method are disclosed. Including, among other features, forming cascode transistors coupled to the differential pair transistors to receive signals from the differential pair. The cascode coupled transistors increase the delay time without increasing power consumption. In addition, an emitter follower transistor is coupled between the cascode transistor and the output of the delay circuit. The emitter follower configuration reduces the load on the cascode transistors and reduces skew between the signals on the outputs of the delay circuits.

While the invention has been described with specific preferred embodiments, many alternatives and variations will be apparent to those skilled in the semiconductor arts. Although the delay circuits 10 and 50 are described with respect to NPN bipolar transistors, the technique is also applicable to PNP transistors and MOS transistors. More specifically, the present invention is described with respect to a particular NPN transistor structure, although the method is directly applicable to other bipolar transistors, as well as to MOS, CMOS, BiCMOS, metal semiconductor fets (mesfets), HFETs, and other transistor structures. In addition, the word "connected to" is used throughout for clarity of description, however, it has the same meaning as the word "coupled to". Thus, "connected" should be interpreted as including either a direct connection or an indirect connection.

Claims (7)

1. A delay circuit, comprising:

first and second differential transistors coupled as a differential pair;

a first cascode transistor having a first current carrying electrode coupled to receive a signal from a first current carrying electrode of a first differential transistor, the first cascode transistor having a control electrode and a second current carrying electrode;

a second cascode transistor having a first current carrying electrode coupled to receive a signal from a first current carrying electrode of a second differential transistor, the second cascode transistor having a second current carrying electrode, wherein control electrodes of both the first cascode transistor and the second cascode transistor are coupled to a power input of the delay circuit, or the control electrode of the first cascode transistor is coupled to a second current carrying electrode of the second cascode transistor and the control electrode of the first cascode transistor is coupled to a second current carrying electrode of the first cascode transistor;

a first emitter follower transistor having a control electrode coupled to receive a signal from a second current carrying electrode of a first cascode transistor, the first emitter follower transistor having a first current carrying electrode and a second current carrying electrode coupled to a first output of the delay circuit; and

a second emitter follower transistor having a control electrode coupled to receive a signal from a second current carrying electrode of a second cascode transistor, the second emitter follower transistor having a first current carrying electrode and a second current carrying electrode coupled to a second output of the delay circuit.

2. The delay circuit of claim 1, wherein the first emitter follower transistor is a bipolar transistor and has a base coupled to a second current carrying electrode of the first cascode transistor and an emitter coupled to the first output of the delay circuit.

3. The delay circuit of claim 1, further comprising: a second current carrying electrode of the first differential transistor coupled to a second current carrying electrode of the second differential transistor.

4. The delay circuit of claim 2, wherein the second emitter follower transistor is a bipolar transistor and has a base coupled to a second current carrying electrode of the second cascode transistor and an emitter coupled to the second output of the delay circuit.

5. The delay circuit of claim 1, further comprising a first load resistance coupled between the first cascode transistor and the power input of the delay circuit.

6. The delay circuit of claim 5, further comprising a second load resistance coupled between the second cascode transistor and a power input of the delay circuit.

7. A method of forming a delay circuit, comprising:

forming a differential pair, the control electrodes of the differential pair being coupled to receive an input signal, the differential pair having a first current carrying electrode;

configuring cascode coupled transistors to receive signals from the differential pair, the cascode coupled transistors having first current carrying electrodes coupled to first current carrying electrodes of the differential pair;

configuring follower-coupled transistors to receive signals from the cascode-coupled transistors and form an output signal representative of and delayed from the input signal, comprising: coupling a control electrode of a first follower transistor to a second current carrying electrode of a first cascode transistor, coupling a first current carrying electrode of the first follower transistor to a first output of the delay circuit, coupling a control electrode of a second follower transistor to a second current carrying electrode of a second cascode transistor, and coupling a first current carrying electrode of the second follower transistor to a second output of the delay circuit, wherein control electrodes of both the first cascode transistor and the second cascode transistor are coupled to a voltage terminal, or a control electrode of the first cascode transistor is coupled to a second current carrying electrode of the second cascode transistor and a control electrode of the second cascode transistor is coupled to a second current carrying electrode of the first cascode transistor; and

a first bias transistor is coupled to a first current carrying electrode of the first follower transistor and a second bias transistor is coupled to a first current carrying electrode of the second follower transistor.