HK1005396B - Timing recovery system for a digital video signal processor, and timing recovery system for a digital signal processor - Google Patents

Description

Timing recovery system for digital signal processor

Technical Field

The present invention relates to digital signal processing systems, and more particularly to a timing recovery system suitable for use in a digital signal receiver, such as a television signal receiver.

Background

The recovery of data from a transmitted signal containing digital video and related information at a digital receiver generally requires three functions to be performed: timing recovery for symbol synchronization, carrier recovery (frequency demodulation) and equalization. Timing recovery is a process of synchronizing the receiver clock (timebase) with the transmitter clock. This allows the received signal to be sampled at an optimum point in time to reduce the chance of clipping errors associated with the decision processing of the received symbol values. In some receivers, the received signal is sampled at a multiple of the transmitter symbol rate. For example, some receivers sample the received signal at twice the transmitter symbol rate. In any case, the receiver's sampling clock must be synchronized to the transmitter symbol clock.

Carrier recovery is a process of frequency shifting a received RF signal to baseband after frequency shifting to a lower intermediate frequency passband to allow recovery of the modulated baseband information. Equalization is the process of compensating for the interference of the transmission channel on the received signal. More specifically, equalization removes inter-symbol interference (ISI) caused by transmission channel interference. ISI causes the value of a given symbol to be distorted by previous and subsequent symbol values. Lee and Messerschmitt describe these functions and related functions in digital communications (Kluwer Academic Press, Boston, MA, USA) in detail.

Existing receivers require that a relatively stable sampling clock signal source be still controllable so that it can lock to the transmitter symbol clock. A voltage controlled crystal oscillator (VCXO) is typically used for this function. The clock signal generated by the VCXO is stable but controllable over a narrow range so that it can be locked to the transmitter symbol clock. However, a voltage controlled oscillator such as a VCXO is an analog component, so it is expensive and tends to shorten its life. Furthermore, if signals must be received from different transmitters having different symbol clock frequencies (such as in the european satellite system), each such transmitter must have a separate VCXO, which further increases the cost of the receiver.

There is a need for a symbol timing recovery system that can support more than one symbol rate. It has also been recognized that there is a need for a timing recovery system that provides performance benefits and cost advantages, such as in terms of hardware requirements, over known types of timing recovery systems, such as those that include multiple VCXOs for each received symbol rate.

Disclosure of Invention

It is an object of the present invention to provide a timing recovery system for a digital signal receiver that receives a signal representing successive symbols from a transmitter. An interpolator coupled to the symbol source is responsive to the control signal for generating samples taken at times synchronized with successive symbols from the transmitter. The control network providing the control signal includes a controlled delay network responsive to the output signal from the interpolator and the nominal delay offset signal.

A timing recovery network for receiving a signal representing successive symbols in a digital signal processing system according to the invention, characterized in that it comprises: an analog-to-digital converter receiving samples representative of a received signal; an interpolator coupled to the analog-to-digital converter and responsive to a control signal representing a predetermined delay signal from a controlled delay network for generating samples taken at times synchronized with successive symbols from a transmitter, and a control network for providing the control signal, the control network including the controlled delay network responsive to an output signal from the interpolator and a nominal delay offset signal, the control network comprising: a phase error detector coupled to the interpolator for detecting a phase error between a sampling time of the transmitter synchronization samples produced by the interpolator and a time of successive transmitter symbols; a nominal delay register; an adder coupled to the nominal delay register; a loop filter coupled between the phase error detector and the summer; and a digitally controlled delay coupled to the adder for generating the interpolator control signal.

Preferably, the digitally controlled delayer comprises: an accumulator for holding a signal representing the time remaining before the interpolator takes the next transmitter synchronous sample; an integer portion selector coupled to the accumulator for counting down the integer portion in the accumulator in response to the fixed frequency clock signal until it reaches zero; a time delay unit for generating a transmitter synchronous sampling clock enable signal when acquiring the transmitter synchronous sampling; and a fractional portion selector coupled to the accumulator for generating the interpolator control signal in response to a fractional portion of the value in the accumulator.

More specifically, the system includes a source of samples representing the received signal, the samples being taken at a fixed frequency. An interpolator is coupled to the sample source and is responsive to the control signal. The interpolator generates samples taken at times synchronized with successive symbols from the transmitter. A phase error detector is coupled to the interpolator and detects a phase error between a time of a sample of the transmitter synchronous samples produced by the interpolator and a time of successive transmitter symbols and provides a phase error signal. The phase error signal is coupled to one input of the adder and the source of the nominal delay signal is coupled to the other input. A digitally controlled delay generates interpolator control signals in response to signals from the adder.

The timing recovery system in accordance with the present invention begins sampling the received signal at a fixed frequency slightly above twice the maximum required transmitter symbol rate. The initially sampled signal is then processed by an interpolator to produce a sequence of samples that is synchronized with the transmitter symbol rate. These synchronized samples are provided to a digital phase error detector. The output of the digital phase error detector is provided to a second order loop filter. A predetermined value representing the desired nominal sampling time delay is added to the output signal of the loop filter. The combination of the predetermined nominal delay and the loop filter output signal controls a digitally controlled delay that provides the integer and fractional clock delay component signals. The integer portion of the clock delay component signal is used to control the generation of a receiver sampling clock signal that is synchronized to the transmitter symbol rate. The sampling clock signal may be further divided in frequency to provide a receiver symbol clock signal. The fractional part of the delay component is applied to the control input of the interpolation filter so that the sampled signal produced by the interpolation filter represents the value of the received signal at the desired sampling time.

The timing recovery system according to the present invention advantageously supports variable symbol rate timing recovery without utilizing multiple analog voltage controlled crystal oscillators as the symbol timing reference. This is achieved by introducing a predetermined nominal delay into the timing control loop. A nominal delay register, controllable by a processor in the receiver, allows selection of any desired receiver sample rate that is less than half of the initial sample rate. Problems associated with multiple specific crystal oscillators utilizing specific symbol rates, such as increased hardware complexity and cost, acquisition time depending on how fast the crystal oscillator frequency can be tuned, etc., are avoided. It is beneficial that the disclosed digital system allows the function of a voltage controlled crystal oscillator to be performed using a single fixed frequency oscillator.

For a receiver that samples an input signal at twice the transmitter symbol rate, the system according to the present invention supports any transmitter symbol rate that is less than half the initial fixed sampling rate. The required frequency accuracy is readily obtained with commercially available crystals because the pull range tested is greater than +/-1000 ppm. The system has been tested and shown to acquire timing lock over a short period of time, exhibiting clusters after 500 samples even with a timing offset of 1000ppm, while locking clusters after thousands of samples. Performance advantages, coupled with the elimination of the VCXO, make the present invention attractive even when single symbol rates are involved.

More specifically, the disclosed system advantageously supports multiple symbol rates, such as those used in european satellite applications. In the example discussed below, the receiver samples the input signal at twice the symbol rate of the transmitter. For example, the disclosed timing recovery system has been shown to support a symbol rate of 20 mega-symbols per second (20M-symbols/second) to 30M-symbols/second with an initial sampling clock frequency of 62 MHz. This gives the ratio of the initial sampling clock frequency to the symbol clock frequency of 62/30 and 62/20. In these expressions, the numerator is the initial sampling rate (MHz) and the denominator is the symbol rate (M symbols/sec). Thus, recovery of 20M symbol/sec and 30M symbol/sec symbol rates is supported in this case with a single fixed 62MHz initial sampling clock frequency from a single fixed crystal controlled oscillator.

Drawings

In the drawings:

FIG. 1 is a block diagram of a Quadrature Phase Shift Keying (QPSK) modulated input signal receiver including a timing recovery network in accordance with the principles of the present invention;

fig. 2 is a block diagram of a symbol timing recovery system in accordance with the principles of the present invention;

FIG. 3 is a more detailed block diagram of an interpolator for use in the system of FIG. 2; and

fig. 4 is a more detailed block diagram of a phase error detector used in the system of fig. 2.

Detailed Description

Fig. 1 is a block diagram of a QPSK modulated input signal receiver, such as a direct broadcast satellite receiver, including a timing recovery network in accordance with the principles of the present invention. The block diagram shown in fig. 1 is conventional in function and configuration, except that element 266 is a symbol timing recovery network in accordance with the present invention.

The input ("input") is coupled to a signal source (not shown) of the modulated QPSK signal, such as an antenna or a cable connection. The input ("input") is coupled to an input processor 262, the processor 262 including an input channel tuner, Radio Frequency (RF) amplifiers, an Intermediate Frequency (IF) amplifier and mixing stages for down-converting the input signal to a lower frequency band suitable for further processing, an automatic gain control network and an output analog-to-digital converter (ADC), which are not shown in the figure but are arranged in a known manner. A fixed frequency oscillator 261, which may be, for example, a crystal oscillator, provides a fixed sampling frequency clock signal AD to the ADC and other circuit elements (e.g., timing recovery network 266) in a manner described in more detail below.

The adjacent baseband output signal from unit 262 is provided to a timing recovery network 266 in accordance with the present invention. The timing recovery network 266 generates samples and other timing signals representative of the transmitted signal synchronized to the transmitter symbol clock in a manner described in more detail below. In the illustrated embodiment, two samples are generated per transmitted symbol. The transmitter synchronized samples and other timing signals are provided to a carrier recovery network 264, which network 264 demodulates the signal to baseband and includes an equalizer, rotator, slicer and phase error detection network, as well as phase controllers for controlling the operation of the equalizer and rotator, all as is known. The baseband demodulated signal from carrier recovery unit 264 is decoded by viterbi decoder unit 272 and deinterleaved by deinterleaving unit 274 before being error detected and corrected by a Reed-Solomon (Reed-Solomon) error detection and correction unit, that is, RS decoder 276 shown in fig. 1. The function of these units is described in the aforementioned article by Lee and Messerschmitt, for example.

The error-corrected signal from the RS decoder 276 is optionally descrambled in a descrambling unit 278. The signal from descrambling unit 278 is provided to an output processor 280, processor 280 providing the functionality required to connect the descrambled data to other signal processing networks. These functions include conforming the data to the appropriate logic levels and providing a clock signal to facilitate interfacing with other networks. Although Motion Picture Experts Group (MPEG) compatibility is not necessary in a system embodying the present invention, the data from the output processor 280 is processed by an MPEG compatible transport processor 282, the MPEG compatible transport processor 282 providing synchronization and error indication information for use in video data decompression. The transport processor 282 also separates data by type based on analysis of the header information. MPEG decompressor 284 decompresses the output data from processor 282 to provide video data suitable for encoding in a predetermined standard, such as NTSC or PAL, for example, with video encoding unit 286. The output signal from the video encoding unit 286 is applied to a video and display processor 288 including an image display (not shown).

The system microprocessor 268 provides initialization parameters and other control signals to the respective elements in the receiver, including the timing recovery network 266, in a known manner. The specific parameters and control signals provided by the system microprocessor 268 to the timing recovery network 266 will be described in greater detail below.

Fig. 2 is a more detailed block diagram of a symbol timing recovery system in accordance with the principles of the present invention. In fig. 2, an analog or simple digital signal is shown in thin lines and a complex digital signal containing real (in-phase) and imaginary (quadrature) component signals in a known manner is shown in thick lines. In the symbol timing recovery system shown in fig. 2, advantageous features include a nominal delay register that allows the designer to select any desired symbol rate that is less than half the input sample rate, and the possibility of a more accurate interpolator design using higher order clusters. Deriving the sign and sampling clock enable signals at the output of the digitally controlled delay operation advantageously enables a fully synchronous design without the need for phase and frequency locked analog components.

IN fig. 2, an input analog signal IN, representing a signal received from a transmitter, is initially sampled and converted to complex digital form by an analog-to-digital converter (ADC)10 (which is part of the input processor 262 IN fig. 1). The ADC10 is clocked by an initial fixed frequency sampling clock AD generated locally by the fixed frequency crystal oscillator 261 (fig. 1). The complex digital data stream from ADC10 is applied to a 4-tap complex interpolator 12 (described in detail below), which interpolator 12 is also clocked by an initial fixed frequency sampling clock signal AD. The aforementioned interpolation function is in effect a timing adjustment function, sometimes referred to as digital phase shift and sample rate conversion. The output of the interpolator 12 is a stream of complex samples generated in synchronism with a fixed frequency sampling clock signal AD, which is pulse-shaped filtered by a fixed (non-adaptive) complex pulse-shaping filter 14, the filter 14 being responsive to the fixed frequency sampling clock signal AD and a sampling clock enable signal (generated as described below). The output of the filter 14 is a filtered complex sample stream that is provided to the other system elements shown in fig. 1. The output of the interpolator 12 is also applied to a phase error detector 16 (described in detail below).

The output of the phase error detector 16 is coupled to respective dividers 20 and 22, the dividers 20 and 22 being implemented as barrel shifters in the illustrated embodiment. A filter loop integer constant Ki is applied to shifter 20 and a loop proportionality constant Kp is applied to shifter 22. The values of the loop integer constant Ki and the loop proportionality constant Kp are calculated by the system microprocessor 268 (fig. 1) in a known manner and provided to the dividers 20 and 22, respectively. An output of the divider 20 is coupled to a first input of an adder 24. An output of adder 24 is coupled to a delay unit 26, and an output of delay unit 26 is coupled to a second input of adder 24 and to a first input of adder 28. The signal from divider 20 is added in adder 24 to a delayed version of the signal from delay 26. An output of the divider 22 is coupled to a second input of the adder 28. The signal from the delay unit 26 is added to the output of the divider 22 in an adder 28. The output of adder 28 is inverted by inverter unit 30 with unity gain. The first and second dividers 20 and 22, the adders 24 and 28, the delay unit 26 and the inverter unit 30 combine to form a second order loop filter. The output of the inverter unit 30 forms the output of the loop filter. This output represents the difference between the interpolation time at which the samples from interpolator 12 were generated and the ideal sampling time for which the transmitter clock was synchronized.

The nominal delay register 31 receives from the system microprocessor 268 of fig. 1 a nominal or expected time delay between sampling times representative of transmitter synchronization. The nominal delay value is calculated by the system microprocessor in the manner described in detail below. In the illustrated embodiment, the received signal is sampled at twice the symbol rate, so the nominal delay between sampled signals is half the desired spacing between transmitted symbols. An output of the nominal delay register 31 is coupled to a first input of an adder 32. The output of the loop filter is added to a predetermined nominal delay value in adder 32. The output signal from the adder 32 is a digital signal representing the instantaneous delay value between samples synchronized to the transmitter symbol clock. The nominal delay register 31 is provided to allow the receiver timing loop to initially approach approximately the input symbol rate to speed acquisition. The pull range of the system is limited only by the characteristics of the phase error detector 16.

The signal value from adder 32 is expressed in terms of the number of fixed frequency clock cycles and includes an integer portion representing the number of whole fixed frequency clock pulses between sampling times and a fractional portion representing the sampling time between two adjacent fixed frequency samples. In the illustrated embodiment, the digital signal from adder 32 is a 22-bit fixed-point digital signal with the two most significant bits carrying the integer portion and the remaining bits carrying the fractional portion. The system microprocessor (fig. 1) inserts values into the nominal delay register 31 in the following manner. First the nominal delay register 31 inserts a signal assigned a logic '1' value into it. The signal is then shifted left by 20 positions. This places the logic '1' signal in the least significant bit of the integer portion. This can be expressed in the following digital logic expression:

1 < RS-IS (1) where RS IS the nominal delay register size, e.g., 22 bits in the illustrated embodiment, and IS IS the size of the integer portion, e.g., 2 bits in the present embodiment. In the illustrated embodiment this expression becomes:

1＜＜(22-2) (2)

a calculation is then made by the system microprocessor to determine the nominal delay between transmitter synchronized samples, expressed as a fixed frequency clock cycle number:

d/(2 · S) (3) where D is the nominal delay between transmitter synchronization symbols expressed as a fixed frequency clock period number, FR is the fixed frequency clock frequency, and S is the transmitter symbol frequency. This calculation is combined with the previous contents of the nominal delay register 31. In order to compensate for the value '1' inserted in the nominal delay register 31 with the result of expressions (1) and/or (2), the value 1 must be subtracted from the nominal delay value D calculated from equation (3). Thus, the expression describing the nominal delay value placed in the nominal delay register 31 by the system microprocessor (FIG. 1) is:

DR31＝(1＜＜(22-2))·(FR/(2·S)-1) (4)

where DR31 is the value stored by the system microprocessor in the nominal delay register 31.

The output signal from adder 32 is applied to one input of multiplexer 34. The other input of the multiplexer receives the value representing the value-1. Adder 36 receives a first input from the output of multiplexer 34. The output of adder 36 is coupled to a delay unit 38 which acts as an accumulator. The accumulator 38 is clocked by a fixed frequency sampling clock signal AD; the same clock signal drives ADC 10. The output of the delay unit 38 is a digital signal MU representing the time delay to the next transmitter sync sample. The digital signal MU contains an integer part representing the number of periods of the fixed frequency clock signal AD until the next transmitter synchronization sample and a fractional part representing the time delay from the last such fixed frequency clock signal until the time of the transmitter synchronization sample.

In the illustrated embodiment, the digital signal MU is a 22-bit fixed-point digital signal with two most significant bits carrying an integer part and the remaining bits carrying a fractional part. Those skilled in the art of digital arithmetic circuitry will appreciate that different sizes and formats may be used. For example, in a Quadrature Amplitude Modulation (QAM) receiver, the time delay is represented by a 26-bit digital signal. The time delayed signal MU is provided to an integer part selector 40 which selects the two most significant bits from the signal MU (MU: 0-1). The integer part is supplied to a comparison circuit 41 which compares the integer with a zero value signal and generates a signal when the integer part equals 0. The time delayed signal MU is also provided to a fractional portion selector 48, and the fractional portion selector 48 generates a signal containing the eight most significant bits of the fractional portion of the signal MU (MU: 2-9), i.e., the most significant bytes of the fractional portion of the time delayed signal MU. This fractional part most significant byte is coupled to a control input of the interpolator 12. The complete 22-bit time-delayed signal MU is coupled to a second input of the adder 36.

The output of comparator 41 is applied to a control input of multiplexer 34 and to delay element 42. Delay unit 42 provides the delay necessary to match the delay between time delayed signal MU and a corresponding output (described in detail below) generated by phase detector 16 in response to time delayed signal MU. The output of the time delay unit 42 is a sample clock enable signal and is applied to an input of a modulo-2 counter 44 and a first input of an and gate 46. An output of the modulo-2 counter 44 is coupled to a second input of the and gate 46. The output of the and gate 46 generates a symbol clock enable signal. Modulo-2 counter 44 comprises, for example, a D-type flip-flop and is divided by 2 in this example. This operation is used in applications that provide two samples per symbol. In other applications, such as where four samples per symbol are employed, the counter 44 may be a modulo 4 counter and have a divide by 4 function.

In operation, the fixed frequency sampling clock AD has a frequency slightly higher than twice the maximum expected transmitter symbol frequency. The system microprocessor 268 (fig. 1) calculates the nominal or expected sampling time period for the symbol rate of the currently receiving signal and loads the nominal delay register 31 with this value. This approximates the start of the operation of a digitally controlled delay device (NCD) with the correct sampling period. The phase error detector 16 and associated loop filter together adjust and lock the NCD to the actual sampling rate of the transmitted signal. The sample clock enable signal from delay element 42 and the symbol clock enable signal from and gate 46 are used by other processing elements in the receiver (shown in fig. 1). For example, the pulse shaping filter 14 (fig. 2) receives a fixed frequency sampling clock AD and a sampling enable clock signal.

As described above, adder 32 generates a digital signal representing the instantaneous time delay from the last transmitter sync sample to the next transmitter sync sample, while NCD accumulator 38 generates a digital signal representing the remaining time until the next transmitter sync sample time. In the illustrated embodiment, these time representative signals are represented by a fixed point 22-bit binary word having two most significant bits carrying an integer part and the remaining bits carrying a fractional part. The time values represented by these signals are expressed in cycles of a fixed-frequency sampling clock AD. Such time representative signals have a range from 0 to 4-2-20. For example, a value of "1" indicates one cycle of the fixed frequency sampling clock AD and has a value of 01000000000000000000002, where the subscript 2 indicates that the value is represented in base 2 or binary format.

The output of comparator 41 is a logic '0' signal if the integer portion of the time delay stored in accumulator 38 is greater than zero. In this state, more than one fixed frequency sampling clock AD period must elapse before the next transmitter sync sample is taken. The accumulator 38 counts down the integer portion value. Multiplexer 34 is conditioned by a logic '0' signal at comparator 41 to couple a-1 valued signal to adder 36. Adder 36 then adds (i.e., subtracts 1) the-1 signal to the signal value in accumulator 38 and stores the newly decremented value in accumulator 38. Furthermore, because the output of comparator 41 is a logic '0' signal, neither the sample clock enable signal nor the symbol clock enable signal (both appropriately delayed by delay unit 42) are in an active state.

The fractional portion of the accumulator 38 value represents the portion of the fixed frequency sampling clock AD period until the next transmitter synchronization sample is taken. The most significant eight bits of the fractional part are used to control the delay of the interpolator 12. This essentially divides the time period between fixed frequency sampling clock AD periods into 256 portions. Thus, the interpolator may be a 256-phase polyphase filter bank. When no more complete fixed frequency sampling clock AD cycles remain before the next transmitter sync sample is taken, the integer portion of the signal in accumulator 38 is 0. In this case, the signal output from the comparator 41 is a logic '1' signal.

When the output signal from comparator 41 is a logic '1' signal, a sample is taken from interpolator 12 at a time controlled by the most significant byte of the fractional part of the accumulator 38 value, and a sample clock enable signal is generated to start the circuitry timing of the subsequent stage and process this newly generated sample. In addition, modulo-2 counter 44 is clocked, and gate 46 also generates a symbol clock enable signal if the transmitter symbol time. At the same time, the adjustment multiplexer 34 passes the signal from the adder 32 to the adder 36. Adder 36 combines the desired transmitter synchronization sampling time with the fractional part of NCD accumulator 38 (the integer part is zero, as described above), thereby placing the time at which the next transmitter synchronization sample is taken in accumulator 38. The loop is closed by the NCD value changing in response to the phase error detector 16 output signal via a loop filter.

The sampling clock allows signals to be provided to system elements such as elements 14, 16, 26, 44 and 46, and all other post-processing elements that process each transmitter sync sample (fig. 1). Such a unit requires a sampling enable signal in addition to the fixed frequency sampling clock signal AD. The symbol clock enable signal is valid for transmitter synchronous samples taken at the transmitted symbol time. The symbol clock allows signals to be provided to those system elements operating on the transmitted symbols, e.g., decision elements associated with a carrier recovery network such as carrier recovery element 264 (fig. 1). Such a unit operates in response to a fixed frequency sampling clock signal AD and a symbol clock enable signal.

For example, if the illustrated embodiment is suitable for use in a satellite broadcast system (e.g., Satlink), the frequency of the fixed-frequency sampling clock signal AD is 62 MHz. One exemplary broadcast signal has a symbol rate of 30 mega-symbols/second. Since the received signal is sampled at twice the symbol rate, the sampling clock enable signal disables the fixed frequency clock signal AD in such a way that the average sampling rate is the required sampling rate of 2 samples per symbol. And thus would be 60 mega samples/second for 30 mega symbols/second and 2 mega disabled fixed frequency sampling clock AD periods per second. The interpolator 12 generates interpolated samples such that at each enabled fixed frequency sampling clock AD period, samples are taken as if at the required transmitter synchronous sampling time. That is, the samples from interpolator 12 have values as if they were taken from ADC10, and ADC10 is clocked at the appropriate sampling frequency, in this example 60 MHz. In the case of an occasional transition of the clock signal (2 mega-bits per second), the sampling occurs at the transition of the 62MHz fixed frequency clock signal AD.

When the disclosed system is used to process Quadrature Phase Shift Keying (QPSK) input signals, it is observed that the bit error rate does not drop by more than 0.1dB near the 4dB signal-to-noise ratio (SNR) threshold where error correction codes often become invalid. The control loop is fully converged during 3000 samples. The loop exhibits convergence at 0dB SNR with about 0.5dB attenuation. These performance characteristics indicate that the disclosed timing recovery system is also applicable to Vestigial Sideband (VSB) modulated input signals of the type proposed for use in large Alliance high definition television (Grand Alliance HDTV) systems. The following table summarizes the system performance of certain SR ratios, which are ratios of a fixed frequency sampling rate (analog-to-digital conversion rate) to a symbol rate, utilizing two samples per symbol.

SR ratio	SNR	Attenuation of
			62/30	9dB	0.2dB
62/30	6dB	0.05dB
			62/30	4dB	0.1dB
62/20	9dB	0.1dB
			62/20	6dB	0.00dB
62/20	4dB	0.04dB

In a system such as a QAM system that samples an input signal with in-phase (I) and quadrature (Q) components, the input I and Q quadrature signals can be sampled at a rate less than twice the symbol rate with the present system and a digital sequence of transmitter synchronization samples generated at twice the transmitter synchronization symbol rate, provided that the fixed frequency sampling clock signal AD rate is greater than a value defined by the equation:

FR＝S×BW_E+ M (5) where FR is the fixed frequency clock signal AD rate; s is the symbol rate; BW (Bandwidth)_EIs the extra bandwidth portion; and M is the boundary of the flat amplitude and group delay bandwidth of the interpolator. In systems with small extra bandwidth, this can reduce the a/D sampling rate by 10% -30% (ideally 49.9%). The digital processing system after the interpolator needs to process multiple samples per unit clock, so it needs to work at a higher clock rate or process data using a parallel approach.

Fig. 3 shows a Farrow-structured segmented parabolic interpolator 12 (fig. 2) implemented as a fixed-point algorithm designed in hardware. The interpolator 12 makes use of a piecewise parabolic filter because in this implementation it forms a low complexity interpolator with sufficient performance. For high order clusters like 64QAM or 256QAM, more complex interpolation filters may be required. Adding the nominal delay signal to the output signal of the loop filter, as shown in adder 32 (fig. 2), advantageously allows the system microprocessor (not shown) to control the nominal delay between the desired transmitter synchronous samples, and the loop need only keep the rate constant.

In particular, the interpolator 12 of fig. 3 is a 4-tap piecewise parabolic filter of the type Lars et al interpolation in the IEEE communication corpus "digital modem" second part: implementation and performance. IN fig. 3, input IN is coupled to the output of ADC10 (fig. 2). The input IN receives a 6-bit sample, carrying a range of values from-32 to +31, and is coupled to: a delay unit 50, an adder 60, a delay unit 51, an adder 61, a delay unit 52, an adder 62, and a delay unit 53 connected in series; and a delay unit 54, an inverting input terminal of the adder 63, a delay unit 55, an adder 64, a delay unit 56, an adder 65, and a delay unit 57 connected in series. The input IN is also coupled to respective inverting inputs of adders 60, 61 and 65, and to a non-inverting input of adder 62. Input IN is also coupled to an input of a x 2 multiplier 68, the output of which is coupled to an input of adder 67 and to the inverting input of adder 66. Adder 66 is coupled to one input of adder 63, and adder 67 is coupled to an input of adder 64. The input IN is further coupled to respective second inputs of adders 66 and 67. The input IN is further coupled to a six time period delay unit 92 and a x 2 multiplier 94 connected IN series.

The control input MU is coupled to the most significant byte of the fractional part of the digitally controlled delay (fig. 2) accumulator 38. Control input MU is coupled to a series connection of multiplier 70, delay unit 72, multiplier 74, limiter 76, delay unit 78, multiplier 80, delay unit 84, and adder 90. An output of delay unit 53 is coupled to a second input of multiplier 70; an output of delay element 57 is coupled to a second input of multiplier 74; an output of the x 2 multiplier 94 is coupled to a second input of the adder 90. A two-cycle delay unit 82 is coupled between the control input MU and a second input of the multiplier 80. An OUTPUT of adder 90 generates transmitter synchronous samples and is coupled to OUTPUT. OUTPUT terminal OUTPUT is coupled to pulse shaping filter 14 (fig. 2).

The interpolator 12 shown in fig. 3 operates in the manner described in Lars et al, supra. The control signal MU represents a time division between adjacent fixed frequency sampling clock AD periods from which transmitter synchronous samples are to be taken. Interpolator 12 shown in fig. 3 interpolates adjacent ADC10 samples at times represented by control signal MU to produce interpolated samples at OUTPUT. In the illustrated embodiment, there is a delay of three fixed frequency clock signal AD periods from the control signal MU input to the interpolated sample output. This delay must be compensated for in the generation of the sample and symbol clock enable signals produced by the digitally controlled delay (fig. 2). Delay unit 42 (fig. 2) provides this time compensation and in the illustrated embodiment is a three clock cycle delay unit.

Fig. 4 is a more detailed block diagram of phase error detector 16 of fig. 2. In fig. 4, mutually quadrature in-phase (I) and quadrature (Q) signal inputs "iin" and "qin" are coupled to respective outputs of the interpolator 12 (fig. 2). The non-inverting input terminal "iin" is coupled to the inverting input terminals of the series-connected delay unit 102, delay unit 103 and adder 108. The non-inverting input terminal "iin" is also coupled to a second input terminal of the adder 108. An output of adder 108 is coupled to a first input of multiplier 110 and an output of delay unit 102 is coupled to a second input of multiplier 110. An output of the multiplier 110 is coupled to a first input of an adder 114.

The quadrature input "Q-input" is coupled to the inverting inputs of the series connected delay unit 104, delay unit 105 and adder 106. The quadrature input "Q-input" is also coupled to a second input of the adder 106. An output of adder 106 is coupled to a first input of multiplier 112 and an output of delay element 104 is coupled to a second input of multiplier 112. An output of multiplier 112 is coupled to a second input of adder 114. The output of the adder 114 produces a signal representing the phase error between the transmitter synchronous sampled signal produced by the digitally controlled delay unit in the receiver and the actual sampling time of the transmitted signal, all in a known manner.

Advantageously, the timing recovery system described herein is capable of processing multiple symbol rate input signals associated with a single clock generated by a fixed frequency oscillator. Furthermore, both the sample clock enable signal and the symbol clock enable signal are derived from the input signal itself. As explained elsewhere herein, the sampling clock enable signal indicates that the output of the interpolator is sampled at a rate that is a multiple of the symbol rate.

The disclosed system advantageously supports multiple input sample rates using a fixed pulse shaping filter 14 and a fixed frequency clock oscillator 261. The structure of the filter 14 need not be modified to accommodate multiple input symbol rates. A pulse shaping filter 14 located after the timing recovery network filters the signal with the same pulse shaping characteristics, thereby enhancing its signal-to-noise performance.

The symbol timing recovery system according to the present invention is applicable to, for example, Binary Phase Shift Keying (BPSK), Quadrature Phase Shift Keying (QPSK), carrierless amplitude modulation (CAP), and Quadrature Amplitude Modulation (QAM), as well as to VSB modulation systems such as those employed by the Grand Alliance (Grand Alliance) High Definition Television (HDTV) system proposed for the united states. Those skilled in the art will recognize what design changes need to be made to adapt the disclosed symbol timing recovery system to a desired modulation and will understand how to design the illustrated components to operate at the desired modulation. It has been observed that the above system achieves lock in a relatively short period of time. It is known that a Quadrature Phase Shift Keying (QPSK) symbol cluster locks after thousands of samples and that the cluster is visible after 500 samples, even with a timing offset of 1000 ppm. These performance characteristics are accompanied by reduced hardware requirements due to digitally performing voltage controlled oscillator functions, making the system attractive even when operating with respect to a single symbol rate.

In the disclosed embodiment, the sampling clock enable signal enables and disables the clock signal AD via the clock enable/disable terminals on the respective units, rather than enabling and disabling the fixed frequency oscillator 261 itself. The gated clock is also an option and may be considered as required by a particular system.

Claims (9)

1. A timing recovery network for receiving a signal representing successive symbols in a digital signal processing system, comprising:

an analog-to-digital converter (10) receiving samples representative of a received signal;

an interpolator (12) coupled to the analog-to-digital converter and responsive to a control signal representing a predetermined delay signal from a controlled delay network for generating samples taken at times synchronized with successive symbols from the transmitter, an

A control network (16, 20-30, 34-46) for providing said control signal, said control network including said controlled delay network responsive to an output signal from said interpolator and a nominal delay offset signal, said control network comprising:

a phase error detector coupled to the interpolator for detecting a phase error between a sampling time of the transmitter synchronization samples produced by the interpolator and a time of successive transmitter symbols;

a nominal delay register;

an adder coupled to the nominal delay register;

a loop filter coupled between the phase error detector and the summer; and

a digitally controlled delay coupled to the adder for generating the interpolator control signal.

2. The timing recovery network of claim 1, wherein:

the samples are taken at a fixed frequency.

3. The timing recovery network of claim 1, wherein said digitally controlled delayer comprises:

an accumulator for holding a signal representing the time remaining before the interpolator takes the next transmitter synchronous sample;

an integer portion selector coupled to the accumulator for counting down the integer portion in the accumulator in response to the fixed frequency clock signal until it reaches zero;

a time delay unit for generating a transmitter synchronous sampling clock enable signal when acquiring the transmitter synchronous sampling; and

a fractional portion selector is coupled to the accumulator for generating the interpolator control signal in response to a fractional portion of the value in the accumulator.

4. The timing recovery network of claim 1 wherein the interpolator is a four-tap piecewise parabolic filter.

5. The timing recovery network of claim 1, wherein:

the received signal represents successive symbols generated at one of a plurality of symbol rates;

the nominal delay register generates a nominal delayed signal having a delay value corresponding to a nominal time delay between successive symbols in the received signal.

6. The timing recovery network of claim 5, wherein: the fixed frequency is greater than twice the maximum required transmitter symbol rate.

7. The timing recovery network of claim 2, wherein: the fixed frequency is greater than twice the maximum required transmitter symbol rate.

8. The timing recovery network of claim 7, wherein the fixed frequency is 62MHz and the symbol rate of the transmitter synchronization is 30M symbols/second.

9. The timing recovery network of claim 7, wherein the fixed frequency is 62MHz and the symbol rate of the transmitter synchronization is 20M symbols/second.