HK1017567A - Method of forming interconnections on electronic modules - Google Patents

Description

Method for forming interconnection of electronic modules

The invention relates to a method for forming interconnections on printed circuit board electronic modules. The interconnection of the present invention includes flip-chip methods that can be reliably used with printed wiring boards.

With the further development of the semiconductor industry, circuits are generally designed to occupy as little space as possible. Circuit space has a saving value, and miniaturization of the circuit can increase speed, reduce noise, and bring other performance advantages. In combination with the need to conserve circuit space, the circuit interconnects should be designed to operate reliably under the desired operating conditions.

Vias are often utilized with Integrated Circuits (ICs) to provide the necessary connections between the internal circuitry of the integrated circuit and external interfaces, such as printed wiring board electronic modules. This interconnection can be accomplished in two ways. In the first method, the vias are completed by metal pads that are wire bonded to the leadframe. If desired, the back or inactive side of the semiconductor device is metallized so that the device can be soldered to a heat sink for heat dissipation, and the entire device is then molded in a plastic package. In assembly, a lead frame extending from the inside to the outside of the plastic package is soldered to a Printed Wiring Board (PWB). However, wire bonding is a major cause of signal parasitic inductance, especially when the loop length is not strictly minimized. Such parasitic inductances disturb the signal frequency.

A second method, commonly referred to as "flip-chip" is to apply a conventional metal deposition process to the via pads to form a suitable layered metallization structure on which a metal bump (bump) is formed through which the semiconductor device may be directly bonded to the substrate. Flip-chip or direct die attach mounting techniques are used to increase circuit density. Flip-chip mounting techniques involve flipping the die and directly connecting the active or top surface of the semiconductor device to the printed wiring board. This saves significant space on the integrated circuit and substrate since the actual semiconductor die size is much smaller than a typical semiconductor package. This approach saves real packaging costs, space for the integrated circuit and substrate.

Flip-chip technology uses conductive bumps, such as tin-lead solder or gold, to provide input/output interconnections between circuitry on a silicon chip and circuitry on an electronic module substrate. The basic connection scheme consists of a die input/output (I/O) pad to which a flange has been applied, plus a matching set of base solder wettable pads. These die input/output pads are formed by etching vias through a passivation layer and then evaporating an appropriate layer of material through a mask to seal the vias. Solder alloy is then deposited on the solder joint to form a solder flange. At the same time, a base solder wettable pad is formed, such as by reflow, to interface with a flange on the integrated circuit. The flux is used to remove oxides from the metal surface to enhance a strong metallurgical bond. The reflow step may be accomplished in a vapor phase or infrared oven or by a localized heat source. The use of flip-chip on printed wiring boards is desirable because of its simplicity, low cost, high density and reliability.

However, conventional flip-chip technology suffers from several drawbacks, one of the major problems is that the direct connection of the device to the printed wiring board provides only a small opportunity for relative movement between the device and the printed wiring board. Conventional printed wiring boards are made of a substrate material such as glass fiber reinforced epoxy or polyurethane, which have a coefficient of thermal expansion that is very different from that of silicon constituting most semiconductor devices. Therefore, when the circuit is subjected to temperature change, the expansion and contraction rates of the printed circuit board and the semiconductor device are different. As a result of stress generated due to different thermal expansion rates, the solder joints are broken, resulting in failure of the electronic product.

Another problem associated with conventional flip chip technology is the metallurgical incompatibility of semiconductor devices, typically incorporating aluminum solder joints, and printed wiring boards, which are relatively easy to deposit and suitable for metal bonding. However, aluminum solder joints are not solderable to tin-lead solder. Therefore, the flip-chip technology firstly ensures that the geometric shape of the welding point of the semiconductor device meets the requirement of the printed circuit board; then, a barrier metal is deposited on the welding point, and a layer of copper is covered on the barrier metal. The barrier metal protects the aluminum device solder joints from the copper. A flange is formed on the copper layer for interconnection with a printed wiring board. Conventional flip-chip methods use tin-lead solder to form the flanges, but with solder flanges, a distance must be maintained between the flanges to prevent connection between the flanges in reflow soldering, thus limiting the input/output density or "pitch" of the device. To meet the demand for high density electronic components, gold flanges are used to connect with tin by thermocompression bonding on copper pads of printed wiring boards. However, the high price of gold has limited the widespread use of such products. Therefore, there is a need for a reliable flip-chip flange connection that takes into account the problems encountered under varying temperature conditions, provides a high density of fine pitch interconnects, and is cost effective.

It is therefore an object of the present invention to provide a method suitable for interconnecting a semiconductor device and a printed wiring board. Another object is to provide a method of interconnecting a semiconductor device and a printed wiring board to solve any problems associated with mismatch in thermal expansion coefficients.

It is a further object of the present invention to provide a method for interconnecting a semiconductor device and a printed wiring board which is inexpensive, occupies little space, and does not require the use of wire bonding.

The above and other advantages are verified in the present invention which describes a method of forming an interconnection between a printed wiring board and an integrated circuit, and also includes a method of forming a metallized via bond pad on an integrated circuit for flip-chip bonding.

Fig. 1 depicts the use of a flip-chip connection flange that is used to obtain interconnection with a printed wiring board substrate.

Fig. 2 depicts a layered structure of a metalized via pad.

Fig. 3 depicts the formation of a printed wiring board substrate and flip-chip connection flange eutectic interconnection.

Fig. 4 depicts a perspective view of an integrated circuit having a plurality of flip-chip connection bumps and interconnected to a printed wiring board substrate.

It is an object of the present invention to provide materials and methods for forming flip-chip interconnections that are inexpensive and robust for connection to printed wiring board electronic modules, such as for connection to automotive electronic modules.

The novel features of the present invention include: (1) metallization of via bond pads (2) metallurgy of the plating on the pad and substrate bond pads, and the process and principles of bond formation. In accordance with the present invention, via-pad metallization and flange metallization may be used separately or in combination, in other words, via-pad metallization as described herein may be used with other flange metallization, and similarly, flange metallization as described herein may be used with other via-pad metallizations.

As shown in FIG. 1, the metallization of via pads 12 on an integrated circuit silicon wafer 10 includes a diffusion barrier layer 14, preferably sputtered titanium-tungsten, on the initial metallization layer, preferably having a thickness of 8-12KA⁰Preferably, the initial metallization layer disposed in mating contact with the silicon wafer 10 is aluminum orCombinations of aluminum and other metals, such as Al/2% Cu or Al/1% Si/0.5% Cu, preferably having a thickness of 10-20KA⁰. The titanium-tungsten layer, which acts as a diffusion barrier, bonds well to the underlying aluminum layer. Covering a titanium-tungsten layer with an oxidation-preventing layer, preferably 10KA⁰A sputtered copper layer 16; this layer provides oxidation resistance to the titanium-tungsten layer during subsequent electroplating and provides adhesion to the "stud" (stud).

The next step involves the application of a primary metallization layer, preferably copper, silver or nickel studs, preferably 25-45 μm thick, which is electroplated onto the sputtered copper layer 16 and provides the primary metallization for the flange 20. The result is metallization of the via pad 12 and the creation of a flip-chip bonding pad 20 thereon.

As shown in fig. 2 and 3, the flip-chip interconnection of the present invention involves the use of a first metal for the flange 20 and a second metal on the base pad 22, the base pad 22 interconnecting the conductive traces on the printed wiring board 26 and forming an effective metallurgical bond between the first and second metals by forming a eutectic phase through the interfacial region 28. The flange 20 is obtained from a first metal by a well-defined flange forming process, such as an electroplating process. A second metal is applied as plating 24 on the solder joints 22 interconnecting the wire traces on the printed wiring board substrate 26, again by well-established methods such as electroplating.

In a preferred embodiment, the first metal is zinc and the second metal is tin. Also in this embodiment, when the flange 20 is comprised of zinc, it is preferably between 25-75 μm in height depending on the particular application. On the zinc flange 20, a gold plating layer is preferably applied by electroplating, preferably to a thickness of 5-20 μ in or 0.13-0.51 μm, for protection against oxidation prior to formation of the interconnect. In the preferred embodiment, the plating 24 on the substrate pad 22 on the printed wiring board substrate 26 is comprised of a layer of tin, preferably tin matte, preferably having a thickness of 300-400 μ in (i.e., 7.62-10.16 μm), disposed on the copper substrate pad 22 interconnecting the conductor traces 31. An optional nickel layer is used as a barrier layer between the copper and tin layers to prevent diffusion of copper through the tin layer, preferably at a thickness of 90-300 μ in (i.e., 2.29-7.62 μm), and may be used depending on the operating conditions of the module. An additional optional layer, an oxidation resistant layer, preferably a gold flash coating, having a preferred thickness of 5-20 μ in (i.e., 0.13-0.51 μm) may be used to prevent oxidation of the nickel and/or tin layer prior to interconnect formation.

For the formation of the interconnection between the flange 20 and the weld 22, the plating 24 on the flange 20 and the weld 22 are in contact to form a direct connection. In a preferred embodiment, an energy source is provided to raise the temperature of the contact surface to 240-. The preferred heating method of the present invention is a reflow or hot pressing method, in which a pressure of 0-250g for 5-15 seconds is a key process parameter.

When the temperature rises to the preferred range of 240-. The second metal tin has a melting point of 232 c and forms a eutectic phase 26 between tin and zinc, the eutectic temperature being 199 c. The eutectic phase 26 provides a stronger bond between the flange and the substrate. The melting points of zinc and tin-zinc eutectic make the interconnection suitable for automotive and other electronic applications.

The entire zinc flange 20 does not melt during this process, the melting point of zinc being 420 c, which maintains the standoff height of the flange and prevents bridging between the flanges. Thus, the flanges do not collapse, which solves the problem of die attach that plagues conventional "controlled collapse". The larger standoff height improves the fatigue life of the flange interconnect. It is noted that the fatigue life of the flange and the shear strain of the flange become inversely proportional, and the shear strain is inversely proportional to the seat height of the flange after the interconnection is formed.

In this process, the gold on the bottom surface of the zinc flange, in only a small proportion, will dissolve in the eutectic phase and the gold on both sides of the zinc flange will remain and continue to provide the flange with corrosion protection in use of the module.

The thermal conductivity of zinc is 116W/(mk), and the electrical resistance is 5.9X 10^-8Ohm, these properties are satisfactory for use in electronic connectionsThe functional requirements of the flange for heat rejection and loss.

The zinc flip-chip connection flange of the present invention provides comparable performance and reliability while also providing a substantial cost savings over alternative gold flanges. For example, in the U.S. metal market at 3 months 1995, the price of gold is $ 381.40 per ounce, while the price of zinc is $ 0.47 per pound, with a price difference of greater than 11800 times.

In another embodiment, zinc is used as the first metal and indium is used as the second metal, the melting points of zinc and indium being 420 ℃ and 157 ℃, respectively, and the indium/zinc eutectic temperature being 144 ℃. In accordance with the process described above, the preferred process temperature should be in the range of 170-190 deg.C, with the other process and dimensional parameters being the same as in the first embodiment of the present invention.

In a third embodiment of the present invention, tin is used as the first metal and indium is used as the second metal. The melting points of indium and tin are 157 ℃ and 232 ℃ respectively, and the indium/tin eutectic temperature is 120 ℃. In the preferred embodiment, the process temperature is in the range of 170-190 ℃, and other process and dimensional parameters are the same as in the first embodiment. It is notable that the thermal conductivity of tin is 66.6W/(mk), and the electrical resistance is 11.5 × 10^-8Ohm. Therefore, the third embodiment is also suitable for a desired application.

In a fourth embodiment, bismuth may be used as the first metal and tin as the second metal, with the melting points of bismuth and tin being 271 ℃ and 232 ℃, respectively, and the temperature of the bismuth/tin eutectic being 139 ℃. In the preferred embodiment, a suitable process temperature should be in the range of 245-265 ℃. The process and dimensional parameters provided in the first embodiment are also applicable to the fourth embodiment, the thermal conductivity of bismuth is 7.87W/(mk), and the electrical resistance is 107 × 10^-8Ohm.

In practice, the method of forming the flange interconnections provided in the present invention is very useful because it involves no toxic components, is environmentally friendly, and is fluxless in the process of the present invention because no flux is required for the formation of the interconnections, which is quite advantageous because the residual flux is detrimental and corrosive to the performance of the circuit.

To further enhance the reliability of the flange interconnection, an epoxy underfill may be used for flip-chip connections on the electronic module. In this way, the mechanical load on the flip-chip connection flange is greatly reduced during use of the electronic module, which makes the interconnection reliable over the lifetime of the product. The underfill will also provide additional corrosion protection to the flange.

The method is particularly suited for use in connection with automotive, consumer, military and other electronic assembly applications.

While the foregoing has described in detail the various embodiments and best modes for carrying out the invention, those familiar with the art to which this invention relates will recognize various alternative designs and embodiments for practicing the invention as defined by the following claims.

Claims (2)

1. A method of forming an interconnection between a printed wiring board and an integrated circuit, comprising:

forming a via pad on the integrated circuit;

forming a flip-chip bonding flange of a first metal on said via bond pad;

providing a substrate pad on the printed wiring board;

applying a coating of a second metal to said substrate welds; and

a bond is formed between the first metal and the second metal to interconnect the printed wiring board and the integrated circuit.

2. The method of claim 1 wherein said first metal is zinc and said second metal is tin.