HK1031958B - Apparatus and method for radio communication - Google Patents

Description

Apparatus and method for wireless communication

Technical Field

The present invention relates to the technical field of devices and methods for wireless communication in a frequency range divided into channels, and more particularly to the part of the field that is relevant for channel selection in the frequency range.

State of the art

The radio frequency spectrum is divided into frequency ranges for different applications, such as radio, television, mobile telephony, satellite communications, radar, and aeronautical and maritime radios. These frequency ranges are often subdivided into a plurality of channels on which independent information can be transmitted. The frequency spacing between channels in a frequency range is commonly referred to as channel spacing or carrier separation. The multiple frequency ranges for a mobile phone are divided into channels such as the mobile phone system Advanced Mobile Phone Service (AMPS), the global system for mobile communications (GSM), and the personal communication system 1900(PCS 1900). However, the channel spacing may be different between the various systems.

Sometimes the same frequency range is used for different applications and the channel spacing may be different for different applications. However, in general, the same frequency range cannot be used for different applications simultaneously in the same geographical area, because signals associated with different applications may interfere with each other.

In wireless communication, in a frequency range divided into a plurality of channels, it must be possible to select with high accuracy a channel to be used for reception or transmission in a given time. Early models of receivers (beginning in the 1920 s) were so-called direct receivers. In a direct receiver, channel selection is accomplished by using a bandpass filter with a variable center frequency. However, it is difficult to design a variable band-pass filter with good selectivity because the center frequency is varied over a large frequency range. So, today, channel selection at reception is done in another way. One approach is to use a filter with a fixed frequency characteristic and good selectivity to frequency shift the received video signal by using an oscillator signal whose frequency is selected relative to the frequency characteristics of the channel and filter to be selected. For example, channel selection in a superheterodyne receiver or a homodyne receiver is based on these principles. For example, when mixing a modulated baseband or intermediate frequency signal to a desired channel in the radio frequency range, the oscillator signal may also be used for channel selection at transmission.

Therefore, it is desirable to be able to generate oscillator signals when selecting channels for reception and/or transmission in a certain frequency rangeFor the oscillator signals, the mutual frequency difference between the oscillator signals corresponds to the channel spacing in the frequency range. Of course, frequency synthesizing circuits have been developed for this purpose. One type of frequency synthesizing circuit is known as a Phase Locked Loop (PLL). With the aid of a phase-locked loop of conventional type, a phase-locked loop having a frequency equal to f can be generated by using a reference frequency_ref(N/R), where N and R are any integer. In order to be able to generate an oscillator signal for channel selection in a frequency range with a certain channel spacing by using such a phase locked loop, the reference frequency should be divisible by the channel spacing if a low noise level and a good loop bandwidth are to be achieved. If the available frequency to be used as the reference frequency is not divisible by the channel spacing, it can be multiplied by the appropriate integer K by using a frequency multiplier. One disadvantage of this solution is that the frequency multiplier needs to occupy space and power. A further disadvantage of this solution is the risk that the reference frequency obtained from the frequency multiplier is too high to be suitable for use in currently available circuits. This risk is particularly high if there is a need to generate the oscillator signal in several frequency ranges with different channel spacings.

Another type of frequency synthesizing circuit is the so-called fractional-N Phase Locked Loop (PLL). According to a reference frequency f_refBy using a fractional-N PLL circuit it is possible to generate a PLL having a frequency equal to f_ref(N + F/Q)/R, where N, F, Q and R are freely selected integers. A fractional-N PLL circuit is typically used to achieve faster adjustment of the oscillator signal frequency, which is an advantage suitable for applications using frequency hopping. An example of the design of a fractional-N PLL circuit is given in patent specification GB, a, 2091960.

Patent specification WO, AL, 96/08883 describes how a fractional-N PLL can be used in a dual mode radiotelephone. It makes it possible to provide a radiotelephone for use in GSM (channel spacing of 200kHz) and in satellite communications (channel spacing of 5 kHz). The intention is to be able to generate oscillator signals for channel selection with a large channel spacing (GSM) and a small channel spacing (satellite) in a cost-effective manner. This patent document proposes a frequency synthesis circuit using a combination of fractional-NPLL and so-called Vernier loop technique. (in Vernier loop technology, two phase locked loops with slightly different comparator frequencies are used, which enables the generation of an oscillator signal for channel selection for channel spacing corresponding to the difference frequency between the comparator frequencies in order to obtain the frequencies for both communication systems.) this design can also be used in situations where the available reference frequency cannot be divided by all channel spacings. However, this design has drawbacks. The design is relatively complex, requiring a large amount of space, relatively high current and power.

Summary of The Invention

The present invention relates to wireless communication devices including wireless communication means for communicating (receiving and/or transmitting) in one or more frequency ranges having associated channel spacings. The wireless communication device uses the oscillator signal for channel selection in a frequency range. The wireless communication device also includes a system clock that generates a clock signal having a predetermined frequency that is not divisible by all of the channel spacing. A first problem solved by the present invention is to obtain in such a radio communication device a frequency synthesizer circuit that can be used to generate the oscillator signal that is used by the radio communication device for channel selection in all frequency ranges. Another problem solved by the invention is that the frequency synthesizing circuit is small in size and consumes little power and current.

The general solution to the above problem lies in: the wireless communication device includes a frequency synthesizing circuit in the form of a fractional-N PLL circuit designed to utilize a clock signal as a reference frequency signal.

It is therefore an object of the present invention to exploit the possibility of frequency division by rational numbers provided by a fractional-N PLL circuit to enable the use of an available clock signal as a reference frequency signal, even if the frequency of the clock signal is not divisible by all channel spacings. The invention also includes the use of such a wireless communication device and a radiotelephone incorporating such a wireless communication device.

The above problem is more particularly solved by a fractional-N PLL circuit having one or more controllable oscillators. A controllable oscillator is connected to the wireless communication device and an oscillator signal generated by the controllable oscillator is used for channel selection in the wireless communication device. The fractional-N PLL circuit controls the controllable oscillator so as to generate an oscillator signal having a frequency corresponding to the frequency of the clock signal multiplied by a factor (N + F/Q) R, where N, F, Q are integers selected according to the present invention with respect to the clock signal frequency, the channel spacing, and the design of the wireless communication device, thereby selecting a desired channel.

The invention has the advantage, in addition to solving the above-mentioned problems, that the fractional-NPLL circuit can utilize a comparator frequency that is higher than the channel spacing, which results in lower noise and faster setting when generating the oscillator signal.

The invention will now be described in more detail by means of preferred embodiments and with reference to the accompanying drawings.

Brief Description of Drawings

Fig. 1 is a block diagram of a phase locked loop.

Fig. 2 is a block diagram of a fractional-N PLL circuit.

Fig. 3 is a block diagram of a wireless communication device.

Fig. 4 is a view of a wireless telephone for communication in the AMPS system and the PCS1900 system.

Description of the preferred embodiments

Fig. 1 shows a block diagram of a frequency synthesizing circuit, more specifically a phase locked loop (usually denoted by the acronym PLL), which is well known in the art. The phase locked loop shown in fig. 1 comprises a reference frequency divider 1 and a main frequency divider 2. The reference divider 1 is arranged to receive a signal having f_refOf the reference frequency of (a). The reference frequency divider 1 is also arranged to generate a first divided signal from the reference frequency signal by division corresponding to the integer R, the divided signal having a first frequency f1(f1 ═ f)_refR) is added. The first frequency f1 is sometimes referred to as the comparator frequency. The reference divider 1 is arranged to receive a first control signal c1 for determining the value of the integer R. The main frequency divider 2 is connected to a controllable oscillator 3 and is arranged to receive a signal generated by the controllable oscillator and having f_outTo output an oscillator signal of a frequency. The main frequency divider 2 is arranged to generate a second divided signal from the oscillator signal by a frequency division corresponding to an integer N, the second divided signal having a second frequency f2(f2 ═ f)_outand/N). The main frequency divider 2 is also arranged to receive a second control signal c2 for determining the value of the integer N.

The phase locked loop shown in fig. 1 comprises a phase comparator 4 connected to the reference frequency divider 1 and the main frequency divider 2. The phase comparator 4 is arranged to receive the first and second divided signals. The phase comparator 4 is arranged to generate a phase difference signal e corresponding to the phase difference between the first and second divided signals.

The phase locked loop shown in fig. 1 comprises means for generating a third control signal c3 for controlling the controllable oscillator in dependence on the phase difference signal e. The phase locked loop thus comprises a loop filter 5 connected to the phase comparator 4 for receiving the phase difference signal e. The loop filter 5 is arranged to generate the third control signal c3 by filtering the phase difference signal e. The controllable oscillator 3 is connected to the loop filter 5 for receiving the third control signal c 3. The loop filter 5 is arranged to generate the third control signal c3 such that the phase difference between the first and second divided signals isAnd (4) eliminating. This means that the first and second frequencies are equal later, which also means that the output frequency f is equal_outWill be given later by:

fig. 2 shows a block diagram of another frequency synthesis circuit known in the art, more specifically a so-called fractional-N Phase Locked Loop (PLL). The block diagram shown in fig. 2 has great similarity to the block diagram shown in fig. 1. Thus, the block diagram shown in FIG. 2 includes: a reference divider 11, a main divider 12, a controllable oscillator 13, a phase comparator 14, and a phase locked loop 15. The reference frequency divider 11 is arranged to receive a first control signal c1 and the main frequency divider 12 is arranged to receive a second control signal c 2. The phase locked loop 15 is arranged to generate a third control signal c3 for controlling the controllable oscillator in a corresponding manner to the loop filter 5 shown in fig. 1. The only difference in form between block diagram 1 and block diagram 2 is that the main frequency divider 12 of figure 2 is arranged to perform a frequency division corresponding to a rational number N + F/Q, N, F and Q being integers whose values are determined by the second control signal c2 of figure 2. By using the frequency synthesizer circuit shown in fig. 2, therefore, the output frequency fout will be given later by:

like the phase locked loop shown in fig. 1, phase locked loops are commonly used in wireless applications for generating an oscillator signal that is received and summed in a wireless communication deviceAnd/or used for channel selection when transmitting. In order to select channels within a frequency range with a certain channel spacing CS, it must be possible to generate a series of oscillator signals with a mutual frequency difference corresponding to the channel spacing CS. When generating the oscillator signal using the phase locked loop of fig. 1, the same comparator frequency should be used, since the comparator frequency has to be taken into account when designing the loop filter 5. In addition, the comparator frequency should not be lower than the channel spacing CS in order to obtain a low noise level and a suitable loop bandwidth. In view of these conditions and the equation (1), it can be seen that the reference frequency f_refMust be divisible by the channel spacing CS to make it possible to use the phase locked loop shown in fig. 1.

When generating the reference frequency signal, a reference oscillator is typically used. The frequency of the reference oscillator often cannot be chosen arbitrarily. An example of this is when the wireless communication device in question includes a system clock for generating clock signals that are used in different timing formats. It is then desirable (as required in some wireless communication systems) to be able to use the system clock as a reference oscillator. If the frequency f0 of the clock signal is not divisible by the channel spacing CS, the clock signal cannot be used directly as a reference frequency signal for the phase locked loop. The remaining alternative is to multiply the frequency f0 of the clock signal by the appropriate integer K by a frequency multiplier. The frequency multiplier consumes both space and current. Another disadvantage of using a frequency multiplier is the risk that the reference frequency f must be used_refBecomes higher than the frequency that the phase locked loop can handle. Circuits currently available on the market and commonly used in mass-produced consumer products can handle reference frequencies up to about 30 MHz; commercially available circuits can handle frequencies up to about 40MHz, but have limited options. This drawback becomes particularly serious when the wireless communication device in question is to communicate in a plurality of (n) frequency ranges related to the channel spacing CS 1. Let θ (J, L) represent the highest common integer factor of two arbitrary integers J and L. A plurality of (n) values p1, pn is now cyclically specified according to the following equation:

p1≡CS1/θ(f0，CS1) (3)，

the smallest integer Kmin which the clock signal has to be frequency multiplied in the frequency multiplier is then given by:

if the frequency f0 of the clock signal is not divisible by most of the channel spacing CS 1. In addition, in many technical systems the predetermined frequency of the clock signal is relatively high (not unusual in the order of 10MHz), which does not make the situation improved.

As a specific example, a dual mode radiotelephone for use with the AMPS system and the PCS1900 system will be discussed. The channel spacing in AMPS is 30kHz and in PCS1900 system is 200 kHz. The timing in the PCS1900 system is based on a clock signal having a frequency of 13 MHz. Formulae (3), (4), and (5) give K_minThis means a reference frequency f of 39MHz_ref. As mentioned above, the choice of commercially available circuits that can handle such high frequencies is relatively limited, and it is therefore desirable to not have to use such high reference frequencies.

According to the invention, it will now be shown that a clock signal from the system clock with frequency f0 can be used directly as a reference frequency signal in frequency synthesis without the need for a frequency multiplier, irrespective of the relationship between the clock signal frequency f0 and the channel spacing CS 1. According to the invention, it is proposed to use a fractional-N PLL technique in the frequency synthesis. In light of the above, we now use f0 ═ f_ref. As can be seen from equation 2, for some given channel spacing CSi, a series of oscillator signals having a mutual frequency difference corresponding to this channel spacing CSi can be derived using the frequency synthesis circuit shown in fig. 2 by selecting the integers Q and R according to:

QR＝f_ref/θ(f_ref，CSi) (6)

by increasing or decreasing the integer F by Csi/θ (F)_refCSi), the output frequency f from the fractional-N PLL circuit_outWill increase or decrease corresponding to the channel spacing CSi. For the fractional-N PLL circuits available today, the integer Q can only be chosen to be 5 or 8. Thus, the right part of formula (6) must theoretically contain a factor of 5 or 8 to function. However, in practice, this is almost always true. As will be appreciated by those skilled in the art, the integers N and F are selected in consideration of the frequency range over which communication is to take place and the design of the wireless communication device used in the communication.

Reference is again made to the previous example of a dual mode radiotelephone. In order to generate the oscillator signals for channel selection according to the invention in an AMPS system, the integers are selected as Q-5 and R-260. Another advantage is that the comparator frequency (50kHz) is then higher than the channel spacing, which means that the oscillator signal is less noisy and adjusts more quickly. For channel selection in the PCS1900 system, integers are selected such that Q is 5 and R is 13, so the comparator frequency becomes 1 MHz. Since the reference frequency of 13MHz is divisible by the channel spacing of the PCS1900 system, the integer R can of course be chosen in the same way as in a conventional phase locked loop, i.e. R65 (F0, Q is arbitrary), in which case the comparator frequency becomes equal to the channel spacing (200 kHz).

Fig. 3 shows a block diagram of an example of a wireless communication device 20 according to the invention. To make the example more specific, the wireless communication device 20 of FIG. 3 is intended for use in a dual-mode radiotelephone for AMPS and PCS 1900.

The wireless communication device 20 of fig. 3 comprises an antenna 21. The wireless communication device 20 also includes wireless communication means connected to the antenna for communicating in the first frequency range of AMPS with a channel spacing of 30kHz (824-894MHz) and in the second frequency range of PCS1900 with a channel spacing of 200kHz (1850-1990 MHz). The wireless communication device 20 includes first and second receiver chains 23 and 25 for downlink communications of the AMPS and PCS1900 systems, respectively. The wireless communication device 20 also includes a transmitter chain 27 for the uplink of both systems. The frequency synthesiser circuit 29 is arranged to generate an oscillator signal having a predetermined frequency for use in channel selection in the first and second receiver chains 23, 25 and the transmitter chain 27.

The first receiver chain 23 is connected to the antenna through a duplex filter 31 and a band splitter 23 that splits between the AMPS range and the PCS1900 range. The first receiver chain 23 comprises an amplifier 37 connected to the duplex filter 31. The first receiver chain 23 comprises a first band pass filter 39 connected to the amplifier 37. The frequency splitter 35, the duplex filter 31 and the first bandpass filter 39 in the first receiver chain 23 are arranged such that the first receiver chain 23 receives radio frequency signals via the antenna 21 having a frequency corresponding to the downlink range of AMPS in the frequency range of 869-894 MHz. The first receiver chain 23 is a superheterodyne receiver chain and so it comprises a first mixer 41, the first mixer 41 being connected to a first bandpass filter 39 and a first intermediate frequency stage in the form of a second bandpass filter 43. The second band pass filter 43 in the first receiver chain 23 has a center frequency of 72 MHz. The first mixer 41 in the first receiver chain 23 is connected to the frequency synthesis circuit 29 and is arranged to receive the oscillator signal generated by the frequency synthesis circuit 29 having a frequency in the interval range of 941-. The frequency spacing between these oscillator signals corresponds to the channel spacing in AMPS (30 kHz). Channel selection in the first receiver chain 23 is performed by the first mixer 41 together with the second band-pass filter 43, because the first mixer 41 shifts the frequency of the channel to be received at a given time to 72MHz in a known manner. The frequency of the oscillator signal is received by the first mixer in the first receiver chain 23 at a given time to determine the AMPS channel to be selected. The first receiver chain 23 also comprises a second mixer 45 connected to the second band-pass filter 43 and arranged to receive the 72MHz first intermediate frequency signal from the second band-pass filter 43. The second mixer 45 in the first receiver chain 23 is further arranged to receive an oscillator signal having a frequency of 71.55MHz generated by a frequency synthesiser circuit (not shown in the figure), the second mixer 45 being arranged to generate a second intermediate frequency signal of 450kHz by downconverting the 72MHz first intermediate frequency signal. The first receiver chain also comprises a second intermediate frequency stage 47 connected to the second mixer 45 and arranged to receive a 450kHz second intermediate frequency signal. Following the second intermediate frequency stage 47 of the first receiver chain 23 is a detector unit 49.

The second receiver chain 25 is connected to the antenna 21 through a transmit/receive switch 51 and a band splitter 35. The second receiver chain 25 comprises an amplifier 53 connected to the transmit/receive switch 51. The band splitter 35, the transmit/receive switch 51 and the amplifier 53 in the second receiver chain 23 are arranged such that the second receiver chain 25 receives radio frequency signals via the antenna 21 having a frequency in the frequency range of 1930-. The second receiver chain 25 comprises a first mixer 55 which is connected to the amplifier and to a first intermediate frequency stage in the form of a first band pass filter 57. The first bandpass filter 57 in the second receiver chain 25 has a centre frequency of 188 MHz. The first mixer 55 in the second receiver chain 25 is also connected to the frequency synthesis circuit 29 and is arranged to receive the oscillator signal generated by the frequency synthesis circuit 29 having a frequency in the interval range 1742-1802 MHz. The frequency spacing between these oscillator signals corresponds to the channel spacing of PCS1900(200 kHz). Channel selection in the second receiver chain 25 is made by the first mixer 55 together with the first band-pass filter 57 in a corresponding manner to the first receiver chain 23, and which PCS1900 channel is selected is determined by the frequency of the oscillator received by the first mixer 55 at a given time. The second receiver chain 23 further comprises a second mixer 59 connected to the first band pass filter 57 and arranged to receive the first intermediate frequency signal at 188 MHz. The second mixer 59 in the second receiver chain 25 is further arranged to receive an oscillator signal having a frequency of 182MHz generated by a frequency synthesiser circuit (not shown in the figure), the second mixer 59 being arranged to generate a second intermediate frequency signal of 6MHz by downconverting the first intermediate frequency signal of 188 MHz. The second receiver chain 25 comprises a second intermediate frequency stage 61 connected to the second mixer 59 and arranged to receive the 6MHz second intermediate frequency signal. Following the second intermediate frequency stage 61 of the second receiver chain 25 is a detector unit 63.

The transmitter chain 27 is used for AMPS (824-849MHz) and PCS1900(1850-1910MHz) transmissions. The transmitter chain 27 is connected to the antenna 21 through the duplex filter 31 and the band splitter 35 when transmitting signals in AMPS, and is connected to the antenna 21 through the transmit/receive switch 51 and the band splitter 35 when transmitting signals in PCS 1900. The reason for this arrangement is of course: the wireless communication device simultaneously performs transmission and reception when communicating in AMPS, whereas in PCS1900 transmission and reception do not occur simultaneously. The transmitter chain 27 comprises a transmitter intermediate frequency modulator 65 arranged to generate a modulated transmitter intermediate frequency signal having a transmitter intermediate frequency of 117 MHz. The same transmitter intermediate frequency (117MHz) is used in AMPS and PCS 1900. The transmitter intermediate frequency modulator 65 is arranged to receive the first and second quadrature signals I and Q and to generate a modulated intermediate frequency signal at 117 MHz. The transmitter chain 27 comprises a mixer 67 connected to the transmitter intermediate frequency modulator 65 and arranged to receive a modulated transmitter intermediate frequency signal of 117 MHz. The mixer 67 in the transmitter chain 27 is also connected to the frequency synthesiser 29 and is arranged to receive an oscillator signal generated by the frequency synthesiser circuit having a frequency in a first interval range of 941-. The frequency spacing between oscillator signals in the first interval range corresponds to the channel spacing in AMPS, and the frequency spacing between oscillator signals in the second interval range corresponds to the channel spacing in PCS 1900. Channel selection in the transmitter chain 27 is performed by the mixer 67 by up-mixing the 117MHz modulated intermediate frequency signal to the desired radio frequency channel. The frequency of the oscillator signal received by the mixer in the transmitter chain 27 at a given time thus determines which channel is to be selected in a manner known per se. The transmitter chain 27 comprises an amplifier 69 connected to the mixer 67. The amplifier 69 in the transmitter chain 27 is thus arranged to receive and amplify signals having frequencies in the range 824-849MHz corresponding to the uplink range of AMPS and signals having frequencies in the range 1850-1900MHz corresponding to the uplink range of PCS1900, but not simultaneously. The transmitter chain 27 finally comprises a power amplifier adaptor 71 connected to the amplifier 69 in the transmitter chain 27 and arranged to receive the amplified signal from the amplifier 69. The power amplifier adapter 71 also includes a duplex filter 31 and a transmit/receive switch 51 and is arranged to perform a band splitting function that separates the AMPS range from the PCS1900 range.

The frequency synthesizing circuit 29 of the wireless communication device 20 is based on a fractional-N PLL circuit. Thus, the frequency synthesis circuit 29 includes a reference frequency divider 73 and a main frequency divider 75. The wireless communication device 20 also includes a crystal oscillator 77 that serves as a system clock. The crystal oscillator 77 is arranged to generate a clock signal of 13 MHz. The 13MHz clock signal is used for timing in the PCS1900, for example, for bit rate and burst rate control. The reference divider 73 is connected to a crystal oscillator 77 and is arranged to receive a clock signal of 13MHz as a reference frequency signal. The reference frequency divider 73 and the main frequency divider 75 are connected to the control unit 78 and are arranged to receive a first and a second control signal, respectively, generated by the control unit 78. The transmit intermediate frequency modulator 65 is also connected to the crystal oscillator 77 and is arranged to receive a clock signal of 13MHz, which is used by the transmit intermediate frequency modulator 65 in generating a transmit intermediate frequency signal of 117 MHz.

The frequency synthesizing circuit 29 further includes first and second voltage-controlled oscillators 79 and 81. The first voltage controlled oscillator 79 is connected to the first mixer 41 in the first receiver chain 23 and the mixer 67 in the transmitter chain 27. The first voltage controlled oscillator is arranged to generate an oscillator signal for use in channel selection in AMPS. The second voltage controlled oscillator 81 is connected to the first mixer 55 in the second receiver chain 25 and the mixer 67 in the transmitter chain 27. The second voltage controlled oscillator 81 is arranged to generate an oscillator signal for use in channel selection in the PCS 1900. Two voltage controlled oscillators 79 and 81 are also connected to the main frequency divider 75 via a combiner 83. The wireless communication device 20 shown in fig. 3, as described above, does not use AMPS and PCS1900 simultaneously, which means that the two voltage controlled oscillators 79 and 81 do not operate simultaneously. The reason why the frequency synthesizing circuit 29 includes two voltage-controlled oscillators 79 and 81 instead of only one oscillator is that: it is not possible to design an oscillator that can use an oscillator signal over a large frequency range as used herein. The frequency synthesizing circuit 29 comprises a loop filter 87 connected to the phase comparator 85 and arranged to receive the phase difference signal e from the phase comparator 85. The loop filter 87 is arranged to generate a third control signal c3 for controlling the two voltage controlled oscillators 79 and 81 connected to the loop filter and arranged to receive the third control signal c3, dependent on the phase difference signal e.

As will be seen from the discussion in connection with fig. 2, the frequency synthesizing circuit 29 in the wireless communication device 20 may be generated to have a frequency according to f_out＝[(N+F/Q)/R]Frequency f of 13MHz_outThe oscillator signal of (1). Here, as described above, N, F, Q, and R are integers determined by the first and second control signals c21 and c 22. In the following, in two tablesIt is shown how the integers N, F, Q, and R can be selected in uplink and downlink channel selection in AMPS and PCS 1900.

Unit: [ MHz ]]

TABLE 1AMPS	Comparator frequency 50kHz R260
							Channel number	FTX	FRX	fout	N	F	Q
991	824.04	869.04	941.04	18820	4	5
							992	824.07	869.07	941.07	18821	2	5
993	824.10	869.10	941.10	18822	0	5
							994	824.13	869.13	941.13	18822	3	5
995	824.16	869.16	941.16	18823	1	5
							996	824.19	869.19	941.19	18823	4	5
997	824.22	869.22	941.22	18824	2	5
							998	824.25	869.25	941.25	18825	0	5
999	824.28	869.28	941.28	18825	3	5
							1000	824.31	869.31	941.31	18826	1	5
1001	824.34	869.34	941.34	18826	4	5
							Etc. of	Etc. of	Etc. of	Etc. of	Etc. of	Etc. of	Etc. of

1023	825.00	870.00	942.00	18840	0	5
							1	825.03	870.03	942.03	18840	3	5
2	825.06	870.06	942.06	18841	1	5
							3	825.09	870.09	942.09	18841	4	5
4	825.12	870.12	942.12	18842	2	5
							5	825.15	870.15	942.15	18843	0	5
6	825.18	870.18	942.18	18843	3	5
							Etc. of	Etc. of	Etc. of	Etc. of	Etc. of	Etc. of	Etc. of
799	848.97	893.97	965.97	19319	2	5

Unit: [ MHz ]]

TABLE 2PCS1900	Comparator frequency 1MHz R13
									Channel number	FTX	FRX	fout(TX)	fout(RX)	N(TX)	N(RX)	F	Q
512	1850.2	1930.2	1733.2	1742.2	1733	1742	1	5
									513	1850.4	1930.4	1733.4	1742.4	1733	1742	2	5
514	1850.6	1930.6	1733.6	1742.6	1733	1742	3	5
									515	1850.8	1930.8	1733.8	1742.8	1733	1742	4	5
516	1851	1931	1734	1743	1734	1743	0	5
									517	1851.2	1931.2	1734.2	1743.2	1734	1743	1	5
518	1851.4	1931.4	1734.4	1743.4	1734	1743	2	5
									519	1851.6	1931.6	1734.6	1743.6	1734	1743	3	5
520	1851.8	1931.8	1734.8	1743.8	1734	1743	4	5
									521	1852	1932	1735	1744	1735	1744	0	5
Etc. of	Etc. of	Etc. of	Etc. of	Etc. of	Etc. of	Etc. of	Etc. of	Etc. of
									809	1909.6	1989.6	1792.6	1801.6	1792	1801	3	5
810	1909.8	1989.8	1792.8	1801.8	1792	1801	4	5

FTX denotes the center frequency of the channel at the time of transmission, and FRX denotes the center frequency of the channel at the time of reception. In the AMPS table, the integers N and F are given according to the following formula and the desired output frequency F_out(in Hz) are linked:

N＝int(f_out/(5*10⁴)) (7)

F＝fract(f_out/(5*10⁴)) (8)

where int (x) represents the integer part of the number x, and fract (x) represents the fractional part of the number x.

In the table for PCS, the integers N and F are given by the following formula with the desired output frequency F_out(in Hz) are linked:

N＝int(f_out/(10⁶)) (9)

F＝fract(f_out/(10⁶)) (10)

the invention is of course not limited to use in mobile phones but may also be used in other applications, such as wireless communication systems.

Fig. 4 shows a radiotelephone 100 including the wireless communication device 20 shown in fig. 3, along with an antenna 21. In fig. 4, it is shown how a radio telephone 100 using a radio communication device 20 communicates via a first base station 101 in AMPS or via a second base station in PCS 1900.

Claims (8)

1. The wireless communication device (20) includes:

at least one antenna (21);

wireless communication means (23, 25, 27) connected to an antenna (21), the means being arranged for communication in at least one frequency range having at least one associated channel spacing, the wireless communication means in turn comprising channel selection means arranged to use an oscillator signal of a predetermined frequency in channel selection; and

at least one system clock (77) arranged to generate at least one clock signal having a predetermined clock frequency for timing of the wireless communication device (20),

the clock frequency is not divisible by all channel spacings;

a wireless communication device (20) comprises a frequency synthesizing circuit (29) having at least one controllable oscillator (81, 79) in the form of a fractional-N PLL circuit for generating an oscillator signal having a predetermined frequency for channel selection, the fractional-N PLL circuit being connected to a system clock (77) and being arranged to receive the clock signal as a reference frequency signal.

2. A wireless communication device (20) according to claim 1, characterized in that the wireless communication means (23, 25, 27) comprise at least one receiver chain (23, 25) connected to the antenna (21) and arranged to receive wireless signals in at least one frequency range.

3. A wireless communication device (20) according to claim 2, characterized in that at least one receiver chain (23, 25) is a superheterodyne receiver chain comprising a first mixer (41, 55) and a first intermediate frequency stage (43, 57) connected to the first mixer, said first mixer being connected to the frequency synthesizing circuit (29) and being arranged to receive a predetermined number of oscillator signals for channel selection.

4. A wireless communication device (20) according to any of claims 1 to 3, characterized in that the wireless communication means (23, 25, 27) comprise at least one transmitter chain (27) connected to the antenna (27) and arranged to transmit wireless signals in at least one frequency range.

5. The wireless communication device (20) according to claim 4, wherein the at least one transmitter chain (27) comprises a transmitter intermediate frequency modulator (65) arranged to generate a modulated transmit intermediate frequency signal;

a transmitter chain (27) with a transmitter intermediate frequency modulator (65) comprises a mixer (67) connected to the transmitter intermediate frequency modulator and arranged to mix a transmitter intermediate frequency signal up to a channel in at least one frequency range, the mixer being connected to a frequency synthesizer circuit (29) and arranged to receive a predetermined number of oscillator signals for mixing.

6. A wireless communication device (20) according to claim 5, characterized in that the transmit intermediate frequency modulator (65) is connected to the system clock (77) and arranged to receive a clock signal used in generating the transmit intermediate frequency signal.

7. Radio telephone arranged for communication in at least one mobile telephone system, characterized in that the radio telephone comprises a radio communication device according to any of claims 1 to 6.

8. A radio telephone according to claim 7, characterized in that it is arranged for communication in at least AMPS and PCS 1900.