HK1142717B - Nitride nanowires and method of producing such - Google Patents

Description

nitride nanowire and method for manufacturing same

Technical Field

The present invention relates to a semiconductor device based on nitride semiconductor nanowires and a method for manufacturing the same by growth. The nitride semiconductor nanowire can be used as, for example, a diode, an LED, an LD, and a transistor. The invention relates in particular to a method of fabricating vertical GaN nanowires with limited lateral growth.

Background

The use of nitride semiconductors in semiconductor devices, and in particular in optoelectronic devices, has received considerable attention for a long time, not least due to the potential possibility of implementing components functioning in wavelength regions not accessible by conventional semiconductor materials. In 1990, two breakthroughs were made in nitride semiconductor growth: manufacturing a high-quality GaN film and realizing p-type GaN. After these, blue and green LEDs and laser diodes were commercialized, and AlN-based UV LEDs were started to be reported. Nitride-based semiconductors are also of interest for transistors and other electronic devices for high voltage and high temperature applications.

GaN films are typically grown by industrial-grade MOCVD techniques. To achieve acceptable film quality, in e.g. NH₃The growth is performed with a high precursor flow rate of TMG (trimethyl gallium), and thus at a high partial pressure. A commonly used measurement is called "V/III ratio", which relates to the molar flow of the precursor elements, e.g. NH₃And the molar ratio of TMG. The V/III ratio for GaN film growth is in the range of 1000-10000.

However, top-level GaN films today still have very high defect densities. In this context, 1-dimensional structures, i.e. nitride based nanowires, have attracted a lot of attention from researchers. For nanowire growth, several methods have been reported, such as VLS, template-limited growth, and oxidation-assisted growth.

Selective area growth of GaN has been extensively studied since 1990 in order to reduce the mismatch density in GaN films. From the dot-patterned GaN openings, Akasaka et al demonstrated growth of GaN bodies with a diameter of 5 μm [1 ]. Recently, Hersee et al reported that GaN wire arrays with dimensions of 221nm were fabricated using selective area growth [2 ]. It describes that pulsed growth must be used to grow GaN nanowires to limit this lateral growth. Pulsed growth is also known as migration enhanced growth. The method can be described as a two-step method comprising an initial nanowire growth step, referred to as a selective growth step, wherein two precursor gases are provided. This initial growth step is followed by a second step of pulsed growth, wherein at this point a precursor gas is provided.

Disclosure of Invention

The reported achievements illustrate the great potential of this technology, but improvements are needed to provide methods that can produce epitaxial vertical-standing GaN nanowires without crystalline defects such as stacking defects and dislocations, and that provide methods that are well suited to scale-up to industrial production.

It is an object of the present invention to provide a method and a semiconductor device which overcome the drawbacks of the prior art. This is achieved by the method as defined in claim 1 and by the semiconductor device as defined in claim 15.

The nitride-based semiconductor nanowire according to the present invention has the same crystal structure over the entire length thereof, i.e., the nanowire does not exhibit stacking defects near the base. Preferably, the crystal structure is hexagonal. Nanowires having the same crystal structure over their entire length can be manufactured by the method according to the invention described below.

A semiconductor device according to the present invention includes nitride semiconductor nanowires each having the same crystal structure over the entire length of the nanowire. A majority of the plurality of nanowires should have only one crystal structure. Even more preferably, at least 90% of the nanowires of the semiconductor device all have the same crystal structure. Even more preferably, 99% of the nanowires of the semiconductor device all have the same crystal structure. Semiconductor devices, such as LED devices, having a plurality of nanowires can be manufactured by the method according to the invention.

The method of growing nitride-based semiconductor nanowires according to the present invention utilizes a CVD-based selective area growth technique. A nitrogen source and a metal-organic source are present during the nanowire growth step, and at least the nitrogen source has a continuous flow rate during the nanowire growth step. The method of the present invention utilizes a V/III ratio that is significantly lower than the V/III ratio typically associated with nitride-based semiconductor growth.

An embodiment of the method of the invention comprises a planar growth phase following the nanowire growth phase described above. The planar growth phase utilizes a V/III ratio that is significantly higher than the V/III ratio of the nanowire growth phase. The planar growth phase causes the previously grown nanowire to begin lateral growth so that the nanowire is at least partially enclosed by the new layer. The planar growth can be repeated using different material compositions, doping, etc., resulting in a shell-like structure. According to one embodiment, the nanowire incorporating one or more shell layers forms a pn-junction of the LED. Likewise, other active semiconductor electronic and optoelectronic devices, such as transistors, can be fabricated in the same manner.

One advantage provided by the method of the present invention is that the nitride semiconductor nanowires do not have crystalline defects, such as dislocations and stacking defects, which may grow. Accordingly, a nitride semiconductor device including a large number of nanowires, which has a very low amount of defective nanowires, can be manufactured.

Another advantage of the method according to the invention is that the overall growth rate of the nanowires is significantly higher than in prior art methods of growing nitride nanowires. The growth rate has been demonstrated to be 200 nm/min.

The process according to the invention, with a low V/III ratio and low source flow, has a lower material consumption than comparable prior processes. In addition, the sustained V/III ratio makes it easier to optimize the growth conditions compared to the pulsed growth method.

The method according to the invention is also advantageous in that the structure comprises more than two elements, for example a ternary composition, such as InGaN. The use of InGaN in the nanowires would be advantageous because the stress on the shell layer can be reduced. However, InGaN is a thermally unstable material, requiring NH₃Flow to prevent In-N bond separation. Thus, by interrupting NH₃The prior art methods of streaming are not suitable for fabricating InGaN nanowires. In the process of the invention, a continuous flow of nitrogen source, for example NH, is used₃These effects are eliminated or at least reduced.

The method according to the invention is based on the MOCVD technique. MOCVD is used industrially and the process is very suitable for industrial-scale production.

Embodiments of the invention are defined in the dependent claims. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings and the claims.

Drawings

Preferred embodiments of the present invention will now be described with reference to the accompanying drawings, in which:

figure 1 schematically illustrates a nanowire according to the present invention;

fig. 2a schematically illustrates a method according to the invention, and fig. 2b is a flow chart of a method according to the invention;

3a-b are SEM images of nanowire structures according to the present invention;

4a-b schematically illustrate embodiments of nanostructured LEDs comprised in nanostructured LED devices according to the present invention;

5a-c schematically illustrate embodiments of nanostructured LED devices according to the present invention;

figure 6 schematically illustrates a nanowire growth apparatus according to the present invention.

FIGS. 7a-b are SEM-images illustrating the results of growth conditions in which nanowires are not provided;

figures 8a-b are SEM-images illustrating the results of growth conditions, wherein the formation of nanowires is initiated;

FIGS. 9a-b are SEM-images illustrating the results of providing growth conditions for nanowires;

10a-c are SEM-images illustrating the results of providing growth conditions for nanowires;

fig. 11a-c are SEM-images illustrating the effect of source doping.

Detailed Description

The semiconductor device and the method of manufacturing the same according to the present invention include at least one nitride semiconductor nanowire, such as a GaN nanowire.

Nitride semiconductor nanowires 110, schematically illustrated in fig. 1, are defined herein as substantially columnar structures having a diameter of less than 500nm and a length of up to several μm. The nanowires 110 are epitaxially connected at their bases to a substrate 105, and the substrate 105 may include an epitaxial layer, such as a GaN layer, next to the nanowires 110. The nanowires 105 are formed of, for example, SiN_xProtrudes through the opening in the growth mask 111. A semiconductor device according to the present invention generally includes a plurality of nanowires 110. As shown in fig. 1, the linerThe surface of the base 105 may exhibit some roughness 112, which is exaggerated in this figure for illustrative purposes only. In the following, the term nanowire should be understood as referring to the structure without being limited to the surface roughness, i.e. the nanowire starts in the first atomic layer on the substrate 110, or is referred to as the first "free" layer. However, this first layer is typically located within the opening of the growth mask 115. The length of the nanowire is denoted L.

Nitride nanowires fabricated by the prior art typically include a number of defects. The aforementioned pulsed selective growth represents a significant advance, but this approach can cause stacking defects near the base of the nanowire. Nanowires typically made in this way have a change from cubic to hexagonal crystal structure near the base. A semiconductor device comprising a plurality of such nanowires will have most or all of the nanowires exhibiting such a defect. Stacking faults have an effect on the physical properties of the nanowire, as regards optical and electrical properties. In applications such as LEDs, the relatively small distortion caused by stacking faults near the base also hampers their performance because the stacking faults increase the resistance. Since this area is very small, the increased resistance can significantly affect the performance of the LED.

The nitride semiconductor nanowire according to the present invention has the same crystal structure over the entire length thereof, i.e., does not exhibit a stacking defect near the base. Preferably, the crystal structure is hexagonal. Nanowires having the same crystal structure throughout their length can be produced using the method according to the invention described below.

The semiconductor device according to the present invention comprises nanowires 105 each having the same crystal structure over its (the nanowire's) entire length. A majority of the plurality of nanowires should have only one crystal structure. Even more preferably, at least 90% of the nanowires of the semiconductor device each have the same crystal structure. Even more preferably, 99% of the nanowires of the semiconductor device each have the same crystal structure. Semiconductor devices, such as LED devices, having a plurality of nanowires can be fabricated using the method according to the present invention.

The method of growing nitride semiconductor nanowires according to the present invention utilizes a CVD-based selective area growth technique. A nitrogen source and a metal-organic source are present during the nanowire growth step, and at least the flow rate of the nitrogen source is continuous during the nanowire growth step. This V/III ratio utilized in the method of the present invention is significantly lower than the V/III ratio typically associated with nitride-based semiconductor growth.

Thus, the method according to the present invention can be directly applied to a Metal Organic Chemical Vapor Deposition (MOCVD) process and apparatus. It will be apparent to those skilled in the art that the method is also applicable, with modification, to other CVD and mixed vapor phase epitaxy (HVPE) -based processes. The method is schematically illustrated in fig. 2a, and in the flow chart of fig. 2b, and comprises the steps of:

a) a growth mask 115 is provided on the substrate 110. The substrate is, for example, GaN and the growth mask is a dielectric, for example SiN_xOr SiO_x。

b) An opening 113 is made in the growth mask. The openings are preferably well controlled both with respect to their diameter and their relative position. Several techniques known in the art may be used for this step, including but not limited to Electron Beam Lithography (EBL), nanoimprint lithography, photolithography, and Reactive Ion Etching (RIE) or wet chemical etching methods. Preferably, the openings are approximately 100nm in diameter and 0.5-5 μm apart. The openings define the position and diameter of the nanowires 105 to be fabricated.

c) Nanowires are grown by a CVD-based process in which the precursor source flow is continuous. The precursor source flow rate is adjusted to achieve low supersaturation in the growth zone. The V/III ratio should be in the range of 1-100, preferably in the range of 1-50, and more preferably in the range of 5-50. It should be noted that this V/III ratio is significantly lower than the ratio used for film growth.

Nanowires fabricated according to the method of the invention are illustrated in the SEM images of fig. 3 a-b. On the starting substrateDeposition of SiN by PECVD_xLayer (30nm thick). In a subsequent step, an array of dot-patterned GaN openings (about 100nm in diameter) was made by electron beam lithography, EBL and reactive ion etching, RIE. The spacing between the openings ranges from 0.5-3.2 μm, and a given growth mask defines both the diameter and the position of the nanowires. The treated sample was then placed into a horizontal MOCVD chamber to grow GaN nanowires. Figure 3a further illustrates that nanowires with pyramidal ends can be formed, which is advantageous in certain applications.

The method may comprise different steps of increasing the growth conditions, illustrated as a pre-treatment step c'), e.g. an annealing prior to the nanowire growth step c). The pre-processing step may comprise a plurality of sub-steps. It should be noted that although the pretreatment, e.g., annealing, may use one or more precursors, the pretreatment step according to the present invention does not result in the growth of nanowires. This change in the V/III ratio can also be observed during the nanowire growth step c). However, the flow of the precursor material should not be interrupted during the nanowire growth step.

Nanowires according to the present invention can be used in a variety of different applications. Particularly important applications include electronic, optical and optoelectronic devices, including but not limited to: diodes, Light Emitting Diodes (LEDs), transistors, photonic crystals, and detectors. The nanowires may also be used as structured building blocks (structured building blocks), for example to form continuous bonding layers of GaN, which may have a very low defect density. How to form the bonding layer from nanowires is described in application US 10/613071.

One high commercial value application is LED devices, which will be taken as a non-limiting example. As will be appreciated by those skilled in the art, transistors and other electronic devices may also be fabricated in the same manner.

An LED device comprising a semiconductor nanowire according to the present invention is schematically illustrated in fig. 4a-b and comprises a substrate 105, wherein the nanowire 110 is epitaxially grown from the substrate 105. A portion of the nanowire 110 is enclosed by a volume element 115. The volume element 115 is preferably epitaxially connected to the nanowire 110. The pn-junction required for diode functionality is formed in the volume element 115 or alternatively in the nanowire 110. A top contact is provided on the volume element 115, for example on the top or on the surrounding outer surface of the enclosing structure. The nanostructured LED100 may be contacted at the other end, for example, via the substrate, by a common bottom contact formed by a dedicated contact layer near the substrate or by a surrounding contact at the lower end of the nanowire 110. The nanowires 110 typically have a diameter on the order of 50nm to 500nm, and the volume element diameter is on the order of 500nm to 10 μm. The volume elements 115 or spheres can have different shapes and the combined design of the volume elements and nanowires to give different positions and shapes of the active region, given the recombination conditions required for light emission. The volume element 115 may further provide a high degree of doping and charge carriers are injected into the nanowire.

Fig. 4a illustrates a design in which the volume element 115 comprises a multi-layered shell-like structure 116, 117. The volume element 15 may also be partially enclosed by a contact layer 118. The doped layer 117 provides a p or n region and the well layer 116 includes an active region 120 in operation. Alternatively, the well may be made up of multiple sublayers. The structure may include other layers (not shown) for enhancing doping characteristics, improving contacts, etc. These structures are also referred to as core-shell structures.

Another design is illustrated in fig. 4b, where the nanowire 110 is surrounded by an overgrowth cone constituting a volume element 115. Similar to the previous, the overgrowth cone may include multiple layers 166, 117, 118, providing the doping and quantum wells required for LED functionality, resulting in the formation of active region 120.

According to an embodiment of the method of the invention, the further growth step comprises providing an overgrowth, or volume element, on the nanowire. As described with reference to the flow chart of fig. 2b, the method comprises two phases. The first phase may be considered as a nanowire growth phase comprising steps a-c), wherein nanowire growth conditions are provided, i.e. a low V/III ratio is provided. In the second stage, the nanowire is overgrown by the volume element 115, which typically comprises a plurality of different layers, in a CVD-based process similar to the first stage growth process and preferably in the same cavity, but with the growth parameters adjusted to planar growth, i.e. with a V/III ratio higher than in nanowire growth, typically in the order of 1000. The method according to this embodiment can be seen as a nanowire growth phase followed by a planar growth phase, or a lateral growth phase. This nanowire growth phase forms a nanowire with a surface that is nearly ideal for planar growth, referred to as the m-plane {1-100} since the sidewalls of the nanowire will be non-polar. Such surfaces are very difficult to manufacture by conventional methods. In a planar growth phase or lateral growth phase following the nanowire growth phase, a shell layer is grown in steps d), e), f) … … using the ideal surface, forming part of the LED device. Other devices, such as diodes and transistors, may be fabricated in the same manner, as will be appreciated by those skilled in the art.

The method according to the invention can also be used for structures comprising more than two elements, for example ternary compositions, such as InGaN. As shown In fig. 5a, stress is a serious problem for fabricating high In content InGaN/GaN core-shell structures, with the GaN nanowires 510 surrounded by InGaN shell layers 515 In fig. 5 a. As shown in fig. 5b, also using InGaN in the nanowire 511 will reduce the stress in the InGaN shell layer. However, InGaN is a thermally unstable material and requires NH₃Flow to prevent In-N bond separation. Thus, interrupted NH is utilized₃The prior art methods of streaming may not be suitable for fabricating InGaN nanowires. NH at InGaN growth temperature₃In the interruption step, it means that In — N bonds are separated and In can be released from the crystal. The invention provides for the use of continuous nanowire growth to support the growth of higher In content InGaN nanowires.

A conventional MOCVD or MOVPE apparatus is not ideal for performing the method according to this embodiment comprising a nanowire growth phase followed immediately by a planar growth phase. Due to the technical limitations of the gas supply system, the same gas supply system cannot provide the nanowire growth stage and the planar growth stage, respectively, with the required accuracyBoth low and high V/III ratios with respect to the segment. The growth apparatus according to the present invention, schematically illustrated in fig. 6, includes a growth chamber 610 in which a sample 615 is placed. The III-supply system 622 includes a III-source 620 and a Mass Flow Controller (MFC). The V-supply system includes a V-source 630, the V-source 630 being connected to a low source flow V-supply line 634 that includes a low flow MFC 633 and a separate high source flow V-supply line 632 that includes a high flow MFC 631. The low flow MFC 633 is adapted to handle for example NH in connection with the nanowire growth phase₃And the high flow MFC631 is adapted to handle the high flow rates associated with the planar growth stage. By switching between two separate V-supply lines and then proceeding from the nanowire growth phase to the planar growth phase, rapid changes can be made in two different phases with the required accuracy of the flow rate. If the required flow rate is not available from two MFCs, the arrangement can of course be provided with more separate supply lines.

The application of the process of the invention is illustrated by the following examples, which should be regarded as non-limiting examples.

Fig. 2a-c illustrate the fabrication sequence of GaN nanowires by selective growth of regions. GaN epitaxial films on sapphire, SiC, or Si and even self-supporting GaN are used as starting substrates on which SiN is deposited by PECVD_xLayer (30nm thick) (a). Subsequently, an array of dot-patterned GaN openings (about 100nm in diameter) (b) was fabricated by EBL and RIE. The distance between the openings is within the range of 0.5-3.2 μm. Thereafter, the treated sample was placed in a domestic horizontal MOCVD chamber to grow GaN nanowires (c). The growth process includes an initial phase in which the temperature is 75sccm of high NH within 5 minutes₃The temperature is ramped up to 900-1200 ℃ in the growth interval under the flow speed. The substrate was annealed at the growth temperature for 1 minute. In the subsequent nanowire growth phase, the NH₃The flow rate is reduced to 3.0-0.2 sccm and TMG (trimethyl gallium) is introduced into the chamber to start growth. A low TMG flow rate of between 0.12 and 1.2. mu. mol/min was used in this operation.

According to the invention, it was verified in experiments that this NH₃The flow rate being controlled from said openingIs a key factor in the growth pattern of (1). FIGS. 7a-b show NH₃SEM image of the growth of this sample at a flow rate of 3.0 sccm. From the top view of fig. 7a, it can be seen that the selective growth from the openings is the same as reported. One point to be elaborated here is that the lateral dimension after growth is greater than 1.0 μm, which is much larger than the opening size of about 100 nm. Thus, GaN grows substantially laterally after it grows out of the opening. Fig. 7b shows an SEM image taken by tilting the sample at 35 deg., which clearly shows that what is obtained is a cone, rather than a line. The cone is defined by six equivalent (1101) faces. The dangling bond density of the (1101) plane is 16.0/nm²Higher dangling bond density (12.1/nm) than (1100) plane²) And dangling bond density of (0001) plane (11.4/nm)²)[3]. From this point of view, when GaN grows out of the opening, the (1100) and (0001) planes are expected to appear. However, fig. 2 shows the opposite case. Thus, the possible explanation is that the (1101) plane has N-polarity when NH₃At high flow rates, it ensures stability. Based on this, NH is used for growing GaN line divided into bulk (processed) surface by (1100) surface₃The flow rate of 3sccm is still actually high. FIGS. 8a-b show a cross-section at NH₃SEM characteristics for sample growth at a flow rate of 1.0 sccm. The top view image of fig. 8a is similar to that of fig. 7 a. But the 35 ° oblique image of fig. 8b differs, i.e. a vertical facet (facet) of the (1100) face starts to appear below the cone cap. This predicts and explains that the N-polarized (1101) plane does not initially define the growth form of the pyramid. Nevertheless, the lateral dimension is still much greater than that of the opening, which is the same as that shown in fig. 7.

FIGS. 9a-b show the reaction of NH₃The flow rate of (c) was further reduced to a growth result of 0.5 sccm. Although they are still larger than the opening size of about 100nm, the top view (a) and the 35 ° oblique image (b) illustrate the reduction in size in the lateral direction. The oblique image of fig. 9b also shows the vertical facets. With NH₃The flow rate of (a) was reduced to 0.2sccm and as shown in FIGS. 10a-c, the synthesis of real GaN nanowires started, wherein (a) is a top view; (b) and (c) is a 45 ° oblique view. Although some crystals greater than 100nm are present, most of the openings develop to have and open100nm diameter wire with the same port size. Thus, when NH₃The lateral growth can also be well controlled at a flow rate of 0.2 sccm. As for vapor phase growth, the degree of supersaturation determines the predominant growth morphology, namely: low supersaturation is required for nanowire growth, while medium supersaturation supports grow crystalline. Formation of powder by gas phase nucleation at high supersaturation [4-5 ]]. According to this, NH is reasonably converted₃The flow rate of (2) is reduced to 0.2sccm, which effectively reduces the supersaturation, which limits the lateral growth and allows growth to occur only in the axial direction. Here, TMG and NH were maintained throughout the growth process₃Simultaneous and continuous flow into the chamber to perform full growth. However, work reported in the prior art appears to indicate that a pulsed growth mode is necessary to obtain nanowire growth. Based on the results presented herein, it is clear that nanowire growth can be achieved by a sustained source flow rate. To fabricate GaN nanowires, NH should be adjusted₃Flow rate in order to achieve low supersaturation or alternatively described as achieving migration enhanced growth.

Cp has been demonstrated₂Mg enhances vertical sidewall surface formation [6]. In FIGS. 11a-c, referring to Table 1, there are shown, for example, Cp₂The Mg dopant source can potentially stabilize the nanowire growth conditions through this effect. Also, it further shows that by increasing supersaturation/NH₃Flow rate, cone growth can be re-established. This can be used to provide lateral growth of the nanowires in a lateral growth phase.

TABLE 1

Growth of nr	NH3Flow rate [ sccm ]]	Cp2Mg flow rate [ sccm ]]	Remarks for note
				a	1	-	Is not doped
b	1	70	Good line
				c	10	70	Increase of NH3Flow velocity to reestablish pyramidal growth

Nanowires can be fabricated using the method of the present invention in a wide range of devices, such as diodes, LEDs, transistors, in particular field effect transistors, and the like. Nitride-based electronic devices are particularly important in applications at high voltages and high temperatures.

In general, by reducing NH₃Flow rate, GaN nanowires can be fabricated by MOCVD, with selective region growth from GaN openings. The key point for growing GaN nanowires is to control the supersaturation. This has previously only been achieved by using pulse growth techniques [2]]. In the presented results, it is shown that pulse growth is not a necessary method, but that NH is sufficiently reduced₃The flow rate can also produce nanowires. The work follows for growing nitride heterojunctions in axial and radial directions using this method.

GaN, NH have been utilized as non-limiting examples₃And TMG describe the inventionThe method is described. It will be clear to the skilled person that the principles of the present method can be applied to the growth of other semiconductor nitride based nanowires, for example comprising indium or aluminium, such as AlInGaN. III-NAs, and III-NP. NH (NH)₃Is a convenient and readily available nitrogen source, but other sources known as N (C) tert-butylamine may be utilized₄H₉)H₂(Tert butylamine N(C₄H₉)H₂)1, 1-Dimethylhydrazine (CH)₃)₂NNH₂(1，1-Dimethylhydrazine(CH₃)₂NNH₂) And tert-butylhydrazine (CH)₃)₃CNHNH₂(Tert butylhydrazine(CH₃)₃CNHNH₂). Depending on the III-V semiconductor chosen, different sources are available. Different sources will result in different suitable flow rate values in order to achieve low supersaturation and therefore require a corresponding adjustment of the V/III ratio. Such modifications will occur to those skilled in the art in light of the foregoing teachings.

Reference documents:

T.Akasaka，Y.Kobayashi，S.Ando，and N.Kobayashi，Appl.Phys.Lett.71(1997)2196.

S.D.Hersee，X.Sun，and X.Wang，Nano Lett.6(2006)1808.

K.Hiramatsu，K.Nishiyama，A.Motogaito，H.Miyake，Y.Iyecchika，and T.Maeda，Phys.Stat.Sol.(a)176(1999)535.

G.W.Sears，Acta Metallurgica，3(1955)367.

Y.Xia，P.Yang，Y.Sun，Y.Wu，B.Mayers，B.Gates，Y.Yin，F.Kim and H.Yan，Adv.Mater.15(2003)353.

B.Beaumont，S.Haffouz，and P.Gibart，Appl.Phys.Letters 72(1997)922.

Claims (26)

1. A method of growing nitride-based semiconductor nanowires using a CVD-based selective area growth technique, comprising:

providing a growth mask on a substrate;

forming an opening in the growth mask;

growing the nanowires in a nanowire growth step by a CVD-based selective area growth technique, wherein a nitrogen source and a metal-organic source are present in the nanowire growth step, and wherein a nitrogen source flow rate and a metal-organic source flow rate are continuous in the nanowire growth step; and

performing a planar growth step after the nanowire growth step, the planar growth step comprising at least one growth step resulting in a shell layer being formed on the nanowire, wherein the V/III-ratio during the planar growth step is higher than the V/III-ratio during the nanowire growth step.

2. The nanowire growth method according to claim 1, wherein the V/III-ratio comprises a ratio of a nitrogen source flow rate to a metal-organic source flow rate, and the V/III-ratio is in a range of 1-100.

3. A nanowire growth method according to claim 2, wherein the V/III-ratio is in the range of 1-50.

4. A nanowire growth method according to claim 3, wherein the V/III-ratio is in the range of 5-50.

5. The nanowire growth method according to any one of claims 1 to 4, wherein the V/III-ratio is constant in the nanowire growth step.

6. The nanowire growth method according to any one of claims 1 to 4, wherein the nitride-based semiconductor is GaN, the nitrogen source is ammonia, and the metal-organic source is trimethyl gallium.

7. The nanowire growth method of claim 1, further comprising a pretreatment step (c'), wherein at least one of the nitrogen precursor source flow and the metal-organic precursor source flow is functional and nanowire growth does not occur during the pretreatment step.

8. A nanowire growth method according to claim 7, wherein the pre-treatment step comprises an annealing step.

9. The nanowire growth method of claim 1, wherein the planar growth step results in the creation of a plurality of layers.

10. The nanowire growth method according to claim 9, wherein the shell layer is InGaN.

11. The nanowire growth method according to claim 9, wherein the plurality of layers comprises a well layer (116) and a doped layer (117).

12. The nanowire growth method of claim 11, wherein the well layer comprises a plurality of sub-layers.

13. The nanowire growth method according to any of claims 9-12, wherein the plurality of layers form a volume element (115) and the method further comprises the step of partially surrounding the volume element (115) by a contact layer (118).

14. The nanowire growth method according to claim 13, wherein the volume element (115) is a pyramid.

15. The nanowire growth method according to claim 1, wherein the V/III-ratio of the planar growth step is at least 10 times higher than the V/III-ratio of the nanowire growth step.

16. The nanowire growth method of claim 1, wherein a dopant source is introduced to stabilize nanowire growth conditions.

17. A semiconductor device comprising a plurality of nanowires (110) of a nitride semiconductor, the nanowires (110) being epitaxially connected to a substrate (105) and upstanding from the substrate (105), characterized in that

Each nanowire has the same crystal structure throughout its respective length in at least a majority of the nanowires;

the nanowire is provided with a volume element (115) comprising at least one shell layer (116);

the semiconductor device is an LED;

the plurality of nanowires are individual nanostructured LEDs; and

the pn-junctions are provided by the nanowires (105) in combination with their respective volume elements (115) such that the nanowires are doped with one of n or p type and the volume elements are doped with the other of p or n type.

18. The semiconductor device of claim 17, wherein at least 90% of the nanowires have the same crystal structure throughout their respective lengths.

19. The semiconductor device of claim 18, wherein at least 99% of the nanowires have the same crystal structure throughout their respective lengths.

20. The semiconductor device of claim 17 wherein the at least one shell layer is InGaN.

21. The semiconductor device of claim 17 wherein the volume element (115) comprises a plurality of layers.

22. The semiconductor device of claim 21, wherein the plurality of layers comprises a well layer (116) and a doped layer (117).

23. The semiconductor device of claim 22 wherein the well layer comprises a plurality of sub-layers.

24. A semiconductor device according to claim 17, wherein the volume element (115) is partially surrounded by a contact layer (118).

25. The semiconductor device of claim 17, wherein the volume element (115) is a cone.

26. The semiconductor device of claim 17, wherein the nanowire comprises a GaN nanowire.