HK1144496B - Current balancing circuit and method - Google Patents

Description

Current balancing circuit and method

Technical Field

The present invention relates generally to power converters, and more particularly to multiphase power converters.

Background

Power converters are used in a variety of electronic products, including automotive, aircraft manufacturing, telecommunications, and consumer electronics. Power converters, such as direct current to direct current ("DC-DC") converters, have been widely used in portable electronic products, such as laptop computers, personal digital assistants, pagers, portable telephones, and the like, that are typically powered by batteries. DC-DC converters are capable of carrying multiple voltages from a single voltage without relying on the load current drawn from the converter, nor on any variation in the power supply that powers the converter. One type of DC-DC converter used in portable electronic applications is a buck converter. This converter, also referred to as a switched mode power supply, is capable of switching an input voltage from one potential to a lower potential. The buck converter is typically controlled by a controller that can be configured as a multi-phase controller having multiple output current channels that switch at different times. The output currents flowing in the output current paths are summed and delivered to the load. The advantage of this configuration is that each channel conducts a portion of the total load current. For example, in a 4-phase buck converter, each channel conducts 25% of the output current. This reduces the power consumption per output. A disadvantage of multi-phase buck controllers is that when the currents are unbalanced, one of the current paths will conduct more current than the other current path, which can lead to thermal failure. Another disadvantage is that the dynamic load coupled to the controller may have the same repetition rate as one of the outputs of the multi-phase buck converter. In this case, the current in the channel becomes unbalanced, causing the converter to experience thermal failure.

It would therefore be advantageous to have a multi-phase controller circuit and method of operating the multi-phase controller circuit that maintains a balanced current at its output. Furthermore, it is desirable that the multi-phase controller circuit be inexpensive and time consuming to manufacture.

Drawings

The present invention will be better understood from a reading of the following detailed description taken in conjunction with the drawings in which like reference characters designate like elements, and in which:

FIG. 1 is a schematic diagram of a multi-phase controller according to an embodiment of the present invention;

FIG. 2 is a timing diagram of a multi-phase controller according to an embodiment of the invention; and

fig. 3 is another timing diagram of a multi-phase controller according to an embodiment of the invention.

Detailed Description

In general, the present invention provides a multiphase power converter and a method for balancing currents in the multiphase power converter. In accordance with an embodiment of the present invention, current balancing is accomplished by actively rearranging or swapping the output signals from the oscillators according to the phase output currents. By exchanging oscillator signals, current sharing can be maintained during dynamic loading without affecting the overall duty cycle delivered to the output. Preferably, the oscillator signals are exchanged when they have substantially the same value, i.e. at the ramp crossing of oscillator signals having a triangular waveform. Switching at the ramp crossing point reduces the effect on the oscillator signal and on the modulation of the output signal.

Fig. 1 is a block diagram of a multiphase power converter 10 fabricated on a semiconductor substrate in accordance with an embodiment of the present invention. FIG. 1 shows a circuit coupled to oscillator circuit 14, error amplifier 100, and output driver circuit 18₁...18_nA pulse width modulator ("PWM") circuit 12. In accordance with an embodiment of the present invention, the PWM circuit 12 includes a comparator 50 coupled to₁...50_nComparator circuits 54 and 56, and selector switches 58 and 60 of switch control circuit 68. The selector switch 58 is also referred to as an analog signal Multiplexer (MUX), and includes a switch 58₁...58_n. Similarly, selector switch 60, also referred to as an analog signal MUX, includes switch 60₁...60_n. Comparator 50₁...50_nEach having an inverting input, a non-inverting input and an output, and comparator circuits 54 and 56 each include a set of comparators that compare each oscillator signal with all other oscillator signals. The PWM circuit 12 further includes an oscillator input 34₁...34_nError signal input 38, current sense input 40₁...40_nAnd a PWM output 44₁...44_n. It should be noted that the number of oscillator inputs, PWM outputs, switch control inputs and error signal inputs is not a limitation of the present invention, and reference character n, which is appended to reference characters 18, 34, 40, 50, is a variable representing an integer.

Comparator 50₁Through switch 58 of selector switch 58₁Coupled to the input 34 of the PWM circuit 12_nAnd an input 54 of a comparator circuit 54₁. Comparator 50₁Also through switch 58_nCoupled to the input 34 of the PWM circuit 12₁By means of a switch 58 of a selector switch 58_nAnd a switch 60 through the selector switch 60₁Is coupled to a comparator 50_nIs input in the opposite phase. Except for coupling to comparator 50₁Is input to the inverting input of comparator 50_nAlso through switch 60 of selector switch 60_nAn input 54 coupled to a comparator circuit 54₁By means of a switch 60 of the selector switch 60₁An input 54 coupled to a comparator circuit 54_i. It should be noted that reference character i, which is appended to reference character 54, is a variable that represents an integer. Comparator 50₁...50_nIs connected to the input 38 of the PWM circuit 12.

The switch control circuit 68 has an input 66 connected to the output of the comparator circuit 54, connected to the switch 58₁Output 70 of₁Connected to the switch 58_nOutput 70 of₂A switch 60 connected to the selector circuit 60₁Output 70 of₃And a switch 60 connected to the selector switch 60_nOutput 70 of_m. The number of outputs of the switch control circuit 68 is not a limitation of the present invention, and therefore reference character m, which is appended to reference character 70, is a variable representing an integer. An output of comparator circuit 56 is connected to an input 67 of a switch control circuit 68.

Output driver circuit 18₁Including an N-channel field effect transistor 80₁N-channel field effect transistor 80₁Having an output 44 connected to PWM12₁Coupled to receive an operating potential V_ccDrain of source, passed diode 82₁Coupled to receive an operating potential V_ssAnd by the inductor 84₁And a resistor 85₁A source coupled to an output node 96. It should be noted that the gate of the field effect transistor and the base of the bipolar junction transistor are also referred to as control electrodes, and the source and drain of the field effect transistor and the collector and emitter of the bipolar junction transistor are also referred to as current carrying or current conducting electrodes. Output driver 18₁Further includes a current sensing circuit 86₁Current sensing circuit 86₁With coupling at resistor 85₁Two terminal inputs and a current sense input 40 connected to the PWM circuit 12_nTo output of (c). Electric currentSensing circuit 86₁And a resistor 85₁In combination, to sense flow through the sensor 84₁And transmits a current sense signal to the comparator circuit 56.

Output driver circuit 18_nIncluding an N-channel field effect transistor 80_nN-channel field effect transistor 80_nHaving an output 44 connected to PWM12_nCoupled to receive an operating potential V_ccIs passed through diode 82_nCoupled to receive an operating potential V_ssAnd by the inductor 84_nAnd a resistor 85_nA source coupled to an output node 96. Output driver 18_nFurther includes a current sensing circuit 86_nCurrent sensing circuit 86_nWith coupling at resistor 85_nTwo terminal inputs and a current sense input 40 connected to the PWM circuit 12₁To output of (c). Current sensing circuit 86_nAnd a resistor 85_nIn combination, to sense flow through the sensor 84_nAnd transmits a current sense signal to the comparator circuit 56.

Multiphase power converter 10 further includes an error amplifier 100 having an output 102 connected to error input 38. In accordance with an embodiment of the present invention, the error amplifier 100 includes an operational amplifier 104 connected in a negative feedback configuration, wherein an impedance 106 is coupled between the output of the operational amplifier 104 and its inverting input, and an impedance 108 is connected to the inverting input of the operational amplifier 104. By way of example, impedance 106 includes a capacitor 110 coupled in parallel with a series connected resistor 112 and capacitor 114, and impedance 108 includes a resistor. The non-inverting input of the operational amplifier 104 is coupled to receive a reference potential V_REF1. It should be understood that the feedback configuration of the error amplifier is not a limitation of the present invention and may be implemented using other feedback configurations known to those skilled in the art.

Load 98 at output node 96 and e.g. V_SSIs coupled between the sources of operating potential. An output capacitor 100 is connected in parallel with the load 98. The output node 96 is connected in a feedback configuration to an impedance 108.

FIG. 2 is a diagram showing a signal OSC from oscillator 14₁And OSC_nRespectively in the comparator 50₁And 50_nIs an input signal OSC of an inverting input_S1And OSC_SnRespectively at the output 44₁And 44_nPulse width modulation signal PWM₁And PWM_nAnd inductor current IL84₁And IL84_nTiming diagram 150 of the temporal relationship therebetween. For clarity, timing diagram 150 is a timing diagram for a two-phase power converter, i.e., a power converter with n-2. Thus, element 34_n、40_n、50_n、58_n、60_n、18_n、80_n、82_n、84_n、IL84_nAnd 86_nMay be respectively referenced by character 34₂、40₂、50₂、58₂、60₂、18₂、80₂、82₂、84₂、IL84₂And 86₂To identify. The number of phases is not a limitation of the present invention. The power converter 10 may be a two-phase power converter (n-2), a three-phase power converter (n-3), a four-phase power converter (n-4), or the like. It will be appreciated that in systems with more than two phases, i.e. n is greater than 2, each phase is compared with all other phases, and the exchange between the phases is preferably performed at the ramp crossing point.

As discussed above, the timing diagram 150 illustrates a triangular waveform or ramp signal generated by the oscillator 14 of the two-phase power converter. FIG. 2 shows a signal with an amplitude ranging from a low potential V_OSCLTo a high potential V_OSCHOf the triangular waveform of the oscillator signal OSC₁And has an amplitude ranging from a low potential V_OSCLTo a high potential V_OSCHOf the triangular waveform of the oscillator signal OSC₂. According to some embodiments, the oscillator signal OSC₁And OSC₂At a potential V_INTIntersecting, having the same frequency, and having phase angles that differ by 180 degrees. For clarity, the oscillator signal OSC₁Drawn as a dashed line, the oscillator signal OSC₂Drawn as a solid line.FIG. 150A shows an oscillator signal OSC₁FIG. 150B shows an oscillator signal OSC₂Fig. 150C shows the oscillator signal OSC in a single diagram₁And OSC₂. It should be noted that the oscillator signal OSC₁And OSC₂The type of waveform of (a) is not a limitation of the present invention. For example, the oscillator signal OSC₁And OSC₂Can have a saw tooth waveform, a sinusoidal waveform, or the like.

Graph 150D shows a signal appearing at comparator 50₁Is an input signal OSC of an inverting input_S1Input signal OSC_S1From time t₀To t₈Of the oscillator signal OSC₁And time t₈Post oscillator signal OSC₁And OSC₂The composition of (a). Plot 150E shows a signal appearing at comparator 50₂Is an input signal OSC of an inverting input_S2Input signal OSC_S2From time t₀To t₈Of the oscillator signal OSC₁And time t₈Post oscillator signal OSC₁And OSC₂The composition of (a). Fig. 150F shows the input signal OSC in a single diagram_S1And OSC_S2. It should be noted that the comparator input signal OSC_S1...OSC_SnCan be controlled by a slave oscillator signal OSC₁...OSC_nEither oscillator signal or a combination of oscillator signals is selected. In other words, the comparator input signal OSC_S1Can be controlled by an oscillator signal OSC₁、OSC₂...OSC_nIndividually or in combination. Likewise, the comparator input signal OSC_S2Can be controlled by an oscillator signal OSC₁、OSC₂...OSC_nFormed separately or in combination, comparator input signal OSC_S3Can be controlled by an oscillator signal OSC₁、OSC₂...OSC_nIndividually or in combination, and a comparator input signal OSC_SnCan be controlled by an oscillator signal OSC₁、OSC₂.. OSCn, individually or in combination.

At time t₀Switch 58₁And 60₁Disposed in the open position, switch 58₂And 60₂Is configured in a closed position. As discussed above, FIG. 2 shows waveforms for an embodiment where n is equal to 2, thus, two switches 58 are depicted₁And 58₂And two switches 60₁And 60₂. Thus, the oscillator signal OSC₁Is transmitted to the comparator 50₁And via input 34₁An input 54 to a comparator circuit 54₂And an oscillator signal OSC₂Is transmitted to the comparator 50₂And via input 34₂An input 54 to a comparator circuit 54₁. It should be noted that at time t₀Oscillator signal OSC₁And an input signal OSC_S1Substantially equal to each other, the oscillator signals OSC₂And an input signal OSC_S2Substantially equal to each other. Responsive to an oscillator signal OSC from oscillator 14₁And OSC₂Error signal from error amplifier 16 and current sense circuit 86₁And 86₂Respectively, PWM circuit 12 at output 44₁And 44₂Generating a pulse width modulated signal PWM₁And PWM₂And transmits it to the output driver circuit 18₁And 18₂。

At a time period t₀To t₄During the period, the oscillator signal OSC₁Is from potential V_OSCHLinearly reduced to potential V_OSCLAnd oscillator signal OSC₂Is from potential V_OSCLLinearly increasing to potential V_OSCHThe ramp signal of (2). Oscillator signal OSC₁And OSC₂At time t₄Respectively reach minimum (V)_OSCL) Potential sum maximum (V)_OSCH) And (4) electric potential. Then, from time t₄To time t₇Oscillator signal OSC₁Is from potential V_OSCLLinearly increasing to potential V_OSCHIs the ramp signal, the oscillator signal OSC₂Is from potential V_OSCHLinearly reduced to potential V_OSCLThe ramp signal of (2). Thus, the oscillator signal OSC₁And OSC₂From time t₀To t₇Circulate through oneComplete cycle, i.e. cycle T₁And at time t₇Starting a new cycle, i.e. the cycle T₂. According to an embodiment of the present invention, the period T₂Occurs at time t₇And t₁₅In the meantime.

From time t₇To time t₁₁Oscillator signal OSC₁Is from potential V_OSCHLinearly reduced to potential V_OSCLIs the ramp signal, the oscillator signal OSC₂Is from potential V_OSCLLinearly increasing to potential V_OSCHThe ramp signal of (2). Oscillator signal OSC₁And OSC₂At time t₁₁Respectively reaches a minimum potential and a maximum potential, and then from a time t₁₁To time t₁₅Oscillator signal OSC₁Is from potential V_OSCLLinearly increasing to potential V_OSCHIs the ramp signal, the oscillator signal OSC₂Is from potential V_OSCHLinearly reduced to potential V_OSCLThe ramp signal of (2).

At time t₂、t₆、t₈、t₁₃、t₁₈、t₂₀And t₂₆Oscillator signal OSC₁And OSC₂At a potential V_INTCrossing, i.e. the oscillator signal OSC₁And OSC₂Are equal in potential. At time t₄、t₇、t₁₁、t₁₅、t₁₉、t₂₃And t₂₈Oscillator signal OSC₁At a potential V_OSCLOscillator signal OSC₂At a potential V_OSCH. Likewise, at time t₂、t₆、t₉、t₁₃、t₁₈、t₂₀And t₂₆Input signal OSC_S1And OSC_S2At a potential V_INTCrossing, i.e. the oscillator signal OSC₁And OSC₂Are equal in potential.

At time t₃Appears at the output 44₁Is driven from a logic low potential V_LIncrease to a logic high potential V_HThis results in a current IL84₁From the lower peak current level I_P-And (4) increasing. At time t₅Appears at the output 44₁Is driven from a logic high potential V_HReduced to a logic low potential V_LThis results in a current IL84₁From the upper peak current level I_P+And (4) reducing. Thus, pulse PWM₁Appears at output 44₁Having a rising edge and a falling edge, the rising edge causing current IL84₁Increasing, falling edge induced current IL84₁And (4) reducing. At time t₃And t₅In turn, current IL84₁Increased to greater than current IL84₂The level of (c). From time t₄To time t₇Oscillator signal OSC₁And a comparator input signal OSC_S1From potential V_OSCLRises to a potential V_OSCH。

At time t₆I.e. when the oscillator signal OSC is present₁Rising time, oscillator signal OSC₁And OSC₂Is equal to the voltage V_INTI.e. they are equal to each other. Because when the oscillator signal OSC is present₁And OSC₂At time t₆Crossing oscillator signal OSC₁Is rising, switch 58₁And 58₂Remains open and switch 60₁And 60₂And remain closed. However, at time t₇Oscillator signal OSC₁To the maximum potential V_OSCHAnd begins to decrease. At time t₈Oscillator signal OSC₁And OSC₂Crossing, i.e. they are substantially at the same potential, the oscillator signal OSC₁At the reduced current IL84₁Greater than current IL84₂. At oscillator signal OSC₁And OSC₂Comparator input signal OSC_S1And OSC_S2And a current IL84₁And IL84₂Under these conditions, comparator circuits 54 and 56 generate switching signals that cause switch control circuit 68 to close switch 58₁And 60₁Opening the switch 58₂And 60₂Whereby switching occurs at comparator 50₁And 50₂The inverted input oscillator signal of (1). After the handoverOscillator signal OSC₁Appears in the comparator 50₁Is an oscillator signal OSC₂Appears in the comparator 50₂Is input in the opposite phase. Before switching, the oscillator signal OSC₁Appears in the comparator 50₂Is an oscillator signal OSC₂Appears in the comparator 50₁Is input in the opposite phase. Thus, the comparator 50 is switched₁And 50₂The oscillator signal at the input of (a) is referred to as switching the phase of the input signal. It should be noted that signal OSC is shown in FIG. 150D_S1Is present in comparator 50₁Of the input signal, signal OSC_S2Is present in comparator 50₂Is input in the opposite phase. Thus, the comparator 50 is switched₁And 50₂To distribute the lowest inductor current to the comparator input with the lowest level, which quickly balances the currents.

At time t₉Appears at the output 44₂Is driven from a logic low potential V_LIncrease to a logic high potential V_HThis results in a current IL84₂From the lower peak current level I_P-And (4) increasing. At time t₁₂Appears at the output 44₂Is driven from a logic high potential V_HReduced to a logic low potential V_LThis results in a current IL84₂From the upper peak current level I_P+And (4) reducing. Thus, pulse PWM₂Appears at output 44₂Having a rising edge and a falling edge, the rising edge causing current IL84₂Increasing, falling edge induced current IL84₂And (4) reducing. At time t₉And t₁₁In turn, current IL84₂Increased to greater than current IL84₁The level of (c). From time t₁₁To time t₁₅Oscillator signal OSC₁And a comparator input signal OSC_S1From potential V_OSCHDown to potential V_OSCL. At time t₁₃Oscillator signal OSC₁And OSC₂And comparator input signal OSC_S1And OSC_S2Is equal in potential, the oscillator signal OSC₁And comparator signal OSC_S1At the reduced current IL84₂Greater than current IL84₁. At oscillator signal OSC₁And OSC₂Comparator input signal OSC_S1And OSC_S2And a current IL84₁And IL84₂Under these conditions, the switch 58₁And 60₁Remains closed, switch 58₂And a switch 60₂Remains on, does not switch the oscillator signal OSC₁And OSC₂。

At time t₁₄Appears at the output 44₁Is driven from a logic low potential V_LIncrease to a logic high potential V_HThis results in a current IL84₁From the lower peak current level I_P-And (4) increasing. At time t₁₆Appears at the output 44₁Is driven from a logic high potential V_HReduced to a logic low potential V_LThis results in a current IL84₁From the upper peak current level I_P+And (4) reducing. Thus, another pulse PWM₁Appears at output 44₁Having a rising edge and a falling edge, the rising edge causing current IL84₁Increasing, falling edge induced current IL84₁And (4) reducing. At time t₁₄And t₁₇In turn, current IL84₁Increased to greater than current IL84₂The level of (c). From time t₁₅To time t₁₉Input signal OSC_S1From potential V_OSCLRises to a potential V_OSCH。

At time t₁₈I.e. when the comparator input signal OSC_S1At the rising time, the oscillator signal OSC₁And OSC₂And a comparator input signal OSC_S1And OSC_S2Is equal to the voltage V_INTI.e. they are equal to each other. Because when the oscillator signal OSC is present_S1And OSC_S2At time t₁₈Input signal OSC at the time of crossing_S1At the rise, the switch 58₁And 60₁Remains closed, switch 58₂And 60₂Remain open. However, at time t₁₉Input signal OSC_S1To the maximum potential V_OSCHAnd begins to decrease. Thus, at the momentt₂₀Input signal OSC_S1And OSC_S2Crossing, i.e. their potentials are equal, comparator input signal OSC_S1At the reduced current IL84₁Greater than current IL84₂. At oscillator signal OSC₁And OSC₂Comparator input signal OSC_S1And OSC_S2And a current IL84₁And a current IL84₂Under these conditions, comparator circuits 54 and 56 generate switching signals that cause switch control circuit 68 to open switch 58₁And 60₁And closing the switch 58₂And 60₂Whereby switching occurs at comparator 50₁And 50₂The inverted input oscillator signal of (1). After switching, the input signal OSC_S1Appears in the comparator 50₂Is an oscillator signal OSC_S2Appears in the comparator 50₁Is input in the opposite phase. Before switching, the input signal OSC_S2Appears in the comparator 50₁Is an inverting input of, the input signal OSC_S1Appears in the comparator 50₂Is input in the opposite phase. Thus, the comparator 50 is switched₁And 50₂To distribute the lowest inductor current to the comparator input signal with the lowest level, which quickly balances the currents.

At time t₂₁Appears at the output 44₂Is driven from a logic low potential V_LIncrease to a logic high potential V_HThis results in a current IL84₂From the lower peak current level I_P-And (4) increasing. At time t₂₄Appears at the output 44₂Is driven from a logic high potential V_HReduced to a logic low potential V_LThis results in a current IL84₂From the upper peak current level I_P+And (4) reducing. Thus, another pulse PWM₁Appears at output 44₁Having a rising edge and a falling edge, the rising edge causing current IL84₁Increasing, falling edge induced current IL84₁And (4) reducing. At time t₂₂And t₂₅In turn, current IL84₂Increased to greater than current IL84₁The level of (c). From time t₂₃To time t₂₆Input signal OSC_S1From potential V_OSCLRises to a potential V_OSCH. At time t₂₅Comparator input signal OSC_S1And OSC_S2Are equal in potential, the comparator input signal OSC_S1At the increased current IL84₂Greater than current IL84₁. At the input signal OSC_S1And OSC_S2And a current IL84₁And IL84₂Under these conditions, the switch 58₁And 60₁Remains open, switch 58₂And 60₂Remains closed, does not switch the input signal OSC_S1And OSC_S2。

FIG. 3 shows the error signal 162 and the oscillator signal OSC₁And OSC₂The timing relationship 160 therebetween. More specifically, FIG. 3 shows a schematic diagram for the oscillator signal OSC₁And OSC₂Has a large semaphore error signal and the current can be balanced between the phases without changing the total duty cycle applied to the output filter.

By now it should be appreciated that a multiphase power converter circuit and a method for balancing currents in a multiphase power converter circuit have been provided. Preferably, the current is dynamically balanced by exchanging oscillator signals in the pulse width modulator circuit. This provides a multi-phase system that is capable of rapidly balancing current on a cycle-by-cycle basis during dynamic loading because oscillator signals falling from a higher potential to a lower potential are more likely to produce higher duty cycle pulse width modulated signals than oscillator signals rising from a lower potential to a higher potential. Thus, if the inductor current is low in a particular phase, the current is distributed to the oscillator signal with the lowest potential to quickly balance the currents.

In accordance with an embodiment of the present invention, when multiphase power converter 10 begins operation, switch control circuit 68 receives a clock signal from comparator circuit 54 that indicates which of the ramps from oscillator 14 have crossed. The crossing ramp may be in the PWM comparator 50₁...50_nAnd (4) exchanging between the two. The exchange of ramp signals being based on currentInductor current IL84 determined by comparator circuit 56₁...IL84_nThe state of (1). At or near the time of the ramp crossing, the oscillator signal transitioning from a higher level to a lower level, i.e., the falling ramp signal, will be swapped to the PWM comparator 50 associated with the lower current phase₁...50_n(if not already connected thereto). Likewise, the oscillator signal transitioning from a lower level to a higher level, i.e., the increased ramp signal, will be exchanged via signal MUX58 to the PWM comparator 50 associated with the higher current phase₁...50_n. Preferably, there are no two PWM comparators 50₁...50_nCan be connected to the same oscillator signal and the number of oscillator signals is designed such that one oscillator signal corresponds to each PWM signal. Thus, at the intersection of each ramp phase, the ramp signal is at the PWM comparator 50₁...50_nAnd (4) exchanging between the two.

While certain preferred embodiments and methods have been disclosed herein, it will be apparent to those skilled in the art from the foregoing disclosure that variations and modifications of such embodiments and methods may be made without departing from the spirit and scope of the invention. For example, rather than using comparator circuit 54, i.e., comparator circuit 54 may be absent, oscillator 14 may be used to generate a signal that is transmitted to input 66 of switch control circuit 68. Furthermore, during dynamic loading, ramp switching may be activated, which can be determined from the output error signal of input 38. In this case, when ramp swapping is disabled, switch control circuit 68 can swap the ramps back to their original order to maintain the trigger order of the state phases. It is intended that the invention shall be limited only to the extent required by the appended claims and the rules and principles of applicable law.

Claims (20)

1. A method for current balancing in a multiphase power converter having a plurality of outputs, comprising the steps of:

providing a plurality of currents;

providing a plurality of input signals, the plurality of input signals generated in response to respective oscillator signals; and

switching at least a first input signal and a second input signal of the plurality of input signals in response to a current level of a first current of at least two of the plurality of currents being greater than a current level of a second current of the plurality of currents, levels of the first input signal and the second input signal of the plurality of input signals being equal, and the first input signal of the plurality of input signals being decreasing.

2. The method of claim 1, wherein the step of switching at least the first input signal and the second input signal comprises:

determining that the first one of the plurality of currents is less than the second one of the plurality of currents; and

determining that the first input signal of the plurality of input signals is decreasing.

3. The method of claim 2, wherein the step of switching at least a first input signal and a second input signal comprises: generating a switching signal in response to the first and second input signals of the plurality of input signals being equal.

4. The method of claim 1, wherein the step of generating the switching signal comprises:

generating a first pulse having a first edge and a second edge in response to the first input signal; and

in response to a first edge of the first pulse, increasing a level of the first one of the plurality of currents to a level greater than the second one of the plurality of currents.

5. The method of claim 4, further comprising: reducing the first current of the plurality of currents in response to the second edge of the pulse signal.

6. The method of claim 5, further comprising: generating a first switching signal in response to the first input signal of the plurality of input signals decreasing from a first level to a second level, the second input signal of the plurality of input signals increasing from the second level to the first level such that their voltage levels are equal at an intermediate voltage level, wherein a first induced current generated in response to the first input signal is greater than a second induced current generated in response to the second input signal.

7. The method of claim 6, further comprising: generating the first switching signal in response to the first one of the plurality of input signals being at the same level as the second one of the plurality of input signals.

8. The method of claim 7, further comprising:

generating a second pulse having a first edge and a second edge in response to the second input signal; and

in response to a first edge of the second pulse, increasing a level of the second one of the plurality of currents to a level greater than the first one of the plurality of currents.

9. The method of claim 8, further comprising:

generating a third pulse having a first edge and a second edge in response to the first input signal;

increasing the first current of the plurality of currents in response to a first edge of the third pulse;

after the first one of the plurality of currents is greater than the second one of the plurality of currents, reducing the first one of the plurality of currents in response to the second edge of the pulse signal; and

generating a second switching signal in response to the second one of the plurality of input signals decreasing from the first level to the second level and in response to the second one of the plurality of input signals being at the same level as the first one of the plurality of input signals.

10. A method for current balancing in a system having an error signal, comprising the steps of:

providing a plurality of input signals generated in response to respective oscillator signals, wherein a first input signal of the plurality of input signals has a first phase, a second input signal of the plurality of input signals has a second phase, and wherein the first phase and the second phase are different from each other; and

switching the first phase of the first input signal and the second phase of the second input signal to balance currents in the system in response to a current level of a first current being greater than a current level of a second current, the first and second input signals of the plurality of input signals being equal, and the first input signal of the plurality of input signals being decreasing.

11. The method of claim 10, further comprising:

providing the first current and the second current, wherein the first current has a rising edge and a falling edge and the second current has a rising edge and a falling edge, and wherein the first current and the second current are out of phase with each other and the first current is less than the second current;

increasing the first current; and

after the first current is greater than the second current, the first current is reduced.

12. The method of claim 11, wherein the step of increasing the first current comprises:

increasing the first current to be greater than the second current in response to a first edge of a first pulse; and

reducing the first current comprises: reducing the first current in response to a second edge of the first pulse, and wherein the first current and the second current are reduced in response to the second edge of the first pulse.

13. The method of claim 12, wherein switching the first phase of the first input signal with the second phase of the second input signal comprises: changing a direction of the first input signal from decreasing to increasing in response to the first input signal and the second input signal having the same value and the first current being greater than the second current.

14. The method of claim 12, further comprising:

reducing the second current in response to a second edge of a second pulse;

increasing the first current to be greater than the second current in response to a first edge of a first pulse;

after the first current is greater than the second current, decreasing the first current in response to a second edge of the first pulse and increasing the second current in response to a first edge of the second pulse; and

switching the first phase of the first input signal with the second phase of the second input signal comprises: changing a direction of the first input signal from decreasing to increasing in response to the first input signal and the second input signal having the same value and the first current being greater than the second current.

15. The method of claim 10, wherein each of the plurality of input signals has the same frequency.

16. A multiphase power converter comprising:

a pulse width modulator having at least one input and at least one output, wherein the pulse width modulator comprises:

a first oscillator signal switching circuit having a first input, a second input, and an output;

a second oscillator signal switching circuit having a first input, a second input, and an output; and

a switch control circuit having at least a first input and a second input and a plurality of outputs, wherein a first input of the at least one input is coupled to the first input of the first oscillator signal switching circuit and to the first input of the second oscillator signal switching circuit, wherein the pulse width modulator is configured to switch a first phase of a first input signal and a second phase of a second input signal to balance currents in a system in response to a current level of the first current being greater than a current level of the second current, the first input signal and the second input signal being at a same level and the first input signal being decreasing.

17. The multiphase power converter of claim 16,

the first oscillator signal switching circuit includes:

a first comparator having an inverting input, a non-inverting input, and an output;

a first switch coupled between the inverting input of the first comparator and a first one of the plurality of inputs of the pulse width modulator, wherein a first one of the plurality of outputs of the switch control circuit is coupled to the first switch;

a second switch coupled between the inverting input and a second input of the plurality of inputs of the pulse width modulator, wherein a second output of the plurality of outputs of the switch control circuit is coupled to the first switch;

the second oscillator signal switching circuit includes:

a second comparator having an inverting input, a non-inverting input, and an output;

a third switch coupled between the inverting input of the second comparator and the second one of the plurality of inputs of the pulse width modulator, wherein a third one of the plurality of outputs of the switch control circuit is coupled to the third switch; and

a fourth switch coupled between the inverting input of the second comparator and the first one of the plurality of inputs of the pulse width modulator, wherein a fourth one of the plurality of outputs of the switch control circuit is coupled to the fourth switch.

18. The multiphase power converter of claim 17, further comprising:

a third comparator having an inverting input, a non-inverting input and an output, wherein the non-inverting input is coupled to the inverting inputs of the first comparator and the second comparator through the second switch and the third switch, respectively, and the inverting input is coupled to the inverting inputs of the first comparator and the second comparator through the first switch and the fourth switch, respectively; and

a fourth comparator having an inverting input, a non-inverting input, and an output, wherein the output is coupled to the second input of the switch control circuit.

19. The multiphase power converter of claim 18, further comprising:

an oscillator having a plurality of outputs, wherein a first output of the plurality of outputs is coupled to the first input of the plurality of inputs of the pulse width modulator and a second output of the plurality of outputs is coupled to the second input of the plurality of inputs of the pulse width modulator; and

an error circuit having an output coupled to the inverting inputs of the first and second comparators.

20. The multiphase power converter of claim 19, further comprising:

a first output stage having: an input coupled to a first output of the plurality of outputs of the pulse width modulator, and a current sense output coupled to the non-inverting input of the fourth comparator; and

a second output stage having: an input coupled to a second output of the plurality of outputs of the pulse width modulator, and a current sense output coupled to the inverting input of the fourth comparator.