HK1144732B - Electronic device including an insulating layer having different thicknesses and a conductive electrode and a process of forming the same - Google Patents

Description

Electronic device with insulating layer and conductive electrode of different thickness and forming method

Technical Field

The present disclosure relates to electronic devices and methods of forming electronic devices, and more particularly, to electronic devices including insulating layers and conductive electrodes having different thicknesses and methods of forming the same.

Background

Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are one common type of power conversion device. A MOSFET includes a source region, a drain region, a channel region extending between the source and drain regions, and a gate structure disposed adjacent to the channel region. The gate structure includes a gate electrode layer disposed adjacent to the channel region and separated from the channel region by a thin dielectric layer.

When the MOSFET is in an on-state, a voltage is applied to the gate structure to form a conductive channel region between the source and drain regions, which allows current to flow through the device. In the closed state, any voltage applied to the gate structure is low enough that a conductive channel cannot form and thus current cannot occur. During the closed state, the device must support a high voltage between the source and drain regions.

In optimizing the performance of a MOSFET, designers are often faced with tradeoffs in device parametric performance. Specifically, the selection of available device structures or fabrication methods may increase one device parameter, but at the same time, such selection may decrease one or more other device parameters. For example, increasing the resistance (R) of a MOSFET_DSON) The available structure and method can reduce the Breakdown Voltage (BV)_DSS) And increases the parasitic capacitance between regions within the MOSFET.

Drawings

The embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings.

Fig. 1 includes an illustration of a cross-sectional view of a portion of a workpiece including an underlying doped region (underlying doped region), a semiconductor layer, a pad layer (pad layer), and a stopping layer (stopping layer).

FIG. 2 includes an illustration of a cross-sectional view of the workpiece of FIG. 1 after forming a trench extending through the semiconductor layer to an underlying doped region.

FIG. 3 includes an illustration of a cross-sectional view of the workpiece of FIG. 2 after forming a conductive layer that substantially fills the trench.

Fig. 4 includes an illustration of a cross-sectional view of the workpiece of fig. 3 after removing a portion of the conductive layer located outside of the trench, and after forming sidewall doped regions.

Fig. 5 includes an illustration of a cross-sectional view of the workpiece of fig. 4 after removal of the stop layer.

FIG. 6 includes an illustration of a cross-sectional view of the workpiece of FIG. 5 after forming an insulating layer having different regions.

Fig. 7A-10 include illustrations of cross-sectional views of portions of the workpiece of fig. 6 having different shapes at transitions between regions within an insulating layer according to various embodiments.

FIG. 11 includes an illustration of a cross-sectional view of the workpiece of FIG. 6 after forming a conductive layer on an insulating layer.

FIG. 12 includes an illustration of a cross-sectional view of the workpiece of FIG. 11 after forming a plurality of layers on a conductive layer.

FIG. 13 includes an illustration of a cross-sectional view of the workpiece of FIG. 12 after forming openings extending through multiple layers.

FIG. 14 includes an illustration of a cross-sectional view of the workpiece of FIG. 13 after forming insulating sidewall spacers (sidewall spacers).

FIG. 15 includes an illustration of a cross-sectional view of the workpiece of FIG. 14 after forming a conductive layer overlying an exposed surface of the workpiece and forming a well region within a semiconductor layer.

FIG. 16 includes an illustration of a cross-sectional view of the workpiece of FIG. 15 after forming a remaining portion of the conductive layer over an exposed surface of the workpiece.

FIG. 17 includes an illustration of a cross-sectional view of the workpiece of FIG. 16 after forming a gate electrode.

FIG. 18 includes an illustration of a cross-sectional view of the workpiece of FIG. 17 after removal of the uppermost insulating layer, truncation of the insulating sidewall spacers, and filling of the gap between the gate electrode and the conductive layer with a conductive fill material.

Fig. 19 includes an illustration of a cross-sectional view of the workpiece of fig. 18 after forming openings through an interlayer dielectric layer and source regions, and after forming well contact regions.

Fig. 20 includes an illustration of a cross-sectional view of the workpiece of fig. 19 after forming a substantially complete electronic device in accordance with an embodiment of the invention.

Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.

Detailed Description

The following description, taken in conjunction with the accompanying drawings, is provided to assist in understanding the teachings disclosed herein. The following discussion will focus on specific implementations and embodiments of the teachings. This focus is provided to assist in describing the teachings and should not be construed as limiting the scope or applicability of the teachings. However, other teachings may of course be utilized in this application.

The terms "normal operation" and "normal operating state" refer to conditions under which an electronic component or device is designed to operate. The conditions may be derived from a spreadsheet or other data sheet relating to voltage, current, capacitance, resistance, or other electrical conditions. Thus, normal operation does not include operating an electronic component or device beyond its design limits.

The terms "comprising," "including," "having," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a method, article, or apparatus that comprises a list of features is not necessarily limited to only those features but may include other features not expressly listed or inherent to such method, article, or apparatus. Further, unless expressly stated to the contrary, "or" refers to an inclusive-or, rather than an exclusive-or. For example, the condition a or the condition B satisfies any one of the following conditions: a is true (or present) and B is spurious (or absent), a is spurious (or absent) and B is true (or present), and both a and B are true (or present).

Also, the use of "a" or "an" is used to describe various elements and components described herein. This is done merely for convenience and to give a general sense of the scope of the invention. This description should be read to include one or at least one and the singular also includes the plural or vice versa unless clearly indicated otherwise. For example, when a single item is described herein, more than one item may be used in place of a single item. Similarly, when more than one item is described herein, a single item may replace the more than one item.

The family numbers corresponding to columns in the periodic Table of elements use a "New notation" protocol, such as CRCHandbook of Chemistry and Physics, 81^stEdition (2000-.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The materials, methods, and examples are illustrative only and not intended to be limiting. To the extent not described herein, many details regarding specific materials and process steps are conventional and may be found in textbooks and other sources within the semiconductor and electronic arts.

Fig. 1 includes an illustration of a cross-sectional view of a portion of a workpiece 100. The workpiece 100 includes an underlying doped region 102, the doped region 102 being lightly or heavily doped, n-type or p-type. For the purposes of this specification, heavily doped is intended to mean at least 10¹⁹Atom/cm³While the expectation of light doping means less than 10¹⁹Atom/cm³The peak dopant concentration of (a). The underlying doped region 102 may be a portion of a heavily doped substrate (e.g., a heavily n-doped sheet) or may be an embedded doped region overlying a substrate of the opposite conductivity type or an embedded insulating layer (not shown) located between the substrate and the embedded doped region. In particular embodiments, the underlying doped region 102 may include a lightly doped portion overlying a heavily doped portion, for example, when the overlying semiconductor layer 104 is of opposite conductivity type, to help increase junction breakdown voltage (junction breakdown). In an embodiment, the underlying doped region 102 is heavily doped with an n-type dopant, such as phosphorus, arsenic, antimony, or any combination thereof. In a particular embodiment, the underlying doped region 102 includes arsenic or antimony if the diffusion of the underlying doped region 102 is to be kept low, and in a particular embodiment, the underlying doped region 102 includes antimony to reduce the degree of outgassing (compared to arsenic) during formation of the semiconductor layer 104.

In the embodiment illustrated in fig. 1, the semiconductor layer 104 overlies the underlying doped region 102. The semiconductor layer 104 has a major surface 105. The semiconductor layer 104 may include a group 14 element (i.e., carbon, silicon, germanium, or any combination thereof) and any of the dopants described with respect to the doped region 102 below or dopants of the opposite conductivity type. In an embodiment, the semiconductor layer 104 is a lightly doped n-type or p-type epitaxial silicon layer having about 0.5 microns toA thickness in the range of about 5.0 microns and a doping concentration of no greater than about 10¹⁶Atom/cm³And, in another embodiment, the doping concentration is at least about 10¹⁴Atom/cm³。

The pad layer 106 and the stop layer 108 (e.g., a polish stop layer or an etch stop layer) are formed on the semiconductor layer 104 using thermal growth techniques, deposition techniques, or a combination thereof. Each of the pad layer 106 and the stop layer 108 may comprise an oxide, a nitride, an oxynitride, or any combination thereof. In an embodiment, the pad layer 106 has a different composition than the stop layer 108. In a specific embodiment, the pad layer 106 comprises an oxide and the stop layer 108 comprises a nitride.

Referring to fig. 2, portions of the semiconductor layer 104, the pad layer 106, and the stop layer 108 are removed to form a trench, such as trench 202, extending from the major surface 105 of the semiconductor layer 106 toward the underlying doped region 102. The slot 202 may be a single slot with different portions as shown in fig. 2, or the slot 202 may include a plurality of different slots. The width of the groove 202 is not so wide that a subsequently formed conductive layer cannot fill the groove 202. In particular embodiments, the width of each groove 202 is at least about 0.3 microns or about 0.5 microns, and in another particular embodiment, the width of each groove 202 is no greater than about 4 microns or about 2 microns. After reading this specification, skilled artisans will appreciate that narrower or wider widths outside the specified dimensions may be used. The trench 202 may extend to the underlying doped region 102; however, the groove 202 may be shallower if needed or desired.

The grooves are formed using anisotropic etching. In an embodiment, a timed etch may be performed, while in another embodiment, a combination of endpoint detection (e.g., detection of a dopant species, such as arsenic or antimony, in the underlying doped region 102) and a timed over-etch may be employed.

If needed or desired, dopants can be introduced into a portion of the semiconductor layer 104 along the sidewalls 204 of the trench 202 to form heavily doped sidewall doping regions (not illustrated in fig. 2). Tilt angle implantation techniques, dopant gases, or solid dopant sources may be used.

As shown in fig. 3, a conductive layer 302 is formed on the stop layer 108 and within the trench 202. The conductive layer 302 substantially fills the slot 202. The conductive layer 302 may include a metal-containing or semiconductor-containing material. In an embodiment, the conductive layer 302 may include a heavily doped semiconductor material, such as amorphous silicon or polysilicon. In another embodiment, the conductive layer 302 includes a plurality of films, such as an adhesive film, a barrier film, and a conductive filler material. In particular embodiments, the tacking film may include a high temperature resistant metal, such as titanium, tantalum, or the like; the barrier film may include a high temperature resistant metal nitride such as titanium nitride, tantalum nitride, or the like, or a high temperature resistant metal semiconductor nitride such as TaSiN; and the conductive fill material may comprise tungsten. In a more specific embodiment, conductive layer 302 may comprise Ti/TiN/W. The number of films and the composition of those films are selected based on electrical properties, temperature of subsequent thermal cycling, other criteria, or any combination thereof. Refractory metals and refractory metal-containing compounds can withstand high temperatures (e.g., the melting point of these materials can be at least 1400 ℃), can be conformally deposited, and have a low bulk resistivity compared to heavily doped n-type silicon. After reading this specification, skilled artisans will be able to determine the composition of the conductive layer 302 to meet their needs or desires for a particular application.

The portion of the conductive layer 302 overlying the stop layer 108 is removed to form a conductive structure within the trench, such as conductive structure 402 within the trench 202, as shown in the embodiment of fig. 4. The removal may be performed using chemical mechanical polishing or blanket etching (blanket etchingtechnique). The stop layer 108 may function as a polish stop layer or an etch stop layer. Polishing or etching may continue for a relatively short period of time after the stop layer 108 reaches a thickness relative to the conductive layer 302, a polishing or etching operation, or any combination thereof to cause non-uniformity across the workpiece.

Before, during, or after forming the conductive structure, a sidewall doped region, such as sidewall doped region 404, may be formed from a portion of semiconductor layer 104 and extend from sidewall 204. Dopants may be introduced in the doping operation described above and become activated when the conductive layer 302 is formed. Alternatively, when the conductive layer 302 includes a doped semiconductor material, the dopant can diffuse from the conductive structure 402 or from the conductive layer 302 (before the conductive structure 402 is completely formed).

In fig. 5, the stop layer 108 is removed and portions of the semiconductor layer 104 proximate the major surface 105 and the sidewall doped regions, e.g., sidewall doped region 404, are doped to form surface doped regions, e.g., surface doped region 504, which are spaced apart from the underlying doped region 102. The surface doped regions 504 have the same conductivity type as the sidewall doped regions 404 and the underlying doped region 102. The surface doped regions 504 have a depth in a range from about 0.1 microns to about 0.5 microns. The lateral dimension (from the conductive structure 402) may depend on the voltage difference between the source and drain of the formed power transistor. As the voltage difference between the source and drain of the transistor increases, the lateral dimensions may also increase. In an embodiment, the voltage difference is greater than about 20V, and in another embodiment, the voltage difference is no greater than 30V, 50V, or greater. The lateral dimension extending from the conductive structure 402 may be in a range of about 0.2 microns to about 3.0 microns. In a specific embodiment, the lateral dimension is in a range from about 0.5 microns to about 2.0 microns. The peak doping concentration in the horizontally oriented doped region may be about 2 x 10¹⁷Atom/cm³To about 2X 10¹⁸Atom/cm³And, in particular embodiments, at about 4 × 10¹⁷Atom/cm³To about 7X 10¹⁷Atom/cm³The range of (1). The pad layer 106 may remain on the semiconductor layer 104 after the surface doped region 504 is formed or may be removed after the surface doped region 504 is formed.

An insulating layer 62 is formed over the conductive structure 402 and the pad layer 106 as shown in fig. 6. The insulating layer 62 includes at least two different regions having different thicknesses. In fact, the insulating layer 62 has a stepped configuration, the importance of which is described later in this specification. In the embodiment shown in fig. 6, insulating layer 62 includes regions 622, 624, and 626. Region 622 overlies surface doped region 504 and is closer to the subsequently formed gate electrode, channel region, and source region. The thickness of insulating layer 62 is thinner in region 622 than in region 626. The thickness of insulating layer 62 within region 624 may be the same as the thickness within regions 622 or 626, or may have a thickness between the thicknesses of regions 622 and 626.

In an embodiment, the thickness of insulating layer 62 within region 622 is at least about 0.02 microns or at least about 0.05 microns, and in another embodiment, the thickness of insulating layer 62 within region 622 is no greater than about 0.2 microns or no greater than about 0.1 microns. Region 624 overlies surface doped region 504 and may be thicker than region 622. In an embodiment, the thickness of the insulating layer 62 within the region 624 is at least about 0.05 microns or at least about 0.15 microns, and in another embodiment, the thickness of the insulating layer 62 within the region 624 is no greater than about 0.5 microns or no greater than about 0.25 microns. Region 626 overlies conductive structure 402 and is thicker than region 622. Regions 624 and 626 may have the same thickness or different thicknesses. In an embodiment, the thickness of the insulating layer 62 within the region 626 is at least about 0.15 microns or at least about 0.25 microns, and in another embodiment, the thickness of the insulating layer 62 within the region 626 is not greater than about 0.8 microns or not greater than about 0.5 microns. In a specific embodiment, the thickness of the insulating layer 62 in the region 622 is in a range of about 0.03 microns to about 0.08 microns, the thickness of the insulating layer 62 in the region 624 is in a range of about 0.13 microns to about 0.2 microns, and the thickness of the insulating layer 62 in the region 626 is in a range of about 0.3 microns to about 0.5 microns.

The insulating layer 62 may be formed by different techniques and obtain different shapes when viewed from a cross-sectional view. The insulating layer 62 may be formed of a single insulating film or a plurality of insulating films deposited on the workpiece. The insulating film or films may include an oxide, a nitride, an oxynitride, or a combination thereof. In particular embodiments, the properties of insulating layer 62 may be different for locations closer to pad layer 106 and conductive structure 402 than for locations further from pad layer 106 and conductive structure 402, respectively. In an embodiment, the composition of the insulating layer 62 may vary during or between depositions. For example, an oxide film may be closer to the doped regions 504 and the conductive structures 402, while a nitride film may be deposited on the oxide film. In another embodiment, a dopant, such as phosphorus, may be incorporated at an increased concentration in the later portion of the deposition. In yet another embodiment, even though the composition is substantially the same throughout the thickness of the insulating layer 62, the stress within the film can be varied by varying deposition parameters (e.g., rf power, pressure, etc.). In further embodiments, the foregoing compositions may be used.

Fig. 7-10 include cross-sectional views of portions of a workpiece to show possible shapes of transitions between regions of the insulating layer 62. The shapes and corresponding techniques in fig. 7-10 illustrate only some exemplary, non-limiting shapes and techniques. After reading this specification, one of ordinary skill in the art will appreciate that other shapes and techniques may be used without departing from the scope of the concepts described herein.

Referring to fig. 7A and 7B, the insulating layer 62 may include a plurality of insulating films that may allow different thicknesses in different regions. In the embodiment shown in fig. 7B, the underlayer 106 may comprise an oxide having a thickness in the range of about 50nm to about 100nm, and in a specific embodiment, in the range of about 60nm to about 70 nm. A nitride film 702 and an oxide film 704 may be successively deposited on the underlayer 106 and the conductive structure 402. The nitride film 702 may have a thickness ranging from about 30nm to about 70nm, while the oxide film 704 may have a thickness ranging from about 0.2 microns to about 0.5 microns. In particular embodiments, the oxide film 704 may be formed using tetraethylorthosilicate (tetraethoxysilane) with sufficient step coverage (step coverage).

After depositing the nitride film 702 and the oxide film 704, the resist mask 72 may be formed and patterned to define an opening to expose a portion of the oxide film 704 corresponding to the region 622, as shown in fig. 7A. The exposed portions of the oxide film 704 may be isotropically etched and undercut a portion of the resist mask 72 to remove the oxide film 704 from the regions 624. In this particular embodiment, the transition 722 between regions 624 and 626 has a concave shape. In a more specific embodiment, prior to removing resist mask 72, the remaining portion of insulating layer 62 in region 622, along with pad layer 106, may be partially or completely removed by anisotropic etching after isotropic etching to form transition 722.

The resist mask 72 may then be removed as shown in fig. 7B, and additional insulating material may be added to the layer 62 using thermal growth techniques, deposition techniques, or a combination thereof. In a specific embodiment, oxide film 742 may be thermally grown from silicon within doped region 504 to a thickness in the range of about 20nm to about 40nm, and nitride film 744 may be deposited on oxide film 742, nitride film 702, and oxide film 704. The nitride film 744 may have a thickness as previously described with respect to the nitride film 702. The nitride films 702 and 744 may have the same thickness or different thicknesses. These additional process actions can further enable shaping of the thickness of insulating layer 62 between regions 622 and 624. In this particular embodiment, insulating layer 62, including pad layer 106 and films 702, 704, 742, and 744, has different thicknesses within regions 622, 624, and 626. More specifically, the thickness of insulating layer 62 within region 624 is closer to the thickness within region 622 than region 626. In another embodiment (not shown), the transition may be a single step. In this embodiment, the oxide film may be anisotropically etched until a portion or the entire thickness of the oxide film within the opening of the resist mask 72 is removed. After reading this description, skilled artisans will appreciate that other embodiments may be used to implement a stepped dielectric that can be tailored to a particular application.

In the embodiment shown in fig. 8-10, the thickness of the insulating layer within regions 624 and 626 is substantially the same. In other embodiments (not shown), the thickness of insulating layer 62 within region 624 may be different than the thickness within regions 622 and 624.

Fig. 8 includes an illustration of an insulating layer 62 having multiple steps to create a stepped structure at the transition 822 between regions 622 and 624. A resist mask is formed and patterned to define an opening. The initial shape of the opening corresponds to the vertical surface of the transition 822 closest to the region 622. The insulating layer 62 is etched only partially through the thickness of the insulating layer 62. The depth of the etch corresponds to the vertical surface closest to region 622. After that, the resist mask 82 is isotropically etched to widen the opening. The process steps continue with alternating anisotropic etching of the insulating layer 62 and isotropic etching of the resist mask 82 to achieve a desired or expected profile of the transition 822 between the regions 622 and 624. More or less steps may be formed in the transition 822 and the ratio of the vertical and linear dimensions of the steps may be adjusted as needed or desired.

Fig. 9 includes an illustration of the insulating layer 62 having a linearly sloped surface at the transition 922 between the regions 622 and 624. A resist mask is formed and patterned to define an opening. The initial shape of the opening corresponds to where the transition 922 meets the horizontal portion of the insulating layer 62 extending over the region 622. The insulating layer 62 and the resist mask 92 can be etched simultaneously during at least one point time. In the embodiment shown in fig. 9, the insulating layer 62 and the resist mask 92 are etched during substantially all of the etching operation. The etching may be terminated when an underlying insulating film (shown by dashed lines) within the insulating layer 62 becomes exposed. In another embodiment (not shown), the resist mask 92 may be formed as first described, with the opening corresponding to where the transition 922 meets the horizontal portion of the insulating layer 62. After anisotropically etching through a partial thickness of the insulating layer 62, a portion of the insulating layer 62 at a portion closer to the resist mask 92 is preferably etched using an isotropic etchant. For example, the insulating layer 62 may include a dopant concentration that increases as the insulating layer 62 becomes thicker or the stress or other physical characteristic is altered by changing the deposition conditions at the time of depositing the insulating layer 62. The use of different characteristics can cause other processing difficulties; however, the skilled artisan will appreciate whether the effects of the processing challenges and the risks they pose are acceptable or can be reduced or substantially eliminated.

Fig. 10 includes an illustration of an insulating layer 62 having a parabolic shape at a transition 1022 between regions 622 and 624. The transition 1022 between regions 622 and 624 can be formed using conventional or proprietary sidewall spacer formation techniques.

Fig. 7-10 include some examples of shapes for the transition between regions 622 and 624, although other shapes are possible. For example, a combination of different techniques may form a mixture of the described shapes. The shape can be tailored to create a transition (for a subsequently formed conductive layer) that allows for an acceptable electric field and step coverage.

The conductive layer 1104 is formed by depositing a conductive material on the insulating layer 62, including regions 622, 624, and 626, as shown in fig. 11. The thicker portion of the insulating layer 62 within the region 626 allows for a higher voltage differential between the conductive layer 1104 and the conductive structure 402 before the insulating layer 62 has dielectric breakdown. The thinner portion of insulating layer 62 within region 622 helps protect subsequently formed gate electrodes. The thickness of the conductive layer 1104 is in a range from about 0.05 microns to about 0.5 microns. The conductive layer 1104 comprises a conductive material, or can be made conductive, for example by doping. The conductive layer 1104 may comprise a doped semiconductor material (e.g., heavily doped amorphous silicon, polysilicon, etc.), a metal-containing material (refractory metal, refractory metal nitride, refractory metal silicide, etc.), or any combination thereof. In a specific embodiment, the conductive layer 1104 is a conductive electrode layer for forming a conductive electrode. The conductive layer 1104 may be patterned at this time to define conductive electrodes, or may be patterned at a later time in the process flow.

A set of layers is formed on the conductive layer 1104 of fig. 12. In an embodiment, the insulating layer 1206, insulating layer 1222, conductive layer 1224, and insulating layer 1226 may be deposited sequentially. Each of the insulating layers 1206, 1222, and 1226 can include an oxide, a nitride, an oxynitride, or any combination thereof.

Conductive layer 1224 includes a conductive material or may be made conductive, such as by doping. Conductive layer 1224 may comprise any material and may be formed using any of the techniques described with respect to conductive layer 1104. The conductive layers 1104 and 1224 may have the same composition or different compositions. The conductive layer 1224 can have a thickness ranging from about 0.1 microns to 0.9 microns. In a specific embodiment, conductive layer 1224 is a gate signal layer. Conductive layer 1224 may be patterned at this point to define gate signal lines, or may be patterned at a later time in the process flow.

In another specific embodiment, the insulating layer 1206 comprises a nitride having a thickness in a range of about 0.05 microns to about 0.2 microns. Insulating layers 1222 and 1226 include an oxide, insulating layer 1222 can have a thickness in a range of about 0.2 microns to about 0.9 microns, and insulating layer 1226 can have a thickness in a range of about 0.05 microns to about 0.2 microns. In yet another embodiment, the insulating layer 1226 includes a nitride. An anti-reflective layer may be incorporated into either the insulating layer or the conductive layer, or an anti-reflective layer (not shown) may be separately used. In other embodiments, more or fewer layers may be used, and the thicknesses described herein are merely exemplary and are not meant to limit the scope of the invention.

As shown in fig. 13, openings, such as opening 1302, are formed through layers 62, 1104, 1206, 1222, 1224, and 1226. The opening is formed such that a portion of the surface doped region 504 is located below the opening 1302. This portion allows portions of the surface doped region 504 to underlie portions of subsequently formed gate electrodes. Insulating sidewall spacers, such as insulating sidewall spacer 1402, are formed along the sides of an opening, such as opening 1302 of figure 14. The insulating sidewall spacers electrically insulate the conductive layer 1104 from a subsequently formed gate electrode. The insulating sidewall spacers 1402 may comprise an oxide, a nitride, an oxynitride, or any combination thereof, and the bottom of the insulating sidewall spacers 1402 have a width in a range of about 50nm to about 200 nm.

Fig. 15 includes an illustration of a workpiece after forming a gate dielectric layer 1502, a conductive layer 1506, and a well region 1504. Pad layer 106 is removed by etching and gate dielectric layer 1502 is formed on semiconductor layer 104. In a specific embodiment, gate dielectric layer 1502 comprises an oxide, nitride, oxynitride, or any combination thereof, and has a thickness ranging from about 5nm to about 100nm, and conductive layer 1506 overlies gate dielectric layer 1502. The conductive layer 1506 may be part of a subsequently formed gate electrode. The conductive layer 1506 may be conductive when deposited, or may be deposited as a high resistance layer (e.g., undoped polysilicon) and subsequently made conductive. The conductive layer 1506 may include a metal-containing material or a semiconductor-containing material. The thickness of the conductive layer 1506 is selected such that, from a top view, a substantially vertical edge of the conductive layer 1506 exposed within the opening 1302 is proximate to an edge of the surface doped region 504. In an embodiment, the conductive layer 1506 is deposited to a thickness of about 0.1 microns to about 0.15 microns.

After the conductive layer 1506 is formed, the semiconductor layer 104 can be doped to form a well region, such as the well region 1504 of fig. 15. The well region 1504 has a conductivity type opposite that of the surface doped region 504 and the underlying doped region 102. In an embodiment, boron dopants are introduced into semiconductor layer 104 through opening 1302, conductive layer 1506 and gate dielectric layer 1502 to provide p-type dopants to well region 1504. In one embodiment, the depth of the well region 1504 is deeper than the depth of the subsequently formed source region, and in another embodiment, the depth of the well region 1504 is at least about 0.5 microns. In a further embodiment, the depth of the well region 1504 is no greater than about 2.0 microns, while in yet another embodiment, the depth of the well region 1504 is no greater than about 1.5 microns. By way of example, the well region 1504 may be formed using two or more ion implantations. In a specific example, about 1.0X 10 is used¹³Atom/cm³Each ion implantation is performed with two implants having energies of about 25KeV and 50 KeV. In another embodiment, more or less ion implantations are performed in forming the well region. Different doses may be used at different energies, higher or lower doses may be used, higher or lower energies, or combinations thereof to meet the needs or desires of a particular application.

As shown in FIG. 16, additional conductive material is deposited onto conductive layer 1506 in order to form conductive layer 1606. The gate electrode will be formed from conductive layer 1606 and, thus, in the illustrated embodiment, the conductive layer is a gate dielectric layer. Conductive layer 1606 can comprise any of the materials previously described with respect to conductive layer 1506. Similar to the conductive layer 1506, the additional conductive material may be conductive as deposited, or may be deposited as a high impedance layer (e.g., undoped polysilicon) and subsequently made conductive. Between the conductive layer 1506 and the additional conductive material, they may have the same composition or different compositions. The thickness of conductive layer 1606, including conductive layer 1506 and additional conductive materials, has a thickness range of about 0.2 microns to 0.5 microns. In particular embodiments, the additional conductive material comprises polysilicon and may be doped with an n-type dopant during deposition or subsequent doping using ion implantation or other doping techniques.

Conductive layer 1606 is anisotropically etched to form a gate electrode, such as gate electrode 1706 of fig. 17. In the illustrated embodiment, the gate electrode 1706 is formed without using a mask and has a shape of a sidewall spacer. Etching of the gate electrode 1706 may be performed such that the insulating layer 1226 and the gate dielectric layer 1502 may be exposed. The etch may extend to expose a portion of the insulating sidewall spacers 1402. An insulating layer (not shown) may be thermally grown from the gate electrode 1706, or may be deposited over the workpiece. The thickness of the insulating layer may be in the range of about 10nm to about 30 nm.

Fig. 18 includes an illustration of the workpiece after forming conductive electrode 1862, gate signal line 1864, truncated insulating sidewall spacers 1802, source region 1804, and conductive fill material 1806 between gate signal line 1864 and gate electrode 1706. Although the operations performed to form the workpiece are described in a particular order, upon reading this specification, the skilled artisan will understand that the order can be altered, if needed or desired. In order to complete the workpiece according to the embodiment shown in fig. 18, a mask or a plurality of masks (not shown) may be used.

If conductive layers 1104 and 1224 are not already patterned, they may be patterned to form conductive electrodes and gate signal lines, such as conductive electrode 1862 and gate signal line 1864. Conductive electrode 1862 may be used to help reduce capacitive coupling between conductive structure 402 and any one or more of gate signal line 1864, gate electrode 1706, or gate signal line 1864 and gate electrode 1706. A gate signal line 1864 can be used to provide signals from control electrons (not shown) to the gate electrode 1706.

Source regions, such as source region 1804, can be formed using ion implantation. The source region 1804 is heavily doped and has an opposite conductivity type as compared to the well region 1504 and the same conductivity type as the surface doped region 504 and the underlying doped region 102. The portion of the well region 1504 located between the source region 1804 and the surface doped region 504 and under the gate electrode 1706 is a channel region 1822 for the power transistor being formed.

The insulating sidewall spacers 1402 may be truncated to form truncated insulating sidewall spacers 1802 by etching an upper portion of the sidewall spacers 1402 to remove portions of the insulating sidewall spacers 1402 between the conductive layer 1224 (gate signal layer) and the gate electrode 1706. The amount of insulating sidewall spacer 1402 removed is at least sufficient to allow conductive fill material 1806, when formed, to electrically connect conductive layer 1224 and gate electrode 1706, but not etch so much of insulating sidewall spacer 1402 to expose conductive layer 1104 (the conductive electrode layer) because gate electrode 1706 and conductive layer 1224 would be electrically connected to conductive layer 1104, which is undesirable. As in the illustrated embodiment, the etching is performed such that the uppermost surface of truncated insulating sidewall spacer 1802 is located near the interface between insulating layer 1222 and conductive layer 1224.

A conductive fill material 1806 is formed over the truncated insulating sidewall spacers 1802 to electrically connect the gate electrode 1706 to the conductive layer 1224. A conductive fill material 1806 may be selectively grown or deposited over substantially all of the workpiece and subsequently removed from areas outside the gap between gate electrode 1706 and gate signal line 1864. Exposed portions of insulating layer 1226 and gate dielectric layer 1502 are removed if needed or desired.

Fig. 19 includes an illustration of the workpiece after formation and patterning of an interlayer dielectric (ILD) layer 1902 to define contact openings, and after doping to form well contact regions. The ILD layer 1902 may comprise an oxide, a nitride, an oxynitride, or any combination thereof. The ILD layer 1902 may comprise a single film or a plurality of discrete films having a substantially constant or variable composition (e.g., high phosphorous content farther away from the semiconductor layer 104). An etch stop film, antireflective film, or combination may be used in or on the ILD layer 1902 to aid in processing. The ILD layer 1902 may be planarized to improve process margins during subsequent processing operations (e.g., lithography, subsequent polishing, or the like). A resistive layer 1904 is formed on the ILD layer 1902 and patterned to define resistive layer openings. An anisotropic etch is performed to define contact openings, such as contact opening 1922, that extend through the ILD layer 1902. Unlike many conventional contact etch operations, the etch continues to extend through the source region 1804 and end within the well region 1504. The etching may be performed as a timed etch or as an end point detection etch with a timed over etch. In a particular embodiment, the first endpoint may be detected when the source region 1804 is exposed, while the second endpoint may be detected by the presence of boron within the well region 1504. Well contact regions, such as well contact region 1924, may be formed by doping a bottom portion of a contact opening, such as contact opening 1922. The well contact regions 1924 may be implanted with dopants of the same conductivity type as the well region 1504 in which they are located. The well contact regions 1924 are heavily doped so that ohmic contacts can be subsequently formed. When the resistive layer 1904 is in place, an isotropic etch may be performed to expose the source regions, such as the uppermost surface of source regions 1804, as becomes more apparent with respect to the description of fig. 20. At this point in the process, a power transistor, such as the one shown in fig. 19, will be formed.

Fig. 20 includes an illustration of a substantially completed electronic device, including conductive plugs and terminals. More specifically, the conductive layer is formed along exposed surfaces of the workpiece and within contact openings, including contact opening 1922. The conductive layer may comprise a single film or multiple films. In an embodiment, the conductive layer includes a plurality of films, such as an adhesive film, a barrier film, and a conductive filler material. In particular embodiments, the adhesive film may include a high temperature resistant metal, such as titanium, tantalum, or the like; the barrier film may include a high temperature resistant metal nitride such as titanium nitride, tantalum nitride, or the like, or a high temperature resistant metal semiconductor nitride such as TaSiN; and the conductive fill material may comprise tungsten. The number of films and the composition of these films are selected based on electrical properties, subsequent thermal cycling temperatures, other criteria, or any combination thereof. After reading this specification, the skilled person will be able to determine the composition of the conductive layer to meet the needs or desires of a particular application. Portions of the conductive layer overlying the ILD layer 1902 are removed to form conductive plugs, such as conductive plug 2022 within contact opening 1922.

A conductive layer may be deposited to form the source terminal 2024 and the drain terminal 2026. The conductive layers may each comprise a single membrane or a plurality of separate membranes. Exemplary materials include aluminum, tungsten, copper, gold, or the like. Each conductive layer may or may not be patterned to form a source terminal 2024 or a drain terminal 2026, as shown in fig. 20. In a specific embodiment, the drain terminal 2026 may be part of a backside contact to a substrate including the underlying doped region 102. In another embodiment, the conductive layer used to form the source terminal 2024 may be patterned to also form a gate terminal (not shown) to be connected to the gate signal line 1864. In the illustrated embodiment, no conductive plug extends to the vertically oriented conductive region, and in particular, conductive structure 402.

The electronic device may include many other power transistors that are substantially equal to the power transistor shown in fig. 20. The power transistors are connected in parallel to provide a sufficiently effective channel width of the electronic device that can support the relatively high currents used during normal operation of the electronic device.

Conductive electrode 1862 may be used to protect gate electrode 1706 from the electric field generated by conductive structure 402 when the electronic device is operating. Accordingly, conductive electrode 1862 helps reduce capacitive coupling between conductive structure 402 and each of gate electrode 1706 and gate signal line 1864. This protection may allow the transistor to operate at higher switching speeds.

The electronic device may be designed to have a maximum source-drain voltage difference of 20V or higher, for example 30V or 50V. The voltage of the conductive structure 402 may be equal to V_DSubstantially the same, and thus a relatively high voltage difference may exist between conductive structure 402 and conductive electrode 1862. In a specific embodiment, an electronic device can have conductive electrode 1862 at about V_SOr about 0V, and the conductive structure 402 is at about V_DOr a normal operating state of about 30V. If the insulating layer 62 is designed to be substantially the same thickness when present in the fabricated form of the electronic device, undesirable effects may occur. If the insulating layer 62 is relatively and uniformly thin, the thinner thickness helps to protect the gate electrode 1706 and improve switchingChanging the speed; however, the relatively thin insulating layer 62 may not be able to withstand the electric field between the conductive structure 402 and the conductive electrode 1862. Additional benefits of the relatively thin insulating layer 62 include better depletion of the surface doped region 504 under normal reverse bias operating conditions and a corresponding reduction in potential near the junction between the surface doped region 504 and the channel region 1822, enabling control of a shorter effective channel length without undesirable electrical breakdown that results in high leakage current. If insulating layer 62 is relatively and uniformly thick, the thicker thickness helps to withstand the electric field between conductive structure 402 and conductive electrode 1862; however, the relatively thick insulating layer 62 is not conducive to protecting the gate electrode 1706 and switching speed. A further benefit of having a conductive electrode 1862 overlying insulating layer 62 that is thinner in region 622 and thicker in region 626 is that it can be used to shift the location of avalanche current generation away from channel 1822 toward vertical conductive structure 402. By moving this source of hot carriers away from the channel region of the transistor, the robustness and stability of the device can be improved.

By having insulating layer 62 with different thicknesses between region 622 and region 626, better protection of the thinner insulating layer may be achieved while still allowing for an acceptable dielectric breakdown voltage with respect to the insulating layer between conductive structure 402 and conductive electrode 1862. When fully depleted under normal reverse bias operating conditions, the depleted charge in the surface doped region 504 allows the voltage within the surface doped region 504 to decrease from a higher voltage at a location closer to the conductive structure 402 to a lower voltage at another location closer to the channel region 1822, the channel region 1822 being located between the surface doped region 504 and the source region 1804. The lower voltage need not be as thick as the insulating layer to protect the dielectric breakdown. Thus, the thickness of insulating layer 62 within region 622 may be thinner, while the thickness of insulating layer 62 within region 626 may be thicker. The thickness of insulating layer 62 within region 624 may be the same as the thickness of the insulating layer within regions 622 and 626, or may have a thickness between the thicknesses of insulating layer 62 within regions 622 and 624.

Other embodiments may be used, if needed or desired. In another embodiment (not shown), a patch may be usedPay zones to help reduce R_DSON. A compensation region is disposed adjacent to the surface doped region 504. During normal operating conditions, surface doped region 504 may be self-consumed by conductive electrode 1862 and self-consumed by the compensation region simultaneously. This may allow the peak dopant concentration in the surface doped region 504 to increase and result in the same Breakdown Voltage (BV)_DSS) Lower R of rank_DSON. The compensation region has an opposite conductivity type from the surface doped region 504 and the underlying doped region 102. In a specific embodiment, the dopant concentration of the compensation region is no greater than about 2 x 10¹⁷Atom/cm³Or in another embodiment, the dopant concentration is no greater than about 5 x 10¹⁶Atom/cm³。

The transistor as illustrated and described herein may be an NMOS transistor in which the source region 1804, the surface doped region 504, the sidewall doped region 404, and the underlying doped region 102 are all n-type doped, while the channel region 1822 is p-type doped. In another embodiment, the transistor may be a PMOS transistor by reversing the conductivity type of the previously described regions.

Many different aspects and embodiments are possible. Some of these aspects and embodiments are described below. After reading this specification, skilled artisans will appreciate that these aspects and embodiments are exemplary only and do not limit the scope of the invention.

In a first aspect, an electronic device can include a semiconductor layer having a major surface, a channel region, a conductive electrode, and an insulating layer. An insulating layer can be positioned between the major surface and the conductive electrode, wherein the insulating layer has a first region and a second region, the first region being thinner than the second region, and the channel region being closer to the first region than the second region.

In an embodiment of the first aspect, the second zone comprises at least one more membrane than the first zone. In another embodiment, the electronic device further comprises a source region disposed adjacent to the channel region; a conductive structure located within the trench of the semiconductor layer; and a surface doped region spaced apart from the underlying doped region. The channel region is closer to the surface doped region than to the conductive structure, and the first region of the insulating layer covers the surface doped region; and a second region of the insulating layer overlies the conductive structure. In a specific embodiment, the electronic device further comprises a drain and is designed to operate normally at a source-drain voltage difference of at least about 20V. In another embodiment, the source and the conducting structure are designed to operate normally at a source-conducting structure voltage difference of at least about 20V. In yet another embodiment, the surface doped region extends from about 0.2 microns to about 3.0 microns from the conductive structure toward the source region along the major surface of the semiconductor layer.

In a second aspect, an electronic device can include a semiconductor layer having a major surface and a trench extending therefrom, a conductive structure within the trench, and a gate electrode overlying the semiconductor layer. The electronic device may further include an insulating layer including a first region and a second region, wherein the second region is thicker than the first region, the gate electrode is closer to the first region than the second region, and the second region overlies the conductive structure. The electronic device may further include a conductive electrode and a conductive structure overlying the first and second regions of the insulating layer.

In an embodiment of the second aspect, the electronic device further comprises a gate signal line overlying the major surface of the semiconductor layer and the conductive electrode, wherein the gate electrode does not overlie the conductive electrode and the conductive electrode is arranged to substantially laterally compress when the electronic device is in a normal operating state. In a specific embodiment, a portion of the conductive electrode is disposed adjacent the gate electrode and has a first surface and a second surface opposite the first surface, the major surface is closer to the first surface than to the second surface, and each of the first surface and the second surface of the conductive electrode is located at a height between a lowermost point and an uppermost point of the gate electrode within an area occupied by the transistor.

In another embodiment of the second aspect, the electronic device further includes a source region disposed adjacent to the gate electrode, a channel region disposed adjacent to the source region and the gate electrode, a conductive structure disposed within the trench of the semiconductor layer, an underlying doped region disposed below the semiconductor layer and the conductive structure, and a surface doped region spaced apart from the underlying doped region. In this embodiment, the channel region is closer to the surface doped region than the conductive structure, the first region of the insulating layer overlies the surface doped region, and the second region of the insulating layer overlies the conductive structure. In a specific embodiment, the electronic device further comprises a drain, wherein the electronic device comprises a transistor comprising a source, a gate electrode, and a drain, and the transistor is designed to operate normally at a source-drain voltage difference of at least about 20V. In another embodiment, an electronic device includes a transistor, the transistor including a source and a gate electrode, and the transistor is designed to operate normally at a source-conducting structure voltage difference of at least about 20V. In yet another embodiment, the surface doped region extends from about 0.2 microns to about 3.0 microns along the major surface from the conductive structure toward the source region.

In a third aspect, a method of forming an electronic device can include providing a workpiece comprising a substrate, including an underlying doped region and a semiconductor layer overlying the underlying doped region, wherein the semiconductor layer has a major surface spaced apart from the underlying doped region. The method may further include forming an insulating layer on the semiconductor layer, wherein the insulating layer has a first region and a second region, and the first region is thinner than the second region, forming a conductive electrode on the first region and the second region of the insulating layer, and forming a source region closer to the first region of the insulating layer than the second region of the insulating layer.

In an embodiment of the third aspect, forming the insulating layer includes depositing an insulating layer, forming a mask defining an opening overlying a first region of the insulating layer, and isotropically etching the insulating layer within the first region. In another embodiment, forming the insulating layer includes depositing an insulating layer, patterning the insulating layer to define an opening overlying the first region of the insulating layer, and forming an insulating sidewall spacer within the opening. In yet another embodiment, forming the insulating layer includes depositing the insulating layer, forming a mask defining an opening overlying the first region of the insulating layer, and simultaneously etching the insulating layer and the exposed portion of the mask during at least one location time such that the insulating layer has a substantially linear slope after the simultaneous etching, as viewed in cross-section. In yet another embodiment, forming the insulating layer includes depositing the insulating layer, forming a mask defining an opening overlying the first region of the insulating layer, anisotropically etching the insulating layer beneath the opening to etch through a portion of the thickness of the insulating layer, isotropically etching a portion of the mask after anisotropically etching the insulating layer to widen the opening in the mask, and anisotropically etching the insulating layer beneath the widened opening after isotropically etching the portion of the mask.

In a further embodiment of the third aspect, the method further includes forming a trench in the semiconductor layer, wherein the trench extends from the major surface toward the underlying doped region, forming a conductive structure located within the trench, and forming the surface doped region spaced apart from the underlying doped region, wherein the first region of the insulating layer overlies the surface doped region and the second region of the insulating layer overlies the conductive structure. In a specific embodiment, the transistor is designed to operate normally at a source-conducting structure voltage difference of at least about 20V. In a more specific embodiment, the surface doped region extends from about 0.2 microns to about 3.0 microns along the major surface from the conductive structure toward the source region. In another embodiment, the method further includes forming a gate signal line on the conductive electrode, and forming a gate electrode on the major surface of the semiconductor layer, wherein the gate electrode does not overlie the conductive electrode. In this embodiment, a conductive electrode is located between the gate signal line and each of the conductive structure and the surface doped region, and in a fabricated form of the electronic device, the conductive electrode is configured to be substantially constant voltage when the electronic device is in a normal operating state. In a more specific embodiment, the transistor is designed to operate normally at a source-drain voltage difference of at least about 20V.

It is noted that not all of the activities described in the foregoing summary or embodiments are required, that a portion of a particular activity may not be required, and that one or more additional activities may be performed in addition to those described. Further, the order in which activities are listed are not necessarily the order in which they are performed.

Certain features that are, for clarity, described herein in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features that are, for brevity, described in the context of a single embodiment, may also be provided separately or in any subcombination. Moreover, reference to values expressed as ranges includes each and every value within that range.

Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. The benefits, advantages, solutions to problems, and any feature(s) that may cause any benefit, advantage, or solution to occur or become more pronounced, however, are not to be construed as a critical, required, or essential feature or feature of any or all the claims.

It is to be understood that certain features that are, for clarity, described herein in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features that are, for brevity, described in the context of a single embodiment, may also be provided separately or in any subcombination. Moreover, reference to values expressed as ranges includes each and every value within that range.

The illustrations and descriptions of the embodiments described herein are intended to provide a general understanding of the structure of the various embodiments. This description and illustration is not intended to be an exhaustive or comprehensive description of all the elements and features of apparatus and systems that utilize the structures or methods described herein. Different embodiments may also be provided in combination in a single embodiment, but rather, different features that are, for brevity, described in the context of a single embodiment, may also be provided separately or in any subcombination. Moreover, reference to values expressed as ranges includes each and every value within that range. Many other embodiments will be apparent to the skilled person only after reading this specification. Other embodiments may be utilized and derived from the disclosure, such that structural substitutions, logical substitutions, or other changes may be made without departing from the scope of the disclosure. Accordingly, this disclosure is to be considered as illustrative and not restrictive.

Claims (10)

1. An electronic device, comprising:

a semiconductor layer having a major surface and a trench in the semiconductor layer, the trench extending from the major surface;

a channel region;

a conductive electrode overlying and spaced apart from and electrically insulated from the conductive material located inside the trench, wherein the conductive electrode is disposed between the semiconductor layer and a gate signal line; and

an insulating layer between the major surface and the conductive electrode,

wherein the insulating layer has a first region and a second region, the first region being thinner than the second region, and the channel region being closer to the first region than to the second region.

2. The electronic device of claim 1, further comprising:

a source region disposed adjacent to the channel region;

a conductive structure located within a trench in the semiconductor layer; and

a surface doped region spaced apart from the following doped region, wherein:

the channel region is closer to the surface doped region than to the conductive structure;

the first region of the insulating layer overlies the surface doped region; and is

The second region of the insulating layer overlies the conductive structure.

3. The electronic device of claim 1, further comprising:

a conductive structure located within the slot; and

a gate electrode overlying the semiconductor layer,

wherein the insulating layer is spaced apart from the gate electrode, the gate electrode is closer to the first region than to the second region, the second region overlies the conductive structure, an

The conductive electrode is disposed between the first and second regions of the insulating layer and the gate signal line.

4. The electronic device of claim 3, further comprising:

a source region positioned adjacent to the gate electrode;

a channel region positioned adjacent to the source region and the gate electrode;

a conductive structure located within a trench in the semiconductor layer;

an underlying doped region underlying the semiconductor layer and the conductive structure; and

a surface doped region spaced apart from the underlying doped region, wherein:

the channel region is closer to the surface doped region than the conductive structure;

the first region of the insulating layer overlies the surface doped region; and is

The second region of the insulating layer overlies the conductive structure.

5. The electronic device of claim 4, wherein the surface doped region extends from about 0.2 microns to about 3.0 microns along the major surface from the conductive structure toward the source region.

6. An electronic device as claimed in claim 1, 2, 4 or 5, wherein a transistor comprises the channel region and is designed to operate normally at a source-drain voltage difference of at least about 20V.

7. A method of forming an electronic device comprising the steps of:

providing a workpiece comprising a substrate, comprising an underlying doped region, a semiconductor layer overlying the underlying doped region, the semiconductor layer comprising a surface region;

removing a portion of the semiconductor layer to form a trench extending from a major surface of the semiconductor layer;

forming an insulating layer over the semiconductor layer, wherein the insulating layer has a first region and a second region, and the first region is thinner than the second region;

forming a conductive electrode over the first and second regions of the insulating layer,

wherein:

the conductive electrode overlies and is spaced apart and electrically insulated from the conductive material located inside the slot,

the conductive electrode is disposed between the semiconductor layer and a gate signal line; and is

The insulating layer is located between the major surface and the conductive electrode; and forming a gate electrode after forming the conductive electrode, wherein:

the insulating layer is spaced apart from the gate electrode; and is

The gate electrode overlies a channel region that is closer to the first region than to the second region.

8. The method of claim 7, wherein the step of forming the insulating layer comprises:

depositing the insulating layer;

forming a mask defining an opening overlying the first region of the insulating layer; and

isotropically etching the insulating layer within the first region.

9. The method of claim 7, wherein the step of forming the insulating layer comprises:

depositing an insulating layer;

patterning the insulating layer to define an opening overlying the first region of the insulating layer; and

insulating sidewall spacers are formed within the opening.

10. The method of claim 7, wherein the step of forming the insulating layer comprises:

depositing the insulating layer;

forming a mask defining an opening overlying the first region of the insulating layer; and

the insulating layer and the exposed portions of the mask are simultaneously etched during at least one location instant such that, from a cross-sectional view, the insulating layer has a substantially linear slope after the simultaneous etching.