HK1148859A - Adapting word line pulse widths in memory systems - Google Patents

Abstract

Systems, circuits and methods for adapting word line (WL) pulse widths used in memory systems are disclosed. One embodiment of the invention is directed to an apparatus comprising a memory system. The memory system comprises: a memory operating according to a wordline (WL) pulse with an associated WL pulse width; a built-in self-test (BIST) unit that interfaces with the memory, the BIST unit being configured to run a self-test of the internal functionality of the memory and provide a signal indicating if the memory passed or failed the self-test; and an adaptive WL control circuit that interfaces with the BIST unit and the memory, the adaptive WL control circuit being configured to adjust the WL pulse width of the memory based on the signal provided by the BIST unit.

Description

Adapting word line pulse width in a memory system

Claiming priority pursuant to 35U.S.C. § 119

The present patent application claims priority from provisional application No. 61/014,257 entitled APPARATUS AND METHOD FOR ADAPTING wordline PULSE width IN a MEMORY system (APPARATUS AND METHOD FOR ADAPTING WORD LINE PULSE width IN MEMORY system), filed on 12, month 17, 2007, which is assigned to the present assignee AND expressly incorporated herein by reference.

Technical Field

Embodiments of the invention relate to memory systems. More particularly, embodiments of the present invention relate to adapting word line pulse widths used in memory systems.

Background

As CMOS technology continues to scale to smaller dimensions, process variations due to process control limitations as well as fundamental physical limitations tend to increase. Embedded memories, such as embedded SRAM, are particularly susceptible to large process variations due to aggressive design rules and their small size compared to other digital logic. To cope with this large increase in process variation, memory circuit designers often use overly conservative design approaches in order to achieve high parameter and functional yield.

For example, a designer may trade-off performance (e.g., speed) and/or power consumption for yield by designing a particular Integrated Circuit (IC) to function over a wide range of process variations, including both local (within each IC) and global (between ICs) variations. This results in a larger percentage of ICs produced being operable (i.e., increased yield), but the sacrifice in performance and/or power consumption may be greater in those ICs that do not experience the full range of process variations. Due to the statistical nature of process variations, the actual number of ICs experiencing greater performance and/or power consumption degradation can be quite high.

Fig. 1 is a schematic diagram illustrating a conventional memory system 100. 100 includes a memory 110, a built-in self test (BIST) circuit 120, and a pulse width setting module 130. The BIST 120 tests all or a portion of the internal functionality of the memory 110. The pulse width setting module 130 sets the WL pulse width for the read/write cycle in the memory 110. The pulse width setting module 130 may receive an external n-bit code indicating a desired WL pulse width from a system controller or the like.

As is well known in the art, the WL pulse width determines the length of time required for each read or write operation to complete, which directly affects both the performance and power consumption of the memory. In general, an increased WL pulse width ensures more accurate read/write operations, but the operation is slower and requires more power. In contrast, the reduced WL pulse width may be less accurate (especially over a wider range of process variations), but may operate faster and require less power. Thus, setting the desired WL pulse width is often a design tradeoff between memory performance and yield.

One of the conventional post-fabrication techniques used to optimize memory performance and increase yield when producing a batch of ICs implementing the memory system 100 is to use post-silicon (post-silicon) digital trimming. Typically, an external digital code for controlling the WL pulse width (WL pulse width code) is set to achieve a target yield for a certain memory. Measurements are performed on a large sample of the memory and yields are determined for different WL pulse widths. The optimal WL pulse width is determined based on the target yield and is fixed for all memories.

This approach has several limitations. One limitation is that the WL pulse width is fixed for all ICs based on extreme process variations. As discussed above, many, if not most, ICs do not experience such extreme process variations. Thus, a large performance penalty and additional power consumption can affect a large portion of the ICs produced. Another limitation is that a large test time is required to measure the large sample size required to accurately determine the value of the optimal WL pulse width for a given target yield.

Disclosure of Invention

Exemplary embodiments of the present invention are directed to systems, circuits, and methods for adapting WL pulse width for use in a memory system.

One embodiment of the present invention is directed to an apparatus comprising: a Word Line (WL) pulse having an associated WL pulse width; a built-in self test (BIST) unit that interfaces with a memory, the BIST unit configured to run a self test of internal functionality of the memory and provide a signal indicating whether the memory passes or fails the self test; and an adaptive WL control circuit interfacing with the BIST unit and the memory, the adaptive WL control circuit configured to adjust the WL pulse width of the memory based on the signal provided by the BIST unit.

Another embodiment of the invention is directed to a method of adjusting Word Line (WL) pulse width in a memory system that includes a memory that operates according to WL pulses. The method comprises the following steps: performing a self-test on the memory system to test internal functionality of the memory at a current WL pulse width; and adjusting, using an on-chip adaptive WL control circuit, a WL pulse width of the memory based on a result of the self-test.

Another embodiment of the invention is directed to an apparatus for adjusting Word Line (WL) pulse width in a memory system that includes a memory that operates according to WL pulses. The apparatus comprises: means for performing a self-test on the memory system to test internal functionality of the memory at a current WL pulse width; and an on-chip means for adjusting a WL pulse width of the memory based on a result of the self-test.

Another embodiment of the invention is directed to a computer-readable medium comprising a set of instructions executable by a processor to adjust a Word Line (WL) pulse width in a memory system comprising a memory operating in accordance with a WL pulse. The computer-readable medium comprises: a first set of instructions executable by the processor to perform a self-test on the memory system to test internal functionality of the memory at a current WL pulse width; and a second set of instructions executable by the processor to adjust a WL pulse width of the memory based on a result of the self-test.

Drawings

The accompanying drawings are presented to aid in the description of embodiments of the invention and are provided solely for illustration of the embodiments and not limitation thereof.

Fig. 1 is a schematic diagram illustrating a conventional memory system reading/writing data according to Word Line (WL) pulses.

Fig. 3 is a flow chart illustrating the operation of the adaptive WL control loop.

FIG. 4 illustrates an example implementation of the pulse width controller of FIG. 2 using an n-bit counter.

FIG. 5 shows a block diagram of a design of a wireless communication device in a wireless communication system.

Detailed Description

Aspects of embodiments of the invention are disclosed in the following description and related drawings directed to specific embodiments of the invention. Alternative embodiments may be devised without departing from the scope of the invention. Additionally, well-known elements of the invention will not be described in detail or will be omitted so as not to obscure the relevant details of the invention.

The word "exemplary" is used herein to mean "serving as an example, instance, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term "embodiments of the invention" does not require that all embodiments of the invention include the discussed feature, advantage or mode of operation.

As discussed in the background, conventional approaches to optimizing Word Line (WL) pulse widths for memory systems in a batch of given Integrated Circuits (ICs) allow for a wide range of process variations by compromising performance and/or power consumption in individual ICs to increase overall yield. However, this approach is often too conservative for many, if not most, memory systems in the IC. To increase performance and reduce power consumption while still maintaining and potentially increasing overall yield, embodiments of the present invention adjust the WL pulse width individually for each IC. While conventional approaches limit the WL pulse width in each IC to a conservative value based on an average measurement for a group of ICs, embodiments of the present invention allow the WL pulse width to be individually adapted to each IC in order to optimize performance and power consumption in view of the actual process variations experienced by the IC.

FIG. 2 illustrates a memory system 200 according to an embodiment of the invention. The memory system 200 includes the memory 210, built-in self test (BIST), described in the background. However, the memory system 200 adds an adaptive WL pulse control module 240, a pulse width controller 250, a decoder 260, and a code reprogramming module 270 that interface with pre-existing conventional memory system infrastructure (including the memory 210, the BIST220, and the pulse width setting module 230) to form an adaptive WL control loop 280, which adaptive WL control loop 280 individually controls the WL pulse width of each memory in one or more ICs, as will be described in more detail below.

The adaptive WL pulse control module 240 interfaces directly with the BIST220, the pulse width controller 250 and the code reprogramming module 270 using a series of control signals. As illustrated in FIG. 2, the adaptive WL pulse control module 240 receives a load _ code signal, an enable signal, and a CLK signal from a system controller or the like (not shown). The load _ code signal indicates that the initial WL pulse width code is to be loaded. The enable signal instructs the adaptive WL pulse control module 240 to start the optimal WL pulse width determination procedure. The CLK signal simply provides the system clock to the adaptive WL pulse control module 240.

The adaptive WL pulse control module 240 sends the en _ BIST signal to the BIST220, instructing the BIST220 to perform a self-test on the memory 210. en _ BIST can be implemented simply as a single bit, with, for example, the "1" instruction BIST220 performing self-tests and the "0" instruction BIST220 not performing self-tests, or by using a finer scheme. In response, the BIST220 sends a pass (pass) signal and a done (done) signal to the adaptive WL pulse control module 240. The pass signal indicates whether memory 210 passed the self test (i.e., memory 210 operates satisfactorily) or whether memory 210 failed the self test (i.e., memory 210 does not operate satisfactorily). The pass signal may simply be implemented as a single bit, with, for example, "1" indicating "pass" and "0" indicating "fail," or by using a more elaborate scheme. The done signal indicates that BIST220 has completed performing a self-test on memory 210. The completion signal may simply be implemented as a single bit, with, for example, "1" indicating that the self test is complete and "0" indicating that the self test is not complete, or by using a more elaborate scheme.

The adaptive WL pulse control module 240 communicates with the pulse width controller 250 by sending a load signal and up/down signals. The load signal instructs the pulse width controller 250 to load the initial WL pulse width code. The initial WL pulse width code may be provided to the pulse width controller 250 by, for example, the system controller. The initial WL pulse width code value may be determined based on the WL pulse width code being signaled up/down to increase or decrease the WL pulse width code from an initial value because the initial WL pulse width code may indicate a WL pulse width that may not be initially optimal (i.e., too large or too small). The up/down signal may simply be implemented as a single bit, where, for example, a "1" instructs the pulse width controller 250 to increase the WL pulse width code value and a "0" instructs the pulse width controller 250 to decrease the WL pulse width code value, or by using a finer scheme. In addition, the adaptive WL pulse control module 240 also provides a clock clk _ cout signal to the pulse width controller 250. The CLK _ cout signal may be, for example, a down-converted version of the CLK signal to facilitate the pulse width controller 250 to increment or decrement the WL pulse width code.

The adaptive WL pulse control module 240 also receives an overload signal from the pulse width controller 250 indicating whether the WL pulse width code has increased to its maximum value or decreased to its minimum value. The overload signal can be implemented simply as a single bit, where, for example, a "1" indicates that the maximum or minimum value has been reached and a "0" indicates that the maximum or minimum value has not been reached, or by using a more elaborate scheme, such as a two-bit signal, where a "10" indicates that the maximum value has been reached, a "01" indicates that the minimum value has been reached, and a "00" indicates that the maximum or minimum value has not been reached.

When the final code has been selected, the pulse width controller 250 outputs the final code to the code reprogramming module 270, and the adaptive WL pulse control module 240 sends a write _ code signal to the code reprogramming module 270, instructing the code reprogramming module 270 to program the optimized final WL pulse width code into the memory contained therein. The write _ code may be implemented simply as a single bit, with, for example, a "1" instruction code reprogramming module 270 programming the final code and a "0" instruction code reprogramming module 270 not programming the final code, or by using a more elaborate scheme. The code reprogramming module 270 allows dynamic real-time reprogramming of the memory system 100 and allows permanent storage of the optimized final WL pulse width code. In some applications, the memory in code reprogramming module 270 may be non-volatile memory capable of storing the optimized final WL pulse code indefinitely. For example, the code reprogramming module 270 may be implemented in eFUSE memory or any other well known programmable non-volatile storage. However, in other applications where it is applicable, volatile memory may be used.

Decoder 260 receives the WL pulse width code from pulse width controller 250 during the WL pulse width determination or from code reprogramming module 270 once the WL pulse width code has been finalized. Because the WL pulse width code may not necessarily have a monotonic relationship with the actual WL pulse width, the decoder 260 is used to map or decode each WL pulse width code such that the WL pulse width output from the pulse width setting module 230 monotonically increases/decreases relative to the previously decoded WL pulse width code. The pulse width setting module 230, in turn, sets the WL pulse width for reading from memory 210 or writing to memory 210.

One of ordinary skill in the art will appreciate that the decoder 260 allows the adaptive WL control loop 280 to search for potential WL pulse width codes to obtain optimized codes without tracking which codes have been searched by searching in a single increase/decrease direction. However, the use of decoder 260 is not intended to limit the scope of various embodiments of the present invention, which may instead use memory or the like to track which codes have been tested.

FIG. 3 is a flow chart illustrating the operation of the adaptive WL control loop according to an embodiment of the present invention. Operation to optimize the WL pulse width of the memory system 200 will now be described below with reference to fig. 2 and 3 and with reference to the control signals described above.

According to an embodiment of the present invention, each IC independently sets its own WL pulse width. This may be done, for example, at initial power up or whenever needed. For example, well-known lifetime-dependent memory degradation effects (e.g., hot carrier effects, Negative Bias Temperature Instability (NBTI) effects, etc.) may reduce performance of the memory over time. Therefore, it may be desirable to adjust the WL pulse width of a memory according to embodiments of the present invention not only initially but also after optimizing memory operation in view of degraded IC characteristics.

Once the system controller enables the adaptive WL control loop 280 with the enable signal, it instructs the adaptive WL pulse control module 240 to load the initial WL pulse width code with the load _ code signal. The adaptive WL pulse control module 240, in turn, uses the load signal to instruct the pulse width controller 250 to load the initial WL pulse width code. The pulse width controller 250 outputs an initial WL pulse width code to the decoder 260, and the decoder 260 then sets the WL pulse width to the initial value.

Once the WL pulse width is set, the adaptive WL pulse control module 240 uses the en _ BIST signal to instruct the BIST220 to perform a self-test on the memory 210 (block 310). The BIST220 performs a self-test and indicates completion to the adaptive WL pulse control module 240 using a completion signal. The BIST220 also passes the results of the self-test to the adaptive WL pulse control module 240 using the pass signal (block 320).

If the pass signal indicates a pass, then the IC meets at least the minimum design specifications. Thus, the adaptive WL pulse control module 240 will attempt to increase the performance and reduce the power consumption of this particular IC. To do so, the adaptive WL pulse control module 240 enters an optimization mode (block group 330). In this mode, the adaptive WL pulse control module 240 instructs the pulse width controller 250 to decrease the WL pulse width code using the up/down signal (block 332). Reducing the WL pulse width code and correspondingly reducing the WL pulse width may allow the IC to function with increased performance and reduced power consumption. The current WL pulse width is applied to the memory 210 in accordance with the current WL pulse width code in the manner described above for the initial WL pulse width code.

Once the WL pulse width has been updated, the adaptive WL pulse control module 240 uses the en _ best signal to instruct the BIST220 to perform a subsequent self-test on the memory 210 to test whether the memory 210 is operating at the current WL pulse width value (block 334). As before, the BIST220 performs a self-test and indicates completion to the adaptive WL pulse control module 240 using a completion signal. The BIST220 also passes the results of the self-test to the adaptive WL pulse control module 240 using the pass signal (block 336). If the memory 210 passes this subsequent self-test, it will still operate even under the increased functional requirements caused by the reduced WL pulse width. Adaptive WL pulse control module 240 will then attempt to further increase performance and reduce power consumption by iteratively repeating the above operations (blocks 332-336) until memory 210 fails a subsequent self-test.

The operational limits of memory 210 have been reached once the subsequent self-test indication fails. Thus, the adaptive WL pulse control module 240 instructs the code reprogramming module 270 to program the last WL pulse width code that caused the self-test to pass (i.e., the previous WL pulse width code in this mode) using the write _ code signal (block 338). If the minimum WL pulse width code is reached, the signal is overloaded. If the memory 210 still passes subsequent self-tests with the minimum WL pulse width, then the minimum WL pulse width code will be programmed into the code reprogramming module 270.

Thus, by entering the optimization mode, an adaptive WL control loop according to an embodiment of the present invention can potentially increase the performance of a particular IC and reduce its power consumption.

Returning now to the initial BIST pass/fail (block 320), if the pass signal indicates a fail, then the IC does not meet the minimum design specifications. In the conventional memory system 100, this would mean that this particular IC is defective and would have to be discarded. However, this particular IC can still be remedied according to embodiments of the present invention. For example, BIST fails to mitigate by potentially increasing read margin (i.e., increasing WL pulse width). To do so, the adaptive WL pulse control module 240 enters a recovery mode (block group 340). In this mode, the adaptive WL pulse control module 240 instructs the pulse width controller 250 to increase the WL pulse width code using the up/down signal (block 341). Increasing the WL pulse width code and accordingly the WL pulse width may allow the IC to function stably, even at reduced performance and higher power consumption. The current WL pulse width is applied to the memory 210 in accordance with the current WL pulse width code in the manner described above for the initial WL pulse width code.

Once the WL pulse width has been updated, the adaptive WL pulse control module 240 uses the en _ best signal to instruct the BIST220 to perform a subsequent self-test on the memory 210 to test whether the memory 210 is operating at the current WL pulse width value (block 343). As before, the BIST220 performs a self-test and indicates completion to the adaptive WL pulse control module 240 using a completion signal. The BIST220 also passes the results of the self-test to the adaptive WL pulse control module 240 using the pass signal (block 345). If memory 210 fails this subsequent self-test, it does not operate even under the reduced functional requirements caused by the increased WL pulse width. As long as the maximum allowable WL pulse width is not reached (block 347), the adaptive WL pulse control module 240 will then attempt to reduce the functional requirements even further by iteratively repeating the above operations (blocks 341-345) until the memory 210 passes subsequent self-tests.

Once the subsequent self-test indicates a pass, the operational limits instruct the code reprogramming module 270 to program the last WL pulse width code that caused the pass self-test (i.e., the current WL pulse width code in this mode) (block 350) using the write _ code signal. If the maximum WL pulse width code is reached and the memory 210 has not passed subsequent self-tests, the pulse width controller 250 will alert the adaptive WL pulse control module 240 of this condition using an overload signal (block 347). In this case, this particular memory fails to recover and is deemed inoperable (block 349).

Thus, by entering the recovery mode, a memory system according to embodiments of the present invention can potentially increase yield by recovering ICs that do not meet the minimum original design requirements, but are still capable of functioning under reduced requirements that provide some acceptable level of operation.

Once the final WL pulse width code is programmed, the system enable signal may deactivate and disable the adaptive WL control loop 280. At this point, the optimized final WL pulse width code is stored in code reprogramming module 270 and passed to decoder 260 for use in memory 210.

One of ordinary skill in the art will appreciate that the incremental search algorithm described above is shown for illustrative purposes and is not intended to limit the scope of search algorithms that may be implemented in accordance with various embodiments of the present invention. For example, a tree search algorithm, a random search algorithm, or other search algorithms well known in the art may also be used in accordance with various embodiments of the present invention.

FIG. 4 illustrates an example implementation of the pulse width controller of FIG. 2 using an n-bit counter.

As shown, the n-bit counter 410 receives a load signal, an up/down signal, and a clk _ cout signal. These control signals may be output from the adaptive WL pulse control module 240, as described above with reference to fig. 2. The n-bit counter 410 also receives an n-bit initial WL pulse width code from a system controller or the like. The n-bit counter 410 outputs an n-bit current WL pulse width code and an overload signal. As described above with reference to fig. 2, the overload signal may be received by the adaptive WL pulse control module 240 and the n-bit current WL pulse width code may be received by the decoder 260 and/or the code reprogramming module 270.

The N-bit counter 410 includes circuitry for incrementing and decrementing the initial WL pulse width code according to the operation described above with reference to the pulse width code values b0 through bn into a series of bit storage devices (e.g., flip-flops). When an up/down signal is received, the n-bit counter 410 increments or decrements the stored WL pulse width code according to the clk _ cout signal using a counter circuit, which is well known in the art and further description thereof will be omitted herein.

Once the current WL pulse width code has been updated, it is output as a current WL pulse width code value Q0-Qn that may be used to adjust the WL pulse width, etc. The count operation also tracks any overflow bits resulting from the calculation. The overflow bit is output using the overload signal to indicate that the maximum or minimum value has been reached. As discussed above, this may be used to determine whether maximum or minimum functionality has been reached.

The techniques described herein may be used for various electronic devices such as wireless communication devices, handheld devices, gaming devices, computing devices, computers, laptop computers, consumer electronic devices, and so on. Exemplary uses of the techniques for a wireless communication device are described below.

FIG. 5 shows a block diagram of a design of a wireless communication device 500 in a wireless communication system. Wireless device 500 may be a cellular phone, terminal, handset, Personal Digital Assistant (PDA), or the like. The wireless communication system may be a Code Division Multiple Access (CDMA) system, a global system for mobile communications (GSM) system, or the like.

Wireless device 500 is capable of providing bi-directional communication via a receive path and a transmit path. On the receive path, signals transmitted by base stations (not shown) are received by an antenna 512 and provided to a receiver (RCVR) 514. Receiver 514 conditions the received signal and provides an analog input signal to an Application Specific Integrated Circuit (ASIC) 520. On the transmit path, a transmitter (TMTR)516 receives and conditions the analog output signal from ASIC 520 and generates a modulated signal, which is transmitted via antenna 512 to the base stations.

ASIC 520 may include various processing, interface, and memory units such as a receive adc (rx adc)522, a transmit DAC (tx DAC)524, a modem processor 526, a Reduced Instruction Set Computing (RISC) processor 528, a controller/processor 530, an internal memory 532, an external bus interface 534, input/output (I/O) drivers 536, an audio DAC/driver 538, and a video DAC/driver 540. Rx ADC 522 digitizes the analog input signal from receiver 514 and provides samples to modem processor 526 and provides an analog output signal to transmitter 516. Modem processor 526 performs processing for data transmission and reception, e.g., encoding, modulation, demodulation, decoding, and so on. RISC processor 528 may perform various types of processing for wireless device 500, such as processing for video, graphics, higher layer applications, and so forth. Controller/processor 530 may direct the operation of various processing and interface units within ASIC 520. Internal memory 532 stores data and/or instructions for various units within ASIC 520.

The EBI 534 facilitates the transfer of data between the ASIC 520 and the main memory 544. I/O driver 536 drives I/O device 546 via an analog or digital interface. The audio DAC/driver 538 drives the audio device 548, which audio device 548 can be a speaker, a headset, headphones, or the like. Video DAC/driver 540 drives a display unit 550, which display unit 550 may be a Liquid Crystal Display (LCD) or the like.

Internal memory 532, main memory 544, and/or other units may implement the techniques described herein. For example, any of the memories may be generated as shown in FIG. 2.

In view of the above, it will be appreciated that embodiments of the invention may also include methods of performing the functions, sequence of actions, and/or algorithms described herein. For example, a method of adapting WL pulse width used in a memory system may be performed according to the flowchart illustrated in fig. 3.

It will also be appreciated that methods according to embodiments of the invention may be implemented in hardware and/or software. A hardware/software implementation may comprise a combination of a processor and an article of manufacture. For example, the RISC processor 528 may be configured to implement the techniques for adapting WL pulse width described herein to optimize operation of the internal memory 532 and/or the main memory 544. The article of manufacture may further include a storage medium and an executable computer program, such as a computer program product stored on a computer readable medium. An executable computer program may include a set of instructions to perform the operations or functions described. It will be appreciated that, as used herein, an instruction set may include one or more instructions.

The embodiments of the present invention described above provide several advantages over conventional techniques. For example, the techniques described herein provide an increase in overall yield. Furthermore, the produced IC does not suffer from worst case process variations, resulting in reduced WL pulse width, which may improve performance and power consumption characteristics, as well as improve cell stability (e.g., by reducing the probability of cell flipping). Due to the tighter distribution of power consumption across different ICs, there may be a better prediction of the total IC power. In addition, because a larger portion of the manufactured ICs may have lower power consumption, the average power consumption of all manufactured ICs may be reduced. The sensing margin may also be reduced as long as the memory does not fail (which results in a faster sensing margin response). The sensing margin may also be individually optimized for each memory as needed for proper operation of the memory. The impact on test time is also negligible, since the techniques described herein use an on-chip BIST to adapt the WL pulse width, which does not require additional external testing.

While the foregoing disclosure shows illustrative embodiments of the invention, it should be noted that various changes and modifications could be made herein without departing from the scope of the invention as defined by the appended claims. For example, one of ordinary skill in the art will appreciate that the incremental search algorithm described above is only one of many search algorithms that may be implemented to find an optimized WL pulse width code. A tree search algorithm, a random search algorithm, or other search algorithms well known in the art may also be used according to various embodiments of the present invention. The functions, steps and/or actions of the method claims in accordance with the embodiments of the invention described herein need not be performed in any particular order. Furthermore, although elements of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

Claims (39)

1. An apparatus comprising a memory system, the memory system comprising:

a memory operating according to a Word Line (WL) pulse having an associated WL pulse width;

a built-in self test (BIST) unit that interfaces with the memory, the BIST unit configured to run a self test of internal functionality of the memory and provide a signal indicating whether the memory passes or fails the self test; and

an adaptive WL control circuit that interfaces with the BIST unit and the memory, the adaptive WL control circuit configured to adjust the WL pulse width of the memory based on the signal provided by the BIST unit.

2. The apparatus of claim 1, wherein the adaptive WL control circuit is configured to increase the WL pulse width if the signal provided by the BIST unit indicates that the memory fails the self-test, and to decrease the WL pulse width if the signal provided by the BIST unit indicates that the memory passes the self-test.

3. The apparatus of claim 2, wherein the adaptive WL control circuit is further configured to instruct the BIST unit to perform a subsequent self-test of the internal functionality of the memory as the WL pulse width increases or decreases until a result of the self-test changes from pass to fail or from fail to pass.

4. The apparatus of claim 3, wherein the adaptive WL control circuit is configured to set the WL pulse width of the memory to a WL pulse width value used immediately prior to the self-test changing from a pass to a fail.

5. The apparatus of claim 3, wherein the adaptive WL control circuit is configured to set the WL pulse width of the memory to a WL pulse width value used when the self-test changes from fail to pass.

6. The apparatus of claim 3, wherein the adaptive WL control circuit is configured to increase or decrease the WL pulse width from an initial value in a feedback loop by providing a new value determined based on the signal provided by the BIST unit.

7. The apparatus of claim 6, wherein the adaptive WL control circuit is configured to increment or decrement the WL pulse width.

8. The apparatus of claim 1, wherein the adaptive WL control circuit comprises:

a first control circuit interfaced with the BIST unit, the first control circuit configured to determine whether to increase or decrease the WL pulse width of the memory based on the signal provided by the BIST unit and provide a first control signal indicating the determined adjustment to the WL pulse width; and

a second control circuit interfacing with the first control circuit, the second control circuit configured to adjust the WL pulse width based on the first control signal provided by the first control circuit.

9. The apparatus of claim 8, wherein the first control circuit determines to increase the WL pulse width if the signal provided by the BIST unit indicates that the memory fails the self-test, and to decrease the WL pulse width if the signal provided by the BIST unit indicates that the memory passes the self-test.

10. The apparatus of claim 8, wherein the second control circuit is further configured to provide an overload signal to the first control circuit indicating that the WL pulse width has reached a maximum or minimum allowed value.

11. The apparatus of claim 10, wherein the second control circuit is a counter configured to increment or decrement a WL pulse width value according to the first control signal provided by the first control circuit, and configured to provide the adjusted WL pulse width as an incremented/decremented value and the overload signal as an overflow bit of the increment/decrement operation.

12. The apparatus of claim 8, wherein the adaptive WL control circuit is further configured to map the adjusted WL pulse width to an allowed WL pulse width of the memory in a monotonically increasing or decreasing manner.

13. The apparatus of claim 8, wherein the adaptive WL control circuit further comprises a reprogramming module interfaced with the first and second control circuits, the second control circuit configured to provide the adjusted WL pulse width value to the reprogramming module, the first control circuit configured to provide a write signal instructing the reprogramming module to store the adjusted WL pulse width value provided by the second control circuit, and the reprogramming module configured to provide non-volatile storage of the adjusted WL pulse width value.

14. The apparatus of claim 8, wherein the reprogramming module is implemented as an eFUSE memory.

15. The apparatus of claim 8, wherein the apparatus is a wireless communication device, the apparatus further comprising a system controller.

16. The apparatus of claim 15, wherein the system controller is configured to instruct the memory system to adjust the WL pulse width upon initial power up of the wireless communication device.

17. The apparatus of claim 15, wherein the system controller is configured to instruct the memory system to periodically adjust the WL pulse width according to a given time interval.

18. A method of adjusting a Word Line (WL) pulse width in a memory system including a memory operating according to a WL pulse, the method comprising:

performing a self-test on the memory system to test internal functionality of the memory at a current WL pulse width; and

adjusting the WL pulse width of the memory based on a result of the self-test using an on-chip adaptive WL control circuit.

19. The method of claim 18, wherein the adjusting includes increasing the WL pulse width if the memory fails the self-test and decreasing the WL pulse width if the memory passes the self-test.

20. The method of claim 19, further comprising:

repeating the performing and the adjusting until the result of the self-test changes from pass to fail or from fail to pass.

21. The method of claim 20, further comprising:

mapping the adjusted WL pulse width to an allowed WL pulse width of the memory in a monotonically increasing or decreasing manner.

22. The method of claim 20, further comprising:

setting the WL pulse width of the memory to a WL pulse width value used immediately before the self-test changes from a pass to a fail.

23. The method of claim 20, further comprising:

setting the WL pulse width of the memory to a WL pulse width value used when the self-test changes from fail to pass.

24. The method of claim 18, wherein the performing and conditioning operations are initiated upon initial power-up of the memory system.

25. The method of claim 18, wherein the performing and adjusting operations are initiated periodically according to a given time interval.

26. An apparatus for adjusting a Word Line (WL) pulse width in a memory system including a memory operating according to a WL pulse, the apparatus comprising:

means for performing a self-test on the memory system to test internal functionality of the memory at a current WL pulse width; and

means on chip for adjusting the WL pulse width of the memory based on a result of the self-test.

27. The apparatus of claim 26, wherein the means for adjusting comprises means for increasing the WL pulse width if the memory fails the self-test, and means for decreasing the WL pulse width if the memory passes the self-test.

28. The apparatus of claim 27, further comprising:

means for repeating the performing and the adjusting until a result of the self-test changes from pass to fail or from fail to pass.

29. The apparatus of claim 28, further comprising:

means for mapping the adjusted WL pulse widths to allowed WL pulse widths of the memory in a monotonically increasing or decreasing manner.

30. The apparatus of claim 28, further comprising:

means for setting the WL pulse width of the memory to a WL pulse width value used immediately before the self-test changes from a pass to a fail.

31. The apparatus of claim 28, further comprising:

means for setting the WL pulse width of the memory to a WL pulse width value used when the self-test changes from fail to pass.

32. A computer-readable medium comprising a set of instructions executable by a processor to adjust a Wordline (WL) pulse width in a memory system comprising a memory operating according to a WL pulse, the computer-readable medium comprising:

a first set of instructions to perform a self-test on the memory system to test internal functionality of the memory at a current WL pulse width; and

a second set of instructions to adjust the WL pulse width of the memory based on a result of the self-test.

33. The computer-readable medium of claim 32, wherein the second set of instructions includes instructions executable by the processor to increase the WL pulse width if the memory fails the self-test and decrease the WL pulse width if the memory passes the self-test.

34. The computer-readable medium of claim 33, further comprising:

a third set of instructions to repeat the first and second sets of instructions until the result of the self-test changes from pass to fail or from fail to pass.

35. The computer-readable medium of claim 34, further comprising:

a fourth set of instructions to map the adjusted WL pulse widths to allowed WL pulse widths of the memory in a monotonically increasing or decreasing manner.

36. The computer-readable medium of claim 34, further comprising:

a fifth set of instructions to set the WL pulse width of the memory to a WL pulse width value used immediately prior to the self-test changing from a pass to a fail.

37. The computer-readable medium of claim 34, further comprising:

a sixth set of instructions to set the WL pulse width of the memory to a WL pulse width value used when the self-test changes from fail to pass.

38. The computer-readable medium of claim 32, further comprising:

a seventh set of instructions to run the first and second sets of instructions upon initial power up of the memory system.

39. The computer-readable medium of claim 32, further comprising:

an eighth instruction set to periodically execute the first and second instruction sets according to a given time interval.