HK1151400B - Frame sync detecting circuit and fsk receiver using the same - Google Patents

Abstract

A frame sync detecting circuit and FSK receiver wherein, as shown in the drawing, sequential moving average values (squared marks) are determined, from the over-sample values (solid line) of a received word pattern, in a given symbol interval, and the differences between the sequential moving average values (□) and the respective average values of a given sync word pattern in the given symbol interval are determined as DC offsets Δf. Subsequently, the DC offsets Δf are subtracted from the received word pattern to perform a calculation of correlation with the sync word pattern, thereby determining correlation values designated by black circular dots (●). Then, if any ones of the correlation values exceed a predetermined threshold value, it is determined that a sync word candidate has been received, so that the symbol values (P11'-P20') of the received word pattern after the DC offset corrections are compared with the symbol values of the sync word pattern. If all of the symbol errors are within a given range, the sync word pattern detection is ultimately determined.

Description

Frame synchronization detection circuit and FSK receiver using the same

Technical Field

The present invention relates to a frame synchronization detection circuit suitably implemented in an FSK demodulation circuit or the like, and an FSK receiver using the same.

Background

In the case of the FSK (Frequency Shift Keying) modulation scheme, demodulation is performed by Frequency-voltage conversion. In such demodulation, as a demodulation signal, for example, voltage outputs corresponding to a plurality of frequencies of 2 or 4 values are superimposed on the demodulation signal with a DC offset due to a frequency error of transmission and reception. In the case of the phase modulation method, demodulation is performed by phase-voltage conversion, and a DC offset is generated similarly due to a phase error in transmission and reception, but only the FSK modulation method will be described below. If the DC offset is included, it is difficult to detect a specific word pattern (specific word pattern) of frame synchronization or the like. This problem is particularly significant in the case of a 4-value FSK in which the symbol voltage interval (symbol frequency deviation interval) is narrow. On the other hand, as a conventional technique for detecting a character pattern by performing offset correction, for example, patent document 1 is known.

In the synchronization signal detection device disclosed in patent document 1, in order to detect a frame synchronization word inserted into a predetermined position of each frame, a product-sum correlation value (product-sum-based correlation value) between a detection signal and a known frame synchronization word is first obtained. When the correlation value is a peak value and exceeds a predetermined threshold value, the detection signal is determined as a frame synchronization word candidate, a DC offset value is determined from the average value of the detection signal, and the DC offset value is subtracted from the detection signal to perform offset correction. Then, a vector error (sum of squares of errors) for all symbol data between the corrected detected signal and a known frame synchronization code is obtained. When the vector error is smaller than a predetermined threshold value, the synchronization signal detection means judges that the detected signal is a target frame synchronization word, and therefore, synchronization is achieved. Thus, it is possible to eliminate a response delay caused by removing the DC offset and to accurately detect synchronization from the first signal.

In the above-described conventional technique, the correlation between the detected signal and the known frame synchronization code is obtained, and then the DC offset value obtained from the average value of the detected signal is corrected. Therefore, as described above, although the frame synchronization word candidates can be determined relatively blockwise, since correlation calculation (convolution) is performed when DC offset is included, the threshold for final frame synchronization establishment determination is low, and as a result, noise or main data (traffic channel in the case of FSK) is erroneously determined as a frame synchronization word, which is a problem that it takes time to establish synchronization.

Patent document 1: japanese patent laid-open publication No. 2006-339859

Disclosure of Invention

In view of the above problems, it is an object of the present invention to provide a frame synchronization detecting circuit capable of establishing frame synchronization quickly and with high accuracy, and an FSK receiver using the same.

In a frame synchronization detecting circuit (frame sync detecting circuit) and an FSK receiver according to the present invention, a DC offset is obtained from a difference between a moving average value and a predetermined ideal average value of a predetermined number of received patterns, the DC offset is corrected by subtracting the DC offset from each symbol value of the received patterns, the received patterns corrected by the DC offset are compared with each symbol value of a predetermined synchronization pattern, and when errors of all symbols fall within a predetermined range, it is determined that a synchronization pattern is detected. Therefore, the frame synchronization detection circuit and the FSK receiver according to the present invention can establish frame synchronization quickly and with high accuracy.

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawings.

Drawings

Fig. 1 is a block diagram showing an electrical configuration of an FSK receiver according to an embodiment of the present invention.

Fig. 2 is a block diagram showing an example of a configuration of a demodulation circuit in the FSK receiver shown in fig. 1.

Fig. 3 is a waveform diagram for explaining a DC offset generated in a received signal due to a transmission/reception frequency deviation in 4-value FSK.

Fig. 4 is a diagram for explaining a DC offset correction operation and a correction control operation in the FSK receiver shown in fig. 1.

Fig. 5 is a diagram showing a configuration example of a DC offset correction circuit and a correction control circuit that perform the operation shown in fig. 4.

Fig. 6 is a block diagram showing an example of a configuration of a demodulation circuit in an FSK receiver according to another embodiment of the present invention.

Fig. 7 is a block diagram showing a configuration example of a synchronization word-pattern (word-pattern) detection circuit.

Fig. 8 is a waveform diagram for explaining the operation of the synchronization word pattern detection circuit shown in fig. 7.

Fig. 9 is a waveform diagram for explaining the operation of the synchronization word pattern detection circuit shown in fig. 7.

Fig. 10 is a waveform diagram for explaining the operation of the synchronization word pattern detection circuit shown in fig. 7.

Fig. 11 is a waveform diagram for explaining the operation of the synchronization word pattern detection circuit shown in fig. 7.

Fig. 12 is a waveform diagram for explaining the operation of the synchronization word pattern detection circuit shown in fig. 7.

Fig. 13 is a block diagram showing a configuration example of a 4-value FSK symbol reproducing circuit.

Fig. 14 is a waveform diagram for explaining the operation of the 4-value FSK symbol reproduction circuit shown in fig. 13.

Fig. 15 is a waveform diagram for explaining a counting operation of a timer in the 4-value FSK symbol reproduction circuit shown in fig. 13.

Detailed Description

An embodiment according to the present invention will be described below with reference to the drawings. In the drawings, the same reference numerals denote the same components, and description thereof will be appropriately omitted.

Fig. 1 is a block diagram showing an electrical configuration of an FSK receiver 1 according to an embodiment of the present invention. The FSK receiver 1 employs a double super heterodyne (double super heterodyne) system, and for example, as shown in fig. 1, the FSK receiver 1 includes an antenna 3, a band-pass filter (band-pass filter)4, an amplifier (amplifier)5, a mixer (mixer)6, a local oscillator circuit (local oscillator circuit)7, a band-pass filter 8, an amplifier 9, a mixer 10, a local oscillator circuit 11, a band-pass filter 12, an amplifier (intermediate frequency amplifier) 13, an analog/digital converter 14, a digital/analog converter 15, a speaker 16, a digital/analog converter 17, and a demodulation circuit 21.

In the FSK receiver 1, a signal received by the antenna 3 is filtered by the band-pass filter 4, for example, a component of a 440MHz FSK high-frequency signal is amplified by the amplifier 5, and then input to the mixer 6 of the first stage. The mixer 6 is mixed with an oscillation signal of, for example, 486.35MHz from the local oscillation circuit 7 to obtain an intermediate frequency signal (first intermediate frequency signal) of, for example, 46.35MHz, and an intermediate frequency component of the first intermediate frequency signal is filtered by the band-pass filter 8, amplified by the amplifier 9, and then input to the mixer 10 of the second stage. In the mixer 10, an oscillation signal of, for example, 45.9MHz from the local oscillation circuit 11 is mixed to obtain an intermediate frequency signal (second intermediate frequency signal) of, for example, 450kHz, an intermediate frequency component of which is filtered by a band-pass filter 12 and amplified by an amplifier (intermediate frequency amplifier) 13, and then, is input to an analog/digital converter 14. In the analog/digital converter 14, the input signal is down-sampled at 30kHz, for example, and converted into a digital value having a rate of 96ksps (sample per second), and then input to the demodulation circuit 21.

The demodulation circuit 21 includes a DSP (digital signal processor) or the like, and in the demodulation circuit 21, a voice signal is demodulated, subjected to analog conversion in the digital/analog converter 15, and then converted into sound by the speaker 16. The demodulation circuit 21 outputs data corresponding to the input signal level to the digital/analog converter 17, and the data is subjected to analog conversion and then to gain control of the RF amplifier 5 and the intermediate frequency amplifiers 9 and 13.

Fig. 2 is a block diagram showing a configuration example of the demodulation circuit 21. The signal output from the analog/digital converter 14 is input to the frequency converter 22, and first, the high frequency component is filtered by the high pass filter 221. Next, at the mixer 222, a 12kHz, 96ksps signal is obtained by mixing with an oscillation signal of a rate of, for example, 18kHz, 96ksps from the local oscillation circuit 223, and after the 12kHz, 96ksps signal is filtered in its signal component by the band-pass filter 224, is decimated at 1/2 intervals, that is, after being down-sampled at a frequency of 1/2 (48kHz), and is input to the quadrature converter 24. The converter 23 is provided to reduce the processing of the orthogonal converter 24, and the converter 23 may be omitted when the orthogonal converter 24 can sufficiently perform the processing.

In the quadrature converter 24, the input signal is divided into two paths and input to the mixers 241 and 242. In the mixer 241, the divided signal is mixed with an oscillation signal having an oscillation frequency of 12kHz and a rate of 48ksps, for example, from the local oscillation circuit 243. The other divided signal is mixed with an oscillation signal from a local oscillation circuit 243 whose phase is shifted by 90 ° at a phase shifter 244 in a mixer 242, and is converted into a signal of an I component and a Q component having rates of 48ksps after quadrature conversion. The I and Q signals are output through low pass filters 245 and 246, down-sampled at a sampling frequency of 1/2 (24kHz) at converters 25 and 26, passed through low pass filters 27 and 28, and input to a phase detector 29. The converters 25 and 26 are provided to reduce the load of the band limiting process of the low-pass filters 27 and 28, and when the low-pass filters 27 and 28 can sufficiently perform the process, the converters 25 and 26 may be omitted.

The phase detector 29 calculates θ tan from the I, Q component by I cos θ and Q sin θ^-1(Q/I) to determine the phase of the signal. The adder 301 of the frequency detector 30 subtracts the phase 1 sample before delayed by the delay unit 302 from the obtained phase. The amount of the frequency deviation is thus obtained as a phase differential. The phase detector 29 and the frequency detector 30 thus constitute a detector circuit, and delay detection (delay detection) is performed on them, and a demodulated signal that is oversampled (over-sampled) at a sampling rate (24kHz) that is 10 times the symbol rate (2.4kHz) is obtained from the output of the detector circuit.

The demodulated signal is input from the arcsine filter 31 to a 4-value FSK symbol reproduction circuit 33 and a synchronization-word-pattern detection circuit (sync-pattern) 34 via a root-raised-cosine filter (root-raised-cosine filter) 32. The arcsine filter 31 and the root-raised cosine filter 32 function as a root-cosine roll-off filter together with the Sinc filter inserted on the transmission side, and together form a Nyquist filter. The Sinc filter 31 suppresses the high-frequency side (to be deleted), and the arcsine filter 31 restores the high-frequency side (reinforces the high-frequency side), thereby realizing band limitation.

The 4-value FSK symbol reproduction circuit 33 demodulates the 4-value FSK symbol data based on the amplitude value (frequency deviation) of the demodulation signal. In this demodulation process, the 4-value FSK symbol reproduction circuit 33 internally generates a symbol clock, reads the amplitude value (frequency deviation) at the time of the symbol clock of 2.4kHz, performs map determination (map-based determination), determines which of the symbol values "00", "01", "10", and "11" of the 4-value FSK the amplitude value (frequency deviation) corresponds to, and reproduces the symbol data. As described below, the 4-value FSK symbol reproduction circuit 33 receives a reset signal (reset signal) from the synchronization pattern detection circuit 34 at the detection timing of the synchronization pattern, and adjusts the timing of the internal symbol clock.

The symbol data demodulated by the 4-value FSK symbol regeneration circuit 33 is the 4-value, and therefore, it is output to a frame formation circuit (frame formation circuit)35 as a 2-bit signal at the symbol rate of 2.4 ksps. When the synchronization pattern detection circuit 34 detects a synchronization pattern as described below, that is, when the reception is performed normally, the frame generation circuit 35 configures the symbol data into a predetermined frame and outputs the frame to the speech demodulation unit 3 (36). The correction of the symbol clock by the synchronization pattern detection circuit 34 and the reproduction of the symbol data by the 4-value FSK symbol reproduction circuit 33 will be described in detail later.

The obtained symbol data is extended by using a predetermined speech codec circuit in the speech demodulation section 36, and is demodulated into a PCM speech signal of 8kHz and 16 bits from 4-valued data having a sampling frequency of 2.4 kHz. The PCM speech signal is oversampled at 6 times the frequency (48kHz) in a converter 37, passed through a low-pass filter 38, input to a digital/analog converter 39, demodulated into an analog speech signal, amplified by an amplifier 40, and converted into sound by a speaker 41.

On the other hand, the converted data from the analog/digital converter 14 is down-sampled at a frequency of 1/24 (4kHz) at the converter 45, and is input to the RSSI circuit 46. In the RSSI circuit 46, the dc component mixed in the analog/digital converter 14 is removed by the high-pass filter 461, and then the absolute value is obtained by the absolute value circuit 462, and the RSSI level is obtained by averaging by the low-pass filter 463. Then, the RSSI level is supplied to an indicator not shown or the like, and is input to the AGC computing circuit 42. The AGC operation circuit 42 calculates an IF gain based on the RSSI level, and performs gain control of the RF amplifier 5 and the intermediate frequency amplifiers 9 and 13 after analog conversion of the calculated data by the analog/digital converter 39.

In the FSK receiver 1 configured as described above, it should be noted that in the present embodiment, in order for the DC offset correction circuit 50 as the correction means to adjust the oscillation frequency of the local oscillation circuit 223 (or 243) so as to remove the DC offset component (F0-F0 '═ Δ F) based on the intermediate value (F0') of the maximum value "11" and the minimum value "00" of the demodulated signal, the correction control circuits 51, 52 are provided and the correction thereof is stopped as appropriate. The frequency converter 22 is provided to reduce the number of processes at the later stage, and the frequency converter 22 may be omitted. At this time, the local oscillation circuit 243 outputs an oscillation signal having an oscillation frequency of 30kHz and a rate of 96ksps, and the oscillation frequency of the local oscillation circuit 243 is controlled to perform DC offset correction based on the frequency deviation.

Fig. 3 is a waveform diagram showing the correction. In the present embodiment, for example, the frequency deviation at the minimum value "00" is set to-1050 Hz, the frequency deviation at "01" is set to-350 Hz, the frequency deviation at "10" is set to +350Hz, and the frequency deviation at the maximum value "11" is set to +1050Hz with respect to the carrier frequency f 0.

When the carrier frequency F0 on the receiving side coincides with the carrier frequency F0 on the transmitting side, the symbol values obtained at the sampling points are the above-mentioned frequencies, as shown in fig. 3 (a). In fig. 3, for simplicity of explanation, the sampling points are assumed to be symbol determination points at which the deviation is the least when considering an eye pattern (eye pattern). On the other hand, if the carrier frequency F0' on the receiving side does not match the carrier frequency F0 on the transmitting side, the symbol values obtained at the sampling points are shifted as shown in fig. 3 (b). In the example of fig. 3(b), since the carrier frequency F0' on the receiving side is biased to the higher side, the data of the minimum value "00" does not appear, and only the remaining data of "01", "10", and "11" appears. Therefore, the sensitivity is deteriorated. Then, as described above, the oscillation frequency of the local oscillation circuit 223 (or 243) is adjusted based on the intermediate value (F0') of the maximum value "11" and the minimum value "00" of the demodulation signal, thereby removing the DC offset component (F0-F0 ═ Δ F).

Fig. 4 is a diagram for explaining a correction operation of the DC offset correction circuit 50 and a control operation of the correction control circuit 51 as first correction control means. As the demodulation signal, the waveform data shown in fig. 4(a) is output from the root raised cosine filter 32 in a state (24ksps) of being oversampled at the 24kHz which is 10 times the symbol rate (2.4 kHz). The waveform data is sampled at the symbol rate, i.e., 2.4kHz, in the 4-value FSK symbol reproduction circuit 33, and the sample values (frequency deviations) P1 to P9 shown by black circles in fig. 4(a) are obtained. In addition, actually, the output of the root raised cosine filter 32 is wave height value (wave height value) data of the DC waveform as shown in fig. 4(a), but in fig. 4(a), for the sake of easy understanding of the explanation, the scale (scale) is represented by the frequency of the frequency deviation by replacing the DC value with the frequency.

Here, the DC offset correction circuit 50 introduces the sampled values P1 to P9 for DC offset correction, and updates the sampled values to the maximum value when a value larger than the existing value is input, as shown in fig. 4 (d). Similarly, as shown in fig. 4(e), when a value smaller than the existing value is input, the DC offset correction circuit 50 updates the value to the minimum value. On the other hand, as shown in fig. 4(f), the correction control circuit 51 obtains the difference between the maximum value and the minimum value, stops the correction operation of the DC offset correction circuit 50 when the difference is lower than a predetermined threshold TH1, performs the correction operation when the difference is equal to or greater than the threshold TH1, and resets the maximum value and the minimum value. That is, the maximum value and the minimum value are updated to the symbol value at the next sampling point.

Here, the threshold TH1 is smaller than (maximum frequency deviation-minimum frequency deviation) and larger than (maximum frequency deviation-minimum frequency deviation) × (n-2)/(n-1) in the case of n-value modulation (n is 3 or more), and is selected in consideration of an appropriate margin. In the present embodiment, since n is 4, the maximum frequency deviation is +1050Hz, and the minimum frequency deviation is-1050 Hz, the threshold TH1 is smaller than 2100Hz and larger than 1400Hz, and 1500Hz is selected in consideration of the margin.

In the example of fig. 4, the frequency deviation of the first sampled value P1 is-350 Hz, which is registered as both a maximum value and a minimum value. Since the frequency deviation at the next sample value P2 is +1050Hz, the maximum value is updated to this value, and the difference between the maximum value and the minimum value is 1400Hz, and therefore, the correction action of the DC offset is prohibited. On the other hand, since the frequency deviation at the sampling value P3 is +1400Hz, the maximum value is updated to this value, and the difference between the maximum value and the minimum value is 1750Hz, the DC offset correction operation is performed. As shown in fig. 4(g), this correction operation calculates an average value of the maximum value and the minimum value corresponding to Δ f in fig. 3, and subtracts the average value from the sample value. In the example of the sample value P3, the value obtained by subtracting (1400-350)/2 from the 1400Hz is 525Hz, and 875Hz is set as the corrected sample value P3'.

In an actual correction operation, the oscillation frequency of the local oscillation circuit 223 (or 243) is changed so as to shift the inputted data of the frequency deviation to the 525Hz with a decrease. That is, the local oscillation circuit 223 (or 243) includes a digital VCO, and the DC offset correction circuit 50 changes the oscillation frequency by changing the timing of reading waveform (indicating the amplitude level) data from the sin table which is the basis of the oscillation waveform, and changes the read timing to the timing of the oscillation frequency higher than the current oscillation frequency by 525 Hz.

By this correction operation, the data of the frequency deviation of the subsequent sampling values P4 to P9 are shifted to the reference symbols P4 'to P9', and the determination result of the 4-value FSK symbol regeneration circuit 33 can be demodulated with a more accurate value as shown in fig. 4(b) than the original value of fig. 4 (c). When the sample value P3 'is corrected appropriately, the absolute value of the maximum value and the absolute value of the minimum value are substantially equal to each other at the time (P7') when the data of 1 sample after correction is input, and the correction amount (Δ f) is 0.

On the other hand, the data of the frequency deviation amount output from the adder 301 is supplied to a squelch circuit (squelch circuit) 43. In the squelch circuit 43, a high-pass filter 431 extracts a noise component, an absolute value circuit 432 calculates an absolute value of the noise, and a low-pass filter 433 averages the absolute value. The magnitude of the squelch is thus determined. The correction control circuit 52 prohibits the DC offset correction circuit 50 from adjusting the oscillation frequency of the local oscillation circuit 223 (or 243) when the squelch level (noise level) is larger than a predetermined threshold TH 2. Thereby preventing erroneous correction caused by noise.

Fig. 5 is a diagram showing a configuration example of the DC offset correction circuit 50 and the correction control circuits 51 and 52. Similarly to the 4-value FSK symbol reproduction circuit 33, the 24ksps demodulated signal output from the root-raised cosine filter 32 is sampled at a clock of 2.4ksps symbol rate output from the 4-value FSK symbol reproduction circuit 33 by a sampler 501, and frequency deviation information corresponding to the DC offset Δ f obtained by sync pattern detection, which will be described later, is subtracted by a subtractor 502, and then input to sample-and-hold circuits 503 and 504. The sample hold circuit 503 compares the data sequentially input from the reset time with the stored data (stored data), and when data larger than the stored data is input, updates the stored data to the input value, obtains the maximum value, and holds the maximum value. Similarly, the sample hold circuit 504 compares the data sequentially input from the reset time with the stored data, and when data smaller than the stored data is input, updates the stored data to the input value, thereby obtaining and holding the minimum value. Next, the data of the maximum value and the minimum value are added to each other by an adder 505 and divided by a divider 506 by 1/2. Thereby obtaining information on the frequency deviation. In other words, after the output from the divider is enabled, the correction control circuit 51 resets the maximum value held by the sample-and-hold circuit 503 and the minimum value held by the sample-and-hold circuit 504. Next, after the reset, the sample hold circuits 503 and 504 compare the sequentially input data with the stored data, and update the stored data according to the comparison result. The information is input to a conversion circuit 508 via a low-pass filter 507 for noise removal, converted into waveform data read timing of a digital VCO constituting the local oscillation circuit 223 (or 243), and supplied to the local oscillation circuit 223 (or 243).

Further, the correction control circuit 51 includes: a subtractor 511 that subtracts the minimum value held by the sample-and-hold circuit 504 from the maximum value held by the sample-and-hold circuit 503 to obtain the difference between the two values; a threshold value determining unit 512 for comparing the obtained difference with the threshold value TH1, that is, 1500 Hz; and a gate (gate)513 that allows an output from the divider 506 when the difference is above the threshold TH1 and blocks the output from the divider 506 when the difference is below the threshold TH 1. Likewise, the correction control circuit 52 includes: a threshold determination unit 521 for comparing the squelch level outputted from the squelch circuit 43 with a predetermined threshold TH 2; and allowing the output from the divider 506 when the squelch size is below the threshold TH2, and blocking the gate 522 of the output from the divider 506 when the squelch size is greater than the threshold TH 2.

According to the above-described configuration, in the FSK receiver 1, in order for the DC offset correction circuit 50 to correct the DC offset component generated by the frequency deviation of transmission and reception based on the intermediate value between the maximum value and the minimum value of the demodulated signal, the correction control circuit 51 is provided, and the correction control circuit 51 stops the correction by the DC offset correction circuit 50 when the difference between the maximum value and the minimum value is less than the predetermined threshold value TH1, so that, for example, in the case of the 4-value FSK signal, the offset correction is not performed for values such as "00" and "01", "10" and "11" which do not have intermediate values therebetween, or values such as "00" and "10", "01" and "11" which do not have intermediate values therebetween but have a deviation from the intermediate values, and only when the maximum value and the minimum value of "00" and "11" are obtained, even for a multivalued FSK signal, it is possible to accurately detect a frequency deviation and appropriately remove an offset. Further, since the offset correction is performed at the timing when the signal equal to or higher than the predetermined threshold TH1 is obtained, the offset correction can be performed quickly without monitoring the signal for a long time.

Further, since the DC offset correction circuit 50 performs offset correction by controlling the oscillation frequency of one of the local oscillator 223 in the frequency converter 22 that obtains an intermediate frequency signal from a received high frequency signal and the local oscillator 243 in the quadrature converter 24 that performs quadrature conversion on the obtained intermediate frequency signal, it is not necessary to change the characteristics of the band pass filter 224 or the low pass filters 245, 246, 27, and 28 (since the pass bands are the same), and it is possible to improve adjacent channel signal removal capability.

In addition, the correction control circuit 52 stops the correction operation of the DC offset correction circuit 50 even when the noise level is large in response to the output of the muting circuit 43, and thus it is possible to prevent malfunction due to noise.

Here, the DC offset correction circuit 50 performs offset correction by controlling the oscillation frequency of the local oscillator 223 in the frequency converter 22 that obtains an intermediate frequency signal from a received high frequency signal or the local oscillator 243 in the quadrature converter 24 that performs quadrature conversion on the obtained intermediate frequency signal, as described above, but as another embodiment, the DC offset correction circuit 50 may directly correct the demodulated signal itself by subtracting the average value (median) of the maximum value and the minimum value from the output signal level (output signal level) of the 24ksps demodulated signal output from the root-raised cosine filter 32 by the subtractor 62, as shown in the demodulation circuit 61 in fig. 6. In this case, the control of the local oscillator 223 or 243 is not performed.

As described above, by directly subtracting the DC offset from the demodulated signal, the symbol can be quickly reproduced regardless of the amount of the frequency deviation. On the other hand, when the oscillation frequency of the local oscillator 223 or 243 is controlled as described above, the center frequency of the obtained intermediate frequency signal always coincides with the center frequency of the band-pass filter 224, or coincides with the pass bands of the low-pass filters 245, 246, 27, and 28, and therefore, signal degradation is small and high sensitivity can be obtained.

Note that, in the present embodiment, in order to detect the synchronization pattern by the synchronization pattern detection circuit 34 as a frame synchronization detection circuit, correction of the DC offset Δ f caused by the frequency difference between the transmission and reception is first performed. Fig. 7 is a block diagram showing a configuration example of the synchronization pattern detection circuit 34. The synchronization word pattern detection circuit 34 generally includes: a memory 341 for storing over-sampled values during a specified number, for example, 10 symbols, of the received word pattern (the demodulated signal); an average value calculation unit 342 for calculating a moving average value of the oversampling values; a register 343 that stores the average value of the specified number of parts of the given synchronization word pattern as an ideal average value; a subtractor 344 that obtains a DC offset from a difference between the ideal average value stored in the register 343 and the moving average value obtained by the average value calculation unit 342; a subtractor 345 for subtracting the DC offset from each oversampled value of the received word graph; a memory 346 in which the synchronization word map is stored; a correlation operator 347 for calculating a correlation between the DC offset-corrected received word pattern obtained by the subtractor 345 and the synchronization word pattern stored in the memory 346; a register 348 storing a predetermined threshold TH 3; a comparator 349 for comparing the correlation value obtained by the correlation operator 347 with a threshold TH3 stored in the register 348 and recognizing the correlation value as a synchronization word candidate when the correlation value is greater than a threshold TH 3; and a symbol comparator 340 for comparing the received pattern after the DC offset correction with each symbol value of the synchronization pattern when the comparator 349 recognizes the synchronization pattern candidate, and determining that the synchronization pattern is detected when errors of all symbols are within a predetermined range.

Fig. 8 to 12 are waveform diagrams for explaining the operation of the synchronization pattern detection circuit 34 described above. In the above description, oversampling is performed at a frequency 10 times the symbol clock, but in order to avoid complicating the drawing, these figures show data at intervals of 1 sample (equivalent to the case of performing oversampling at a frequency 5 times the symbol clock). The 24ksps received pattern (the demodulated signal) output from the root-raised cosine filter 32 is input to the memory 341, and in fig. 8, as shown by times … …, t-2, t-1, and t0, the received pattern is sequentially updated each time an over-sampled value is input, and only the over-sampled value during the latest 10 symbols is stored in the memory 341. In fig. 8, the oversampling values are indicated by continuous solid lines, and the symbol values P11 to P20 are indicated by circles.

Next, the average value calculation unit 342 calculates the average value every time the storage content of the memory 341 is updated, and sequentially obtains the moving average value of the oversampling values as shown in fig. 9. Then, the subtractor 344 as offset calculating means subtracts the average value of the 10 symbol periods of the synchronization word pattern stored in the register 343 from the moving average value output from the average value calculating section 342, thereby obtaining a DC offset (frequency correction amount) Δ f. Then, the DC offset Δ f is subtracted from each of the over-sampled values of the received word pattern stored in the memory 341 in the subtractor 345, thereby obtaining a DC offset-corrected received word pattern.

The correlation calculator 347 calculates the correlation (convolution) between the DC offset-corrected received pattern and the synchronization pattern stored in the memory 346 to obtain the correlation value shown in fig. 10. That is, when the synchronization word map is ai and the reception word map is bi, the correlation value F is F ∑ [ ai x (bi- Δ F) ] (where i is the number of samples, and i is 1, 2, … …, 91). In the case of the FSK, for example, 80 or 40msec frame data includes a synchronization word including a synchronization burst (sync burst) and a traffic channel (traffic channel) as main data. The synchronization word pattern stored in the memory 346 is a pattern of the synchronization word.

When the comparator 349 as the candidate determination means compares the correlation value F obtained as described above with the threshold TH3 stored in the register 348, in the example shown in fig. 8 to 10, if the correlation value F is greater than the threshold TH3 at time t-5 before 5 samples as shown in fig. 11, the comparator 349 determines that the synchronization word candidate is received and determines that the time t-5 is the provisional symbol time. That is, in the correlation operation (convolution), the word graph is received, offset correction is performed to perform offset (shift) in the y-axis direction in the curves shown in fig. 8 to 11, and sequential input is equivalent to performing offset in the x-axis direction, thereby determining whether or not the word graph matches a fixed synchronization word graph.

Next, with the candidate decision as a trigger (trigger), the symbol comparator 340 as a final decision unit corrects the DC offset Δ f for the symbol values P11 to P20, compares the corrected symbol values P11 'to P20' with the corresponding symbol values in the synchronization word map stored in the memory 346, and finally decides that the synchronization word map is detected when the errors of all the symbols are within a certain range, as shown in fig. 12. That is, when the symbol value of the synchronization word map is Ak and the symbol value of the reception word map is Bk, the error E is E ∑ Ak- (Bk- Δ f) | (where k is the number of samples and k is 1, 2, … …, 10), and when the error E is within the predetermined threshold TH4, the symbol comparator 340 performs the final synchronization determination.

In the detection determination of the synchronization word pattern, the symbol comparator 340 supplies a reset signal to the 4-value FSK symbol reproduction circuit 33 at the detection timing of the synchronization word pattern to adjust the timing of the internal symbol clock, as described below. The symbol comparator 340 takes the tentative DC offset Δ f used in the determination as a true value, supplies a value corresponding to the true value as frequency deviation information to the 4-value FSK symbol regeneration circuit 33 and the DC offset correction circuit 50, and performs DC offset correction in the following manner until communication is completed. Further, the symbol comparator 340, upon detecting the synchronization word pattern, notifies the 4-value FSK symbol reproduction circuit 33 and the frame generation circuit 35 that the synchronization word pattern has been detected, that is, that the reception is being performed normally, and allows the symbol reproduction in the 4-value FSK symbol reproduction circuit 33 and the frame formation in the frame generation circuit 35, that is, allows the output of the voice. On the other hand, when the comparator 349 detects that the correlation value is below the threshold TH3 and when the sign comparator 340 does not detect the synchronization word pattern, the control output as described above is not performed.

By adopting the structure as described above, the DC offset Δ f has been removed by the subtractor 344 before the correlation operation (convolution) is performed by the correlation operator 347, and therefore, the threshold for the symbol comparator 340 to decide the detection of the sync word can be strictly determined. Further, since the detection of the synchronization word is not determined based on the correlation operation (convolution) result, and the final detection condition is set such that the errors of all the symbol points are within a certain range, the frames can be finally synchronized quickly and with high accuracy.

In addition, it should be noted that, in the present embodiment, in the 4-value FSK symbol reproduction circuit 33, correction of the symbol clock for obtaining the sampling values (frequency deviations) P1 to P9, P3 'to P9' in fig. 4(a) is performed. Fig. 13 is a block diagram showing a configuration example of the 4-value FSK symbol regeneration circuit 33. In the 4-value FSK symbol reproduction circuit 33, the demodulated signal output from the root-raised cosine filter 32 and oversampled at a rate 10 times the symbol rate is input to a subtractor 330, and frequency deviation information corresponding to the DC offset Δ f obtained by detecting the synchronization pattern by the symbol comparator 340 of the synchronization pattern detection circuit 34 is subtracted therefrom, and then input to a shift register 331-1. Two stages of shift registers 331-2, 331-3 are connected in cascade with the shift register 331-1, and are sequentially shifted when new sample data is input. Therefore, in the oversampling cycle, the newest data is stored in the shift register 331-1, and the oldest data is stored in the shift register 331-3, for a total of 3 samples.

Further, the subtraction of the frequency deviation information is performed by the subtractor 330 only when the synchronization word pattern is detected by the synchronization word pattern detection circuit 34, that is, only when a frame is received and reception is normally performed. In addition, the control of the oscillation frequency of the local oscillators 223 and 243 by the DC offset correction circuit 50 or the subtraction of the DC offset component by the subtractor 62 are used to compensate. Also, the symbol comparator 340 outputs the DC offset Δ f when the sync word pattern is detected, and Δ f becomes 0 during a period when the sync word pattern is not detected. In this way, when the sync pattern is detected by the sync pattern detection circuit 34, correction based on the DC offset Δ f detected at that time is preferentially performed, and the DC offset Δ f can be quickly compensated.

Here, similarly, in the DC offset correction circuit 50, the frequency deviation information corresponding to the DC offset Δ f is subtracted by the subtractor 502, and thereby, in the synchronous pattern detection by the synchronous pattern detection circuit 34, as described above, the frequency deviation information is promptly subtracted by the subtractor 330 of the 4-value FSK symbol reproduction circuit 33, and the correction operation in the DC offset correction circuit 50 is performed under the same condition as the case of compensating the DC offset. That is, as described above, the DC offset correction based on the synchronization pattern detection by the synchronization pattern detection circuit 34 is preferentially performed in the 4-value FSK symbol reproduction circuit 33, and the frequency deviation information is subtracted by the subtractor 502 in the DC offset correction circuit 50 so that the correction does not overlap with the correction by the DC offset correction circuit 50. During the period when the sync pattern is not detected, the sign comparator 340 sets the frequency deviation information to 0, and therefore, the DC offset correction circuit 50 completely functions to correct the local oscillators 223, 243, and the like.

Further, the communication (call) for which the synchronization word pattern is detected uses the frequency deviation information (DC offset) obtained based on the first synchronization word, and continues to use the frequency deviation information (DC offset) until the communication (call) is ended. Further, if the synchronization pattern detection circuit 34 detects a synchronization pattern, the synchronization pattern can be detected by normal symbol regeneration by the 4-value FSK symbol regeneration circuit 33 thereafter, and therefore, the synchronization pattern detection circuit 34 does not perform detection processing for the synchronization pattern until the end of the communication (call). Therefore, since reception is performed when there is a frequency deviation, the phase characteristics in the band-pass filter 224 or the low-pass filters 245, 246, 27, and 28 are inferior to those in the correction operation performed by the DC offset correction circuit 50, but since a synchronization pattern can be detected, a signal that can be successfully demodulated is input to the 4-value FSK symbol reproduction circuit 33, and there is no error and no problem in the symbol data after reproduction.

Returning to fig. 13, the contents of the shift registers 331-1 to 3 are introduced into the shift registers 334-1 to 3, respectively, at the time of the symbol clock generated by the timer 333 via the gate circuit 332. Therefore, the sample values at the sample point T2 near the ideal symbol point P and the sample points T1 and T3 before and after the ideal symbol point P shown in fig. 14 are stored in the shift registers 334-2, 334-1, 334-3. The sample value at the sample point T2 is input to the sign determination unit 335, and the sign value of the actual sign point P estimated from the sample value at the sample point T2 is determined to be most likely any one of the "00", "01", "10", and "11", and the determination result is output to the frame generation circuit 35 as the 2-bit and 2.4ksps signal.

The ideal amplitude level of the sign value corresponding to the determination result is output from the sign determination unit 335, and the ideal amplitude level is subtracted from the contents stored in the shift registers 334-1 to 3 by the subtractors 336-1 to 3. Of the subtraction results, i.e., the magnitudes of the errors (differences) with the ideal amplitude levels V1 to V3, the magnitudes of the errors V1 and V3 of the sample values at the shift registers 334-1 and 3, i.e., the sample points T1 and T3, are input to the selector 337, and it is determined which error is large. Then, the smaller error, i.e., sample point T3 in fig. 14, is output to the timing correction circuit 338 as data (index) in the direction in which the sample point T2 should be moved.

On the other hand, the magnitude V2 of the error in the subtractor 336-2 is input to the time correction circuit 338 as data of a correction amount, and the time correction circuit 338 combines the data of a sign as a correction direction with a count value of the data corresponding to the correction amount, and outputs the result as a time control signal to the timer 333 via a loop filter 339. The loop filter 339 includes a low-pass filter such as an IIR filter, and the larger the time constant is, the more stable the symbol clock is, and the smaller the time constant is, the better the followability of the symbol clock is.

The timer 333 includes a free-running counter (free-running counter) such as a digital VCO, whose oscillation frequency is set to a symbol frequency, and when a symbol period (symbol timing) is reached, an overflow portion is removed and the counter starts a counting operation again after the reset. Also, the symbol timing is a timing at which the phase of the digital VCO passes 0 °. For example, if 0 to 360 ° (1 symbol period) of the phase of the VCO is made to correspond to the count value of 0 to 30000 of the counter, the timer 333 adds 3000 to each oversampling point T, so that a symbol clock in which a symbol value at a symbol rate of 2.4ksps can be sampled can be reproduced from 24ksps of oversampled data.

In the case of fig. 14, the timer 333 initially sets the count value at the time when the phase of the digital VCO is 0 ° to 500, and advances the next symbol clock by an amount corresponding to the error V2 at the sample point T2, for example, by 500 counts, with the direction of the sample point T3, i.e., the direction of advance, as the correction direction. Accordingly, only during the period when the timer 333 counts 500 times, the symbol timing is accelerated, and the next sampling point T2 is close to the actual symbol point P. Specifically, if the 500 count values are corrected during the repetition of the counting operation, the timer 333 overflows (overflows) at 30500, and at this time, the timer is reset, and the correction value 500 at this time is added to the 500 excluding the overflow portion, and then the counting operation is restarted, and the next time the counting operation overflows at 31000. Thus, when the total correction value reaches 3000, the sampling timing is accelerated by 1 sample.

Fig. 15 shows a case where the initial value is set to a negative value and the symbol time is delayed as an example of the counting operation of the timer 333. By increasing the maximum value of the timer 333, the resolution is improved, and by increasing the sampling rate of oversampling, the correction accuracy is improved. Further, when the error V2 at the sampling point T2 is smaller than a specified value, stability can be improved by providing a dead-band (dead-band) in which the above-described timing correction is not performed. The timer 333 is also configured to forcibly reset to 0 at the timing of detecting the synchronization pattern based on the reset signal output from the sign comparator 340 of the synchronization pattern detection circuit 34, and to restart the counting operation.

As described above, the 4-value FSK symbol reproduction circuit 33 of the present embodiment obtains the differences V1 to V3 from the shift registers 331-1 to 3, the gate circuit 332, the shift registers 334-1 to 3, the symbol determination unit 335, and the subtractors 336-1 to 3 constituting the arithmetic unit, for the symbol data of 3 points, i.e., the sampling point T2 close to the symbol point P and the sampling points T1 and T3 before and after the sampling point P, among the symbol data obtained by oversampling the demodulation signal at a frequency higher than the symbol clock, and selects the measurement point having a smaller difference V1 and V3 among the sampling points T1 and T3 before and after the symbol point P by the selector 337 as the selection unit, in order to sample the demodulation signal at a predetermined symbol point and reproduce the demodulation data based on the amplitude value of the obtained symbol data, the timing correction circuit 338 shifts the sampling timing of the next symbol point of the self-running timer 333 by a time corresponding to the difference V2 at the sampling point T2 to the sampling point T3 side selected by the selector 337.

Therefore, for example, in the case of a 4-value modulation wave of "00", "01", "10", and "11", even when there is no transition between "00" and "01" or "10" and "11" with an intermediate value therebetween, or even when there is a transition between "00" and "10" or "01" and "11" with an intermediate value therebetween but the deviation from the intermediate value is uneven, the deviation of the sampling timing is gradually corrected at each oversampling cycle to the maximum. Even if the sampling timing has a large deviation close to 180 °, the direction of the timing to be corrected can be detected. Thus, a stable symbol clock can be reproduced from the multivalued modulated wave. In addition, since the eye diagram does not depend on the aperture ratio (eye), it is easy to cope with the change of the roll-off ratio (roll-off). Further, since the time calculation is performed at 3 points, i.e., the sample point T2 substantially near the symbol point P and the sample points T1 and T3 before and after the sample point P, the calculation amount can be reduced. Such a method of regenerating the symbol clock is not limited to frequency modulation, and can be applied to various modulation methods having an eye pattern such as phase modulation.

Further, since the timer 333 and the loop filter 339 which are self-running are forcibly reset at the detection timing of the synchronization pattern by the synchronization pattern detection circuit 34, a highly accurate symbol clock can be reproduced from the front end of the main data (traffic channel). In addition, at the subtractor 330, the DC offset component is corrected in accordance with the demodulated signal, and therefore, the symbol data obtained at the sampling point T2 can be made close to the ideal amplitude level, so that a more stable clock can be reproduced.

Here, japanese laid-open patent publication No. 2007-150472 discloses a synchronous code detection device that can eliminate a response delay caused by removing a DC offset and reduce erroneous detection even with a small number of synchronous codes, as in patent document 1. According to the synchronization word detection device of the related art, the average value of the errors (differences) between the received synchronization word candidates and the actual synchronization word is used as the offset, the degree of dissimilarity with the actual synchronization word is obtained based on the sum of squares of values obtained by subtracting the offset from the errors, and when the degree of dissimilarity is lower than a threshold value, it is determined that the synchronization word is detected.

However, in this conventional technique, an error is obtained only at each symbol point to obtain an average value. In the present embodiment, the average value of the oversampling values over 10 symbol periods is obtained, and the offset is obtained from the difference from the ideal average value of the synchronization word. Therefore, although the conventional technique has a small number of samples and poor noise immunity, for example, when the sync word is a 10 symbol, the effect of noise is 1/10 in the conventional technique, but in the present embodiment, the effect of noise can be reduced to 1/100 since oversampling is 10 times. In fact, in the conventional technique, the error between the received synchronization word candidate and the actual synchronization word is calculated for each symbol point first, and therefore the load is large, and it is difficult to apply the method to the oversampled data described in the present embodiment.

In the present embodiment, since the DC offset of the received pattern is first corrected and then the correlation with the synchronization pattern is calculated, an extreme difference does not occur between the two, and the correlator 347 may be a product-sum type correlator having a strong noise immunity.

As described above, the present specification discloses various techniques, and the main techniques among them are summarized as follows.

A frame synchronization detecting circuit according to an embodiment of the present invention detects frame synchronization from a received character pattern, and includes: an average value calculation unit for calculating a moving average value of a predetermined number of received word graphs; an offset calculation unit that calculates a DC offset from a difference between an ideal average value of the moving average values of the predetermined number of synchronous word graphs obtained in advance and the moving average value calculated by the average calculation unit; a subtraction unit that subtracts the DC offset from each symbol value of the received word graph; a correlation calculation unit that calculates a correlation between the DC offset corrected reception word pattern in the subtraction unit and the synchronization word pattern; a candidate determination unit that compares the correlation value obtained by the correlation calculation unit with a preset threshold value and identifies the correlation value as a synchronization word candidate when the correlation value is greater than the threshold value; and a final determination unit that compares the received pattern after the DC offset correction with each symbol value of the synchronization pattern when the candidate determination unit has recognized the synchronization pattern candidate, and determines that the synchronization pattern is detected when errors of all symbols fall within a predetermined range.

According to the frame synchronization detecting circuit configured as described above, in the digital radio receiver, when detecting frame synchronization (synchronization code) for sampling a symbol value from a received pattern, first, a moving average value of a predetermined number of received patterns is calculated by the average value calculating unit, and the offset calculating unit calculates a DC offset corresponding to, for example, a frequency correction amount in FSK by calculating a difference between the moving average values of a predetermined number of received patterns as an ideal average value. Next, the DC offset (frequency correction amount) is subtracted from each symbol value of the received pattern in the subtraction unit, and then the correlation with the predetermined synchronization pattern is calculated in the correlation calculation unit. Then, the correlation value as the calculation result is compared with a predetermined threshold value, and when the correlation value is larger than the threshold value, it is not determined that the synchronization word is detected, but the synchronization word is recognized as a synchronization word candidate by a candidate determination unit, and then the symbol values of the received word pattern after the DC offset correction and the synchronization word pattern are compared by a final determination unit, and when errors of all the symbols fall within a predetermined range, it is finally determined that the synchronization word pattern is detected.

Therefore, since the DC offset is removed before the correlation operation (convolution), the threshold for determining the detection of the synchronization word can be strictly defined, and the detection of the synchronization word is not determined based on the result of the correlation operation, but the final detection condition is set such that the errors of all the symbol points fall within a certain range, and thus, the frame synchronization can be established quickly and accurately in the end.

In another embodiment, the frame synchronization detecting circuit further includes a symbol reproducing circuit for reproducing symbol data by sampling a demodulated signal having an amplitude corresponding to a deviation in frequency or phase of the modulated wave at a predetermined timing of the symbol clock, wherein the final determining unit outputs the DC offset obtained by the subtracting unit to the symbol reproducing circuit as frequency deviation information of the demodulated signal when determining that the synchronization pattern is detected.

According to this configuration, the symbol reproduction circuit can determine the symbol value with high accuracy by subtracting the DC offset component from the word graph (demodulated signal).

In another embodiment, the frame synchronization detecting circuit further includes a timer for generating the symbol clock of the symbol reproducing circuit, wherein the final determining unit resets the timer at a time when the synchronization pattern is detected when it is determined that the synchronization pattern is detected.

According to this configuration, the timer for generating the symbol clock for sampling the symbol value in the symbol reproduction circuit is reset in response to detection of the synchronization word pattern, and the symbol clock of the symbol reproduction circuit can be made to coincide with the symbol timing quickly.

In another embodiment, the frame synchronization detecting circuit further includes a loop filter, and the symbol reproducing circuit gives the time correction amount and data of the correction direction of the symbol clock obtained by reproducing the symbol to the timer, wherein the final determining unit also resets the loop filter.

According to this configuration, since the filter of the loop circuit for controlling the symbol clock in the symbol reproduction circuit for stabilization is also reset in accordance with the detection of the synchronization pattern, the symbol clock in the symbol reproduction circuit can be quickly matched with the symbol timing.

In addition, in another embodiment, the FSK receiver uses the synchronization detection circuit for detection of the synchronization word. With this configuration, frame synchronization can be established quickly and with high accuracy.

This application is based on Japanese patent application No. 2008-198885, filed on 31.7.2008, the contents of which are incorporated herein by reference.

In order to describe the present invention, the present invention has been described in detail with reference to the embodiments with reference to the drawings, but it should be understood that modifications and/or improvements can be easily made to the embodiments by those skilled in the art. Therefore, unless otherwise specified, the present invention is not limited to the above embodiments, but may be modified within the scope of the claims.

Industrial applicability

According to the present invention, a frame synchronization detecting circuit and an FSK receiver can be provided.

Claims (5)

1. A frame synchronization detecting circuit for detecting frame synchronization from a received character pattern, comprising:

an average value calculation unit for calculating a moving average value of a predetermined number of received word graphs;

an offset calculation unit that calculates a DC offset from a difference between an ideal average value of the moving average values of the predetermined number of synchronous word graphs obtained in advance and the moving average value calculated by the average calculation unit;

a subtraction unit that subtracts the DC offset from each symbol value of the received word graph;

a correlation calculation unit that calculates a correlation between the DC offset corrected reception word pattern in the subtraction unit and the synchronization word pattern;

a candidate determination unit that compares the correlation value obtained by the correlation calculation unit with a preset threshold value and identifies the correlation value as a synchronization word candidate when the correlation value is greater than the threshold value; and

and a final determination unit that compares the received pattern after the DC offset correction with each symbol value of the synchronization pattern when the candidate determination unit has recognized the synchronization pattern candidate, and determines that the synchronization pattern is detected when errors of all symbols fall within a predetermined range.

2. The frame synchronization detecting circuit according to claim 1, further comprising:

a symbol reproduction circuit for reproducing symbol data by sampling a demodulated signal having an amplitude corresponding to a deviation in frequency or phase of a modulated wave at a timing of a predetermined symbol clock,

the final determination unit outputs the DC offset obtained by the subtraction unit to the symbol reproduction circuit as frequency deviation information of the demodulated signal when it is determined that the synchronization pattern is detected.

3. The frame synchronization detecting circuit according to claim 2, further comprising:

a timer that generates the symbol clock of the symbol regeneration circuit, wherein,

the final determination unit resets the timer at a time when the synchronization word is detected, when it is determined that the synchronization word is detected.

4. The frame synchronization detecting circuit according to claim 3, wherein:

the symbol reproduction circuit further includes a loop filter that gives the timer a time correction amount and data of a correction direction of the symbol clock obtained by reproducing the symbol data;

the final determination unit resets the loop filter at a time when the synchronization word pattern is detected, when it is determined that the synchronization word pattern is detected.

5. An FSK receiver, characterized by:

use of a frame synchronization detection circuit according to any of claims 1 to 4 for detection of the synchronization word pattern.